JP2874453B2 - One-shot multivibrator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-shot multivibrator, and more particularly, to a one-shot multivibrator which requires a high precision output pulse width.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional one-shot multivibrator has a constant voltage source 47, a base connected to a constant voltage source 47, an emitter connected to one end of a resistor R, and a collector connected to a PNP transistor Q1. N connected to collector
A PN transistor Q2, a base connected to the base of the PNP transistor Q1, an emitter connected to the emitter of the PNP transistor Q1, and a P connected to the power supply line.
NP transistor Q3 and one end of PNP transistor Q
Capacitor C connected to the collector of the other end and grounded at the other end.
1, the non-inverting input terminal is connected to the constant voltage source 54, and the inverting input terminal is connected to P
The comparator 55 whose output is connected to the reset input terminal of the D-type flip-flop 56, the gate is connected to the QB output terminal of the D-type flip-flop 56, and the drain is the PNP transistor Q3
, An NMOS transistor N1 whose source is grounded, a trigger input terminal 57 for inputting a trigger signal TRG to a clock input terminal of the D-type flip-flop 56, and a one-shot pulse for the D-type flip-flop 56. It comprises an output terminal 58 for taking out from the Q output terminal. The data input terminal of the D flip-flop 56 is fixed at a high level (H).

The operation of the one-shot multivibrator will be described below with reference to FIG. Here, it is assumed that the clock input of the D-type flip-flop has a valid rising edge and is already in a reset state. In this state, when a rising edge signal is input to the trigger input terminal 57, the output of the D-type flip-flop 56 is inverted and the QB output becomes low level, so that the NMOS transistor N1 is turned off. On the other hand, the terminal voltage of the constant voltage source 47 is applied to the resistor R via the NPN transistor Q2. Therefore, a current determined by Ohm's law flows through the resistor R. If the current amplification factor h _FE of the transistor Q2 is sufficiently large, the current flowing through the resistor R is equal to the current flowing through the collector of the PNP transistor Q1. The PNP transistor Q1 and the PNP transistor Q3 form a current mirror circuit.
The currents flowing through the respective collectors of the transistor Q1 and the PNP transistor Q3 become equal. That is, a current equal to the current flowing through the resistor R is applied to the NMOS transistor N
While the switch 1 is off, the current flows into the capacitor C1 to increase the terminal voltage of the capacitor C1.

[0004] The comparator 55 compares the reference voltage source 54 with the terminal voltage of the capacitor C1, and when the terminal voltage of the capacitor C1 exceeds the voltage of the reference voltage source 54, sets the output to a low level. As a result, the D-type flip-flop 5
6 is reset, and the NMOS transistor N1 turns on again to discharge the electric charge of the capacitor C1, thereby returning to the initial state.

At this time, the one-shot width T ₁ is given by the following equation.

T ₁ = C · V ₂ / I = C · R (V ₂ / V ₁ ) (sec) where C is the capacitance (F) of the capacitor C 1, and R is the resistance value of the resistor R (Ω), V ₁ is the terminal voltage (V) of the reference voltage source 47, V ₂ is the terminal voltage (V) of the reference voltage source 54, I is the current (A) flowing into the capacitor C1, and for simplicity, the transistor When the base-emitter voltage of Q2 is 0
And

[0007]

In the conventional one-shot multivibrator described above, the one-shot width is proportional to the product of the capacitance value of the capacitor C1 and the resistance value of the resistor R. Therefore, the absolute accuracy of the capacitor and the resistor is directly the accuracy of the one-shot width. However, when manufacturing ICs, it is difficult to improve the absolute accuracy of capacitors and resistors. For this reason, it has been difficult for the conventional one-shot multivibrator to improve the accuracy of the one-shot width when integrated into an IC.

[0008]

A one-shot multivibrator according to the present invention comprises a constant current source, a comparator for comparing a reference voltage supplied to a reference voltage input terminal with a voltage at a control input terminal, and an output signal of the comparator. A reset input, a capacitor connected to the control input terminal, and a switching element provided in parallel with the capacitor, and triggered by a clock pulse input from the outside, the charging current to the capacitor A first pulse generating circuit for outputting a first pulse signal having a pulse width corresponding to the first pulse signal to a data output terminal of the flip-flop, a comparator for comparing a reference voltage supplied to a reference voltage input terminal with a voltage at a control input terminal, A flip-flop having the output signal of the comparator as a reset input, a capacitor connected to the control input terminal, and a And a switching element provided in a column, wherein a second pulse signal having a pulse width corresponding to a charging current to the capacitor is triggered by a trigger signal input from the outside, and a second pulse signal as an output signal to the outside is output from the flip-flop. Comparing a pulse width of the first pulse signal with a pulse width of the first pulse signal, the pulse width of the first pulse signal being determined by a current of the constant current source; A which converts and stores a digital signal combination corresponding to the digital signal and outputs an analog current D having a value corresponding to the digital signal combination
A converter and an output terminal of the analog current and an output terminal of the constant current source of the DA converter are connected to a control input terminal of the first pulse generation circuit during the conversion by the DA converter. Switching means for switching and connecting to a control input terminal of the second pulse generation circuit in response to a conversion end signal from the DA converter.

[0009]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the figure, constant current sources 9, 10, 11, 1
2 are NMOS transistors N9, N10, N
11 and N12 are connected to NMOS transistors N2 and N3. In the present embodiment, it is assumed that the following relationship exists between the current values of these four constant current sources.

I ₉ = 2 · I ₁₀ = 4 · I ₁₁ = 8 · I ₁₂ ... The gates of the NMOS transistors N 9, N 10, N 11 and N 12 are D-type flip-flops 17 and 18, respectively.
19 and 20 are connected to Q outputs.

The D-type flip-flops 17, 18, 19,
Reference numeral 20 denotes a clock input terminal connected to the output terminals of the NAND gates 21, 22, 23, and 24 constituting the decoder, and a data input terminal connected to the Q output terminal of the D-type flip-flop 35. . The T-type flip-flops 25, 26, 27
A counter that counts the clock applied through the gate 29 is configured.
26 Q and QB outputs are connected to NAND gates 21 and
2, 23 and 24 are applied to the input terminals and decoded.
In the T-type flip-flop 27, the Q output is connected to the gate of the NMOS transistor N3, and the QB output is connected to the gate of the NMOS transistor N2. QB output terminal
The input terminals of the ND gates 29 and 28 are also connected.

The other end of the NMOS transistor N2 is
The capacitor C2 is connected to the NMOS transistor N4 and the inverting input terminal of the comparator 34. Capacitor C
2. The other end of the NMOS transistor N4 is grounded. The non-inverting input terminal of the comparator 34 has a reference voltage source 3
3 is connected to the reset terminal of the D-type flip-flop 35 at the output terminal. D-type flip-flop 3
5, a clock input terminal is connected to a clock input terminal 5,
The QB output terminal is connected to the gate of the NMOS transistor N4.

The other end of the NMOS transistor N3 is connected to the capacitor C3, the NMOS transistor N5 and the inverting input terminal of the comparator 40. Capacitor C
3. The other end of the NMOS transistor N5 is grounded. The non-inverting input terminal of the comparator 40 has a reference voltage source 3
9 is connected to the reset terminal of the D-type flip-flop 41 at the output terminal. D-type flip-flop 4
1 is connected to the trigger input terminal 47,
The QB output terminal is connected to the gate of the NMOS transistor 38.

The operation of the embodiment will be described below with reference to FIG. It is assumed that the T-type flip-flops 25, 26, and 27 operate at the falling edge of the clock input. Also, as an initial state, the reset input terminal 42
To the reset signal RES, and the circuit is already in a reset state. Capacitor C2, NMOS transistor N4, reference voltage source 33, comparator 34, D
When the first clock CLK after reset is applied to the first one-shot multivibrator constituted by the flip-flop 35 via the clock input terminal, the output of the D-type flip-flop 35 is output at the rising edge of the clock CLK. Is inverted, the QB output becomes low level, and the NMOS transistor N4 is turned off. During this period, the current I ₈ of the constant current source 8 raises the terminal voltage of the capacitor C2 flows into the capacitor C2 through the NMOS transistor N2.

The comparator 34 compares the reference voltage source 33 with the terminal voltage of the capacitor C2, and sets the output to a low level when the terminal voltage of the capacitor C2 exceeds the voltage of the reference voltage source 33. As a result, the D-type flip-flop 3
5 is reset, and the NMOS transistor N4 is turned on again to discharge the charge of the capacitor C2, thereby returning to the initial state. Accordingly, Q output of D-type flip-flop 35 becomes high for a time T ₂ determined by the current flowing through the capacitor C2 and the NMOS transistor N4 as follows.

T ₂ = C ₂ · V ₃ / I (sec) where C ₂ is the capacitance (F) of the capacitor C ₂ , V ₃ is the terminal voltage (V) of the reference voltage source 33, and I is the capacitor C 2 Represents the current (A) flowing into.

On the other hand, the Q outputs of the T-type flip-flops 25 and 26 are low, the QB output is high, and the AND gate 2
8, when the clock CLK is applied, the output of the NAND gate 21 goes low while the clock is high. When the clock CLK changes from high to low, the output of the NAND gate 21 changes from low to high.
The state of the Q output of the type flip-flop 35 is read into the D-type flip-flop 17.

[0018] Here, the fact that the state of the Q output of the D-type flip-flop 35 is high, the clock CLK is meant that more of the output width T ₂ of the one-shot is longer than the period is high. In this case, the D-type flip-flop 17
Is read high, the NMOS transistor N
9 turns on, the current flowing into the capacitor C2 increases,
Output width T ₂ of the one-shot is shortened. Conversely, the state of the Q output of D-type flip-flop 35 that is low, the clock CLK is meant that towards the output width T ₂ of the one-shot is shorter than the period is high. in this case,
When a row is read into the D-type flip-flop 17, the NMOS transistor N9 remains off.

Next, when the second clock CLK is applied, D is applied in the same manner as when the first clock CLK is input.
The Q output of the flip-flop 35 goes high for a fixed time. On the other hand, the Q output of the T-type flip-flop 25 is high, the QB output is low, and the D-type flip-flop 26
Is low and the QB output is high. Therefore, AN
When the clock CLK is applied via the D gate 28,
This time, the output of NAND gate 22 goes low. Therefore, when the clock CLK changes from high to low, the state of the Q output of the D flip-flop 35 is read into the D flip-flop 18.

If the output width of the one-shot is longer than the period during which the clock CLK is high, a high value is read into the D-type flip-flop 18 and the NMOS transistor N1
0 turns on, and the current flowing into the capacitor C2 increases. However, since the current I ₁₀ of the constant current source 10 is half the current I ₉ of the constant current source 9, the degree of output width of the one-shot is shortened to half the time of the first clock CLK. Conversely, when the output width of the one-shot is shorter than the period in which the clock CLK is high, a low level is read into the D-type flip-flop 18, so that the NMOS transistor N10 remains off.

In the same manner, the one-shot width changes in the same manner as the third clock and the fourth clock, and finally, the one-shot output width expected to be the period T during which the clock CLK is high is assumed. T _{a for} short, T _{b for} long
Becomes the following relationship.

T _a <T <T _b ... Where T _a = C ₂ .V ₃ / (i + I ₁₂ ) and T _b = C _2.
V ₃ / i, i is the current flowing into the capacitor C 2 when the fourth clock is applied, and I ₁₂ is the current of the constant current source 12. Since the maximum value of i is (I ₉ + I ₁₀ + I ₁₁ ), from the equation, i = I ₈ + I ₉ + I ₁₀ + I ₁₁ = I ₈ + 14 · I ₁₂ Therefore, the one-shot for the period when the clock CLK is high is The output width error e is

[0023]

Therefore, T and (C ₂ · V ₃ / I) are equal to the error e
Range.

Next, when the fifth clock is applied,
Since the Q output of the D flip-flop 27 goes low and the QB output goes high, a low is input to the AND gates 29 and 28, and the NAND gates 21, 22, 23 and 24 and the T flip-flops 25, 26, The clock CLK is no longer applied to 27 and no longer operates. Also, the NMOS transistor N2 is turned off, and the NMOS transistor N2 is turned off.
The transistor N3 turns on.

For this reason, the current that has flowed through the NMOS transistor N2 until now flows through the NMOS transistor N3 after the fifth clock, so that the capacitor C3, the NMOS transistor N5, the reference voltage source 39, the comparator The second one-shot multivibrator composed of the D-type flip-flop 41 operates. Shot width T3 of the one-shot _{multivibrator, T 3 = C 3 · V} 4 / I = C 3 · V 4 / (C 2 · V 3 / T) ····· However, C ₃ are capacitors C3 , V ₄ is the terminal voltage (V) of the reference voltage source 39.

From the equations, C ₂ and C ₃ , and V ₃ and V ₄
From the result of the equation, the error e
And higher accuracy can be obtained as compared with the conventional one-shot multivibrator.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. In this embodiment, the NMOS transistor N4, the reference voltage source 33, the comparator 34, and the D-type flip-flop 35 are common to the first one-shot multivibrator and the second one-shot multivibrator in the first embodiment. , NMOS transistor N
2, N3, the capacitors C2 and C3 are switched. In FIG. 2, since the QB output of the T-type flip-flop 27 is high until the fifth clock is input after the reset, the NMOS transistor N2 turns on and the capacitor C2 is selected. During this time, the current flowing through the NMOS transistor N2 changes according to the capacitor C2. After the fifth clock, the D flip-flop 2
7, the Q output becomes high, and the NMOS transistor N3 is turned on, so that the capacitor C3 is selected and normal operation is performed. In the present embodiment, since the first one-shot multivibrator and the second one-shot multivibrator are shared, there is an advantage that the number of elements can be reduced.

In the above two embodiments, the clock CL
Although the K counter has two bits, if the number of bits is further increased, the accuracy of the one-shot pulse width can be improved in proportion to the number of bits.

[0030]

As described above, the present invention provides a first one-shot multivibrator for setting a pulse width,
A second one-shot multivibrator for output is provided, and the first one-shot multivibrator is controlled by using a DA converter such that the output width matches the pulse width of a reference frequency signal input from the outside. When the necessary charging current value is stored and the one-shot pulse is output to the outside, the second one-shot multivibrator for output is operated using the stored current. Has an effect that the pulse width can be determined accurately.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional one-shot multivibrator.

[Explanation of symbols]

5 Clock input terminal 8, 9, 10, 11, 12 Constant current source 17, 18, 19, 20, 35, 41, 56 D-type flip-flop 21, 22, 23, 24 NAND gate 25, 26, 27 T-type flip-flop 28,29 AND gate 33,39 Reference voltage source 34,40,55 Comparator 42 Reset input terminal 47,54 Constant voltage source 57 Trigger input terminal 58 Output terminal

Claims (3)

(57) [Claims] 1. A constant current source, a comparator for comparing a reference voltage applied to a reference voltage input terminal with a voltage at a control input terminal, a flip-flop having an output signal of the comparator as a reset input, and a control input terminal. A first pulse signal having a pulse width corresponding to a charging current to the capacitor, the first pulse signal being triggered by a clock pulse input from the outside, the flip-flop being provided with a connected capacitor and a switching element provided in parallel with the capacitor; A first pulse generating circuit for outputting to a data output terminal of the flip-flop, a comparator for comparing a reference voltage supplied to a reference voltage input terminal with a voltage of a control input terminal, and a flip-flop having an output signal of the comparator as a reset input And a capacitor connected to the control input terminal, and a switching element provided in parallel with the capacitor. A second pulse generating circuit that is triggered by a trigger signal to output a second pulse signal having a pulse width corresponding to the charging current to the capacitor to the data output terminal of the flip-flop as an external output signal; The pulse width of the first pulse signal determined by the current of the current source is compared with the pulse width of the clock pulse, converted into a combination of digital signals corresponding to the pulse width of the first pulse signal, and stored. A DA converter that outputs an analog current having a value corresponding to a combination of digital signals; and an output terminal of the analog current and an output terminal of the constant current source of the DA converter, wherein the first terminal is used during the conversion by the DA converter. Connected to the control input terminal of the pulse generation circuit, and after the end of the conversion, in response to the conversion end signal from the DA converter, Switching means for switching to and connecting to a control input terminal of the second pulse generating circuit. 2. A constant current source, a comparator for comparing a reference voltage supplied to a reference voltage input terminal with a voltage at a control input terminal, a flip-flop having an output signal of the comparator as a reset input,
A first capacitor connected to the control input terminal via the switching element, a second capacitor connected to the control input terminal via a second switching element, and a switching connected to the control input terminal. A pulse generation circuit that outputs a pulse signal having a pulse width corresponding to a charging current to a capacitor to a data output terminal of a flip-flop; and a pulse width of the pulse signal determined by a current of the constant current source is externally provided. The pulse signal is compared with the pulse width of the clock signal, converted to a combination of digital signals corresponding to the pulse width of the pulse signal and stored, and an analog current having a value corresponding to the combination of the digital signals is controlled by the control of the pulse generation circuit. A DA converter for outputting to a current output terminal connected to an input terminal; and A first switching element is turned on, and an input terminal of the clock pulse is connected to a clock input terminal of a flip-flop of the pulse generation circuit. After the conversion is completed, the second switching element of the pulse generation circuit is turned on. And a switching means for switching an input terminal of an external trigger signal to a clock input terminal of a flip-flop of the pulse generating circuit for connection. 3. The one-shot multivibrator according to claim 1, wherein the DA converter is a counter that counts the number of input pulses of the clock pulse, a decoder that decodes an output signal of the counter, An output signal for each bit of the decoder is used as a clock input, and a first pulse output from the first pulse generation circuit is output.
A D-type flip-flop having a data signal of a pulse signal output from the pulse generation circuit or at least one constant current source; and a constant current source provided between the constant current source and the analog current output terminal. The conduction state is D
A constant current source circuit having a switching element controlled by a data output of a flip-flop, wherein the switching means is operated by an output signal of the last bit of the counter.