JPH0145250B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer circuit that reduces fluctuations due to changes in ambient temperature.

Figure 1 shows a timer signal obtained by charging and discharging a time constant circuit consisting of a resistor and a capacitor.
FIG. 2 is a configuration diagram of a conventional timer circuit, and FIG. 2 is a waveform diagram showing signal waveforms at each part thereof. When a high level signal IN is applied from the outside to the set input terminal S of the set-reset type flip-flop 1, the flip-flop 1 is set and its output falls to a low level. As a result, the transistor 2 is turned off, the capacitor 5 is charged via the resistor 4 of the time constant circuit 3 , and the terminal potential V _I of the capacitor 5 gradually increases as shown in FIG. When this potential V _I reaches the reference potential V ₀ obtained by dividing the constant voltage Vcc by a pair of resistors 5 and 6, the output of the voltage comparator 7 is inverted to a high level and the flip-flop 1 is reset. . flipflop 1
When the output rises to a high level due to the reset, transistor 2, which had been off until now, turns on, stopping charging of capacitor 5, and the charge that had been stored in capacitor 5 is discharged via transistor 2. be done. and the above signal
Since the period from when IN is input until charging of capacitor 5 is stopped is constant, for example, during this period, flip-flop 1, which is at a high level,
The Q output of is used as the timer signal OUT, and the output time (pulse width) T of this signal is expressed by the following equation.

T=C・R・lnVcc/V ₀ −V _CE(sat) ...(1) where C is the capacitance of capacitor 5, R is the resistance value of resistor 4, and V _CE(sat) is the voltage between the collector and emitter of transistor 2. This is the saturation voltage.

By the way, as is clear from the above equation (1), the output time T of the timer signal OUT is influenced by the collector-emitter saturation voltage V _{CE (sat)} of the transistor 2.
That is, this voltage V _{CE (sat)} becomes the initial value of the voltage V _I , as shown in FIG. However, since this voltage V _{CE (sat)} fluctuates due to changes in ambient temperature, there is a drawback that an error occurs in the output time T of the timer signal OUT.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a timer circuit that can obtain highly accurate timer signals with little error.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of a timer circuit according to the present invention. In the figure, a constant voltage of positive polarity Vcc
Three resistors 11 are connected between the application point and the ground potential point.
-13 are inserted in series, this voltage Vcc is divided by these three resistors 11-13, and the first reference potential _V1 is applied to the connection point of resistors 11 and 12, and the first reference potential V1 is applied to the connection point of resistors 12 and 13. A second reference potential V ₂ is obtained at each point. The lower second reference potential V ₂ is then supplied to the positive (+) side input terminal of the voltage comparator 14 .

Further, a resistor 15, a collector and an emitter of an NPN transistor 16, and a capacitor 17 are inserted in series in this order between the Vcc application point and the ground potential to form a charging circuit for the capacitor 17.
The terminal potential V ₃ of this capacitor 17 is supplied to the negative (-) side input terminal of the voltage comparator 14 . Further, a discharge resistor 18 is connected between both ends of the capacitor 17.

A current source 19 is inserted between the base of the transistor 16 and the Vcc application point, and this current source 19
A PNP transistor ₂₀ , whose base is supplied with the higher first reference potential V1, is inserted between the emitter and collector of the PNP transistor 20 and the ground potential.
Further, the collector and emitter of an NPN transistor 21 are connected in parallel between the emitter and collector of this transistor 20.

The base of the transistor 21 is supplied with the Q output of a set-reset type flip-flop 22 which uses an external signal IN as a set S input and the output of the voltage comparator 14 as a reset R input. Further, the output of this flip-flop is supplied to the outside via an inverter 23 as a timer signal OUT.

The voltage comparator 14 compares the second reference potential V ₂ supplied to its positive input terminal with the terminal potential V ₃ of the capacitor 17 supplied to its negative input terminal,
When V ₃ is higher than V ₂ , a low level signal is output, and after V ₃ and V ₂ match, the output is inverted to high level.

Next, the operation of the circuit configured as described above will be explained in the fourth section.
This will be explained with reference to the waveform diagram shown in the figure.

First, when the signal IN is not input to the flip-flop 22 and the flip-flop 22 is reset, the Q output is at a low level, so the transistor 21 is turned off. Therefore, current source 1
Transistor 16 is turned on by the current from 9, and capacitor 17 is charged. At this time, since the base potential of the transistor 20 is V ₁ ,
Terminal potential of capacitor 17 when charging is completed
V ₃ is expressed by the following formula.

V ₃ =V ₁ +V _BE20 +V _BE16 (2) However, the above V _BE20 and V _BE16 are the voltages between the base and emitter of the transistors 20 and 16, respectively.
Here, since V _BE20 and V _BE16 are almost equal, the potential V ₃ at the time of completion of charging is the first reference potential V ₁
It's getting old. Therefore, at this time, the output of the voltage comparator 14 is at a low level, the flip-flop 22 remains in the reset state, and the timer signal OUT also remains at a low level.

Next, the flip-flop 22 receives a high level signal.
When IN is input, the flip-flop 22 is set and its Q output rises to a high level, and the timer signal OUT also rises to a high level. When the Q output rises to a high level, the transistor 21, which has been in the off state, is turned on, the current from the current source 19 flows through this transistor 21, and the transistor 16, which has been in the on state, is turned off. When the transistor 16 is turned off, the charges that have been stored in the capacitor 17 are discharged through the resistor 18, so that the terminal potential _V3 of the capacitor 17 gradually decreases as shown in FIG. Then, when the above potential V ₃ matches the second reference potential V ₂ , after this,
The output of voltage comparator 14 is inverted to a high level and flip-flop 22 is reset. By resetting the flip-flop 22, the Q
The output returns to low level and the timer signal OUT also returns to low level. When the Q output of the flip-flop 22 becomes low level, the transistor 21, which has been on, turns off and the transistor 16 turns on, so that the capacitor 17 is rapidly charged and its terminal potential _V3 returns to _V1 .

Here, the output time T ₀ of the timer signal OUT is expressed by the following equation.

T ₀ = C ₀ · R ₀ · lnV ₃ /V ₂ ...(3) where C ₀ is the capacitance of capacitor 17, R ₀ is the resistance value of resistor 18, and resistors 11, 12, 13
If the resistance values of are R ₁₁ , R ₁₂ , and R ₁₃ , V ₂ and V ₃ are respectively expressed as follows.

V ₂ = Vcc・R ₁₃ /R ₁₁ +R ₁₂ +R ₁₃ ……(4) V ₃ =Vcc・(R ₁₂ +R ₁₃ )/R ₁₁ +R ₁₂ +R ₁₃ ……(5) In other words, the output time of the timer signal OUT T ₀ is
The terminal potential V ₃ of the capacitor 17 when the transistor 16 is on (substantially the first reference potential
V ₁ ) and the second reference potential V ₂ and the capacitor 17
is determined by the capacitance C ₀ of the resistor 18 and the resistance value R ₀ of the resistor 18. That is, the accuracy of T ₀ depends on each of the above-mentioned potentials and values. Here, the first and second reference potentials V ₁ and V ₂ are obtained by the resistance ratio of the resistors 11, 12, and 13, so they hardly change with respect to changes in ambient temperature, and when the transistor 16 is off, the V ₃ is obtained by applying the first reference potential V ₁ between the bases and emitters of the transistors 20 and 16 of different polarities, so this also has a value equal to V ₁ regardless of the ambient temperature. Therefore, if high-precision capacitors 17 and resistors 18 are used as external components when this circuit is integrated, the fluctuations in the output time T ₀ of the timer signal OUT due to ambient temperature changes will be small. Therefore, it is possible to achieve high precision with little error.

It goes without saying that this invention is not limited to the above-mentioned embodiment, and that various modifications are possible. For example, in the above embodiment, the timer signal
The case where OUT is obtained by inverting the output of flip-flop 22 by inverter 23 has been explained, but in this case, the Q output itself may be used as a timer signal, and the level at output time T ₀ must be low. If there is, the output may be used as a timer signal.

As explained above, according to the present invention, it is possible to provide a timer circuit that can obtain a highly accurate timer signal with little error.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional timer circuit, Fig. 2 is a waveform diagram showing signal waveforms of each part, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 shows signal waveforms of each part. FIG. 11, 12, 13, 15, 18...Resistance, 14
... Voltage comparator, 16, 21 ... NPN transistor, 17 ... Capacitor, 19 ... Current source, 2
0...PNP transistor, 22...Set-reset type flip-flop, 23...Inverter.

Claims (1)

[Claims] 1 means for obtaining first and second reference potentials having different values, a capacitor whose one end is connected to the ground voltage, and a first capacitor whose collector and emitter are inserted between the power supply voltage and the other end of the capacitor. a polar first transistor, a current source inserted between a power supply voltage and a base of the first transistor, and a collector and an emitter inserted between the base of the first transistor and a ground voltage. a second transistor of a second polarity to which the first reference potential is applied to its base; a potential comparison circuit that compares the potential at the other end of the capacitor with the second reference potential; A flip-flop circuit is set and reset by the output signal of the potential comparison circuit, and current switch means causes the current of the current source to flow to the ground voltage by the set output of the flip-flop circuit. A timer circuit configured to obtain a signal.