JPH05232149A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To realize a peak holding circuit, wherein the output change caused by noises is less even if noises in a short time are inputted into a signal, and therefore the effect of the noises is less. CONSTITUTION:The non-inverted input terminal of an operation amplifier 2 is connected to an input terminal 1. The inverted input terminal is connected to the source of an N-channel MOS transistor 4, an output terminal 3 of a peak holding circuit, a holding capacitor 5 and a discharging resistor 6. The output terminal is connected to the N-channel MOS transistor 4. The other ends of the holding capacitor 4 and the discharging resistor 5 are grounded. A constant current source 7 is connected to the drain of the N-channel MOS transistor 4. The other end of the constant current source 7 is connected to a power supply terminal 8 and an external power supply 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit, and more particularly to a peak hold circuit suitable for semiconductor integrated circuits.

[0002]

2. Description of the Related Art In a conventional peak hold circuit, as shown in FIG. 4, an operational amplifier 2 having a non-inverting input terminal connected to an input terminal 1 and an inverting input terminal connected to a holding capacitor 5, and an operational amplifier having a gate. An N-channel MOS transistor 4 whose source is connected to the holding capacitor 5 and whose drain is connected to the constant voltage source 9, the holding capacitor 5 whose other terminal is grounded, and the holding capacitor 5 are connected in parallel to the output of 2. And a resistor 6. Reference numeral 8 is a power supply terminal, and 3 is a peak hold circuit output terminal. When the voltage of the input terminal 1 is lower than the voltage of the holding capacitor 5, the output voltage of the operational amplifier 2 becomes low, the N-channel MOS transistor 4 turns "off", and the voltage of the holding capacitor 5 is held. If the voltage of the input terminal 1 is higher than the voltage of the holding capacitor 5,
The output voltage of the operational amplifier 2 becomes high and the N channel MO
The S transistor 4 is turned “on”, a charging current flows through the holding capacitor 5, and charging continues until the voltage of the holding capacitor 5 becomes equal to the voltage of the input terminal 1. The resistor 6 connected in parallel with the holding capacitor 5 is a resistor that determines the discharge time constant.

[0003]

In the conventional peak hold circuit, when a noise larger than the input signal is input, a charging current determined by the "on" resistance of the transistor 4 flows, and the peak noise is generated as shown by the broken line in FIG. Holds the level.
This hinders holding the peak level of the signal. Therefore, if a resistor 61 is connected between the source of the transistor 4 and the terminal 3 as shown in FIG. 6, for example, the problem of holding the peak level of noise is improved. However, when the resistance in the integrated circuit is used, the variation is large as ± 20% as a typical example, and the demand for the accuracy of the charging current may not be satisfied. If the resistor 61 is an external resistor, the accuracy will be improved, but it is necessary to increase the number of terminals by one, and if there are many peak hold circuits, the increase in the number of terminals becomes a particular problem.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel peak hold circuit capable of solving the above problems inherent in the conventional art. Especially.

[0005]

In order to achieve the above object, a peak hold circuit according to the present invention comprises an input terminal,
A holding capacitor; an operational amplifier having a non-inverting input terminal connected to the input terminal and an inverting input terminal connected to the holding capacitor; and a switch controlled by the output of the operational amplifier and having an output terminal connected to the holding capacitor. The peak hold circuit has a constant current source connected to the input terminal of the switch.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a circuit configuration diagram showing a first embodiment of a peak hold semiconductor integrated circuit according to the present invention.

Referring to FIG. 1, the input terminal 1 is the non-inverting input terminal of the operational amplifier 2, the output terminal of the operational amplifier 2 is the gate of the N-channel MOS transistor 4, and the inverting input terminal is the N-channel MOS transistor 4. And the peak hold circuit output terminal 3 are respectively connected. The drain of the N-channel MOS transistor 4 is the output terminal of the constant current source 7, the input terminal of the constant current source 7 is the power supply terminal 8, the power supply terminal 8 is the external power supply 9, and the peak hold circuit output terminal 3 has the other end. The holding capacitor 5 and the discharging resistor 6 which are grounded are connected to each other.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG.
A description will be given based on the waveform diagram of.

The input voltage of the input terminal 1 is the holding capacitor 5
When the voltage becomes higher than the voltage of 1, the output voltage of the operational amplifier 2 becomes higher, the transistor 4 turns on, and the current of the constant current source 7 flows into the holding capacitor 5. If the current of the constant current source 7 is I and the capacity of the holding capacitor 5 is C, the voltage of the holding capacitor 5, that is, the output voltage of the peak hold circuit is dV / d.
It rises with a slope of T = I / C. The durations of the signal and noise are set to T1 and T2, respectively, and when T1 << T2, the output voltage of the peak hold circuit due to the signal and noise is respectively V
1, V2 is V1 >> V2. Therefore, even if noise is input for a short time as compared with the signal, the output voltage rises only slightly as shown by the broken line in FIG. Does not interfere with holding the level.

In FIG. 2, instead of the constant current source 7 of FIG.
It is a circuit block diagram which shows the 2nd Example by this invention when the current mirror which consists of channel MOS transistors 21 and 22, and the constant current source 23 is used, and the operation | movement of this 2nd Example is the same as that of FIG. is there. Since the circuits of FIGS. 1 and 2 have a constant current source inside the integrated circuit, when the accuracy of the charging current is strict, trimming or the like is used to reduce the variation of the constant current due to the variation of the resistance. It needs to be corrected.

FIG. 3 is a circuit configuration diagram showing a third embodiment of the present invention.

Referring to FIG. 3, the input terminal 1 is the non-inverting input terminal of the operational amplifier 2 and the output terminal of the operational amplifier 2 is N.
The inverting input terminal is connected to the gate of the channel MOS transistor 31 and to the drain of the P-channel MOS transistor 33 and the peak hold circuit output terminal 3, respectively. The drain of the N-channel MOS transistor 31 is connected to one end of the resistor 32 and the gate of the P-channel MOS transistor 33.
Are connected to the drains of the P-channel MOS transistors 34, respectively. The inverting input terminal of the operational amplifier 36 is the constant voltage source 37, and the non-inverting input terminal is the external resistor terminal 38 and the P-channel MOS transistor 35.
Of the P-channel MOS transistors 34 and 35 is connected to the output terminal thereof. External resistor 39 grounded to external resistor terminal 38
However, the other end of the resistor 32 and the P channel MOS are connected to the power supply terminal 8.
The sources of the transistors 34 and 35 are connected to the external power supply 9, respectively. Peak hold circuit output terminal 3
Holding capacitor 5 and discharge resistor 6 whose other end is grounded
Are connected to each other.

Next, the operation of the circuit shown in FIG. 3 will be described. If the voltage of the constant voltage source 37 is V and the resistance value of the external resistor 39 is R, and the P-channel MOS transistors 34 and 35 are transistors of the same shape, the current flowing through the holding capacitor is V / R. Variations in the voltage of the constant voltage source can be reduced, and the external resistor 39
Since it is more accurate than the resistance in the integrated circuit, it is possible to reduce the variation in the constant current, and thus to improve the accuracy of the charging current. Further, even if there are many peak hold circuits, one external resistor can be used by increasing the number of outputs of the current mirror circuit, so the number of pins does not increase. Further, in the third embodiment, the transistor 33 which inverts the signal of the operational amplifier 2 by the transistor 31 to control the charging current to the holding capacitor 5 is a P-channel MOS transistor, so that the threshold value due to the substrate bias effect is obtained. The increase of the voltage VT is prevented and the dynamic range of the peak hold circuit is widened.

[0015]

As described above, according to the present invention,
By charging the holding capacitor with a constant current source, even if short-term noise is introduced to the signal, the change in the peak hold circuit output due to noise is small, and thus a peak hold circuit that is less affected by noise can be realized. it can.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a peak hold circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of a peak hold circuit according to the present invention.

FIG. 3 is a circuit configuration diagram showing a third embodiment of a peak hold circuit according to the present invention.

FIG. 4 is a circuit diagram showing a first example of a conventional peak hold circuit.

FIG. 5 is an input / output waveform diagram of the peak hold circuit.

FIG. 6 is a circuit diagram showing a second example of a conventional peak hold circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2, 36 ... Operational amplifier 3 ... Peak hold circuit output terminal 4, 31 ... N-channel MOS transistor 5 ... Holding capacitor 6 ... Discharge resistor 7, 23 ... Constant current source 8 ... Power supply terminal 9 ... External power supply 21 , 22, 33 to 35 ... P-channel MOS transistor 37 ... Constant voltage source 38 ... External resistance terminal 39 ... External resistance

Claims (2)

[Claims] 1. An input terminal, a holding capacitor, an operational amplifier having a non-inverting input terminal connected to the input terminal and an inverting input terminal connected to the holding capacitor, and the holding capacitor controlled by the output of the operational amplifier. A peak-hold circuit having a switch having an output terminal connected to the output terminal, wherein a constant current source is connected to an input terminal of the switch. 2. The constant current source is replaced by a current mirror circuit, and a second constant current source connected between the current mirror circuit and ground is used. Peak hold circuit.