JP2008125018A - Surround control circuit - Google Patents

Surround control circuit Download PDF

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JP2008125018A
JP2008125018A JP2006309625A JP2006309625A JP2008125018A JP 2008125018 A JP2008125018 A JP 2008125018A JP 2006309625 A JP2006309625 A JP 2006309625A JP 2006309625 A JP2006309625 A JP 2006309625A JP 2008125018 A JP2008125018 A JP 2008125018A
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surround
control circuit
circuit
smoothing capacitor
voltage
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JP4970002B2 (en
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Hideyuki Nakasone
秀幸 中曽根
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To attain click noise reduction while eliminating the need of a particular capacitor for click noise reduction. <P>SOLUTION: In a surround control circuit comprising a first control circuit which includes a smoothing capacitor C1 for smoothing a voltage resulting from rectifying an audio signal and outputs a voltage Vcont generated in the smoothing capacitor C1 as a surround effect control signal for setting a strength of surround effect and a second control circuit which operates a comparator circuit 4 by changing a comparative potential by controlling ON/OFF of a switch SW and sets a state of surround mode in accordance with an output of the comparator circuit 4, the smoothing capacitor C1 and a current source I2 discharging an electric charge of the smoothing capacitor are connected to a node N where the comparative potential is generated, respectively. While the switch SW is OFF, the output of the comparator circuit 4 is set so as to bring the surround mode into active state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、スピーカから発生する可聴帯域の切替音であるボツ音の低減を図ったサラウンド制御回路に関するものである。   The present invention relates to a surround control circuit that reduces the audible noise that is an audible band switching sound generated from a speaker.

図3にボツ音低減を図った従来のサラウンド制御回路の構成を示す。10はサラウンド回路(図示せず)でのサラウンド効果の強弱を決定するサラウンド効果制御電圧Vcontを生成する第1の制御回路、20はサラウンド回路でのサラウンドモードの動作/非動作状態を切り替える第2の制御回路である。   FIG. 3 shows the configuration of a conventional surround control circuit designed to reduce the noise. Reference numeral 10 denotes a first control circuit that generates a surround effect control voltage Vcont that determines the strength of the surround effect in the surround circuit (not shown), and reference numeral 20 denotes a second circuit that switches the operation mode / non-operation state of the surround mode in the surround circuit. This is a control circuit.

第1の制御回路10において、入力するオーディオ信号Vinは、抵抗R0を介して電圧/電流変換回路1に入力して電流信号に変換され、整流回路2で整流され、平滑回路3で平滑される。この平滑回路3では、平滑用コンデンサC1に保持される電圧が抵抗R1に発生する電圧のピーク値となるように、演算増幅器OPとトランジスタQ1が動作し、その平滑用コンデンサC1に発生するサラウンド効果制御電圧Vcontがサラウンド回路に供給される。電流源I2は平滑用コンデンサC1に蓄積された電荷の放電用である。平滑用コンデンサC1は比較的大きな容量値が要求されるので、半導体集積回路では外付けとなる。   In the first control circuit 10, the input audio signal Vin is input to the voltage / current conversion circuit 1 through the resistor R 0, converted into a current signal, rectified by the rectification circuit 2, and smoothed by the smoothing circuit 3. . In the smoothing circuit 3, the operational amplifier OP and the transistor Q1 operate so that the voltage held in the smoothing capacitor C1 becomes the peak value of the voltage generated in the resistor R1, and the surround effect generated in the smoothing capacitor C1. A control voltage Vcont is supplied to the surround circuit. The current source I2 is for discharging the electric charge accumulated in the smoothing capacitor C1. Since the smoothing capacitor C1 requires a relatively large capacitance value, it is externally attached in the semiconductor integrated circuit.

第2の制御回路20において、トランジスタQ2〜Q7、電流源I3、基準電圧Vthの電圧源は比較回路4を構成し、そのうちトランジスタQ4とQ5、Q6とQ7はそれぞれカレントミラー回路を構成する。SWはサラウンドモードの動作/非動作状態の切り替えのスイッチである。I1は電流源、C2はボツ音低減用コンデンサ、R2は抵抗である。ボツ音低減用コンデンサC2は比較的大きな容量値が要求されるので、平滑用コンデンサC1と同様に、半導体集積回路では外付けとなる。トランジスタQ4の電流Iout1とトランジスタQ7の電流Iout2はサラウンドモードの動作/非動作状態の切替用の制御信号として、サラウンド回路に供給される。この第2の制御回路20については、例えば、特許文献1に類似の記載がある。   In the second control circuit 20, the transistors Q2 to Q7, the current source I3, and the voltage source of the reference voltage Vth constitute the comparison circuit 4, and the transistors Q4 and Q5, and Q6 and Q7 each constitute a current mirror circuit. SW is a switch for switching the operation / non-operation state of the surround mode. I1 is a current source, C2 is a noise reduction capacitor, and R2 is a resistor. Since the noise reduction capacitor C2 is required to have a relatively large capacitance value, it is externally attached to the semiconductor integrated circuit, like the smoothing capacitor C1. The current Iout1 of the transistor Q4 and the current Iout2 of the transistor Q7 are supplied to the surround circuit as control signals for switching the operation / non-operation state of the surround mode. The second control circuit 20 has a description similar to Patent Document 1, for example.

さて、第1の制御回路10では、入力するオーディオ信号Vinのピーク値を示す電圧がノードN1に生成され、サラウンド効果の強弱を決定するサラウンド効果制御電圧Vcontとしてサラウンド回路に供給される。一方、第2の制御回路20では、スイッチSWがOFFのときは、ノードN2の電位Vn2が低くなる(ほぼ接地電位)ので、トランジスタQ2のベース電位が基準電圧Vthより低くなり、そのトランジスタQ2がONし、トランジスタQ3がOFFしている。このため、トランジスタQ4の電流Iout1が出力し、トランジスタQ7の電流Iout2はゼロとなっている。これにより、サラウンド回路によるサラウンドモードが動作状態となっている。   In the first control circuit 10, a voltage indicating the peak value of the input audio signal Vin is generated at the node N1 and supplied to the surround circuit as a surround effect control voltage Vcont that determines the strength of the surround effect. On the other hand, in the second control circuit 20, when the switch SW is OFF, the potential Vn2 of the node N2 is low (approximately ground potential), so that the base potential of the transistor Q2 is lower than the reference voltage Vth, and the transistor Q2 ON and transistor Q3 is OFF. For this reason, the current Iout1 of the transistor Q4 is output, and the current Iout2 of the transistor Q7 is zero. Thereby, the surround mode by the surround circuit is in the operating state.

ここで、スイッチSWをONさせると、電流源I1の電流が抵抗R2に流れてそこの電圧Vn2が上昇し、その電圧Vn2が基準電圧Vthよりも高くなると、トランジスタQ2がOFF、トランジスタQ3がONとなる。このため、トランジスタQ4の電流Iout1がゼロとなり、トランジスタQ7の電流Iout2が出力する。これにより、サラウンド回路によるサラウンドモードが非動作状態となる。   Here, when the switch SW is turned on, the current of the current source I1 flows through the resistor R2 and the voltage Vn2 rises. When the voltage Vn2 becomes higher than the reference voltage Vth, the transistor Q2 is turned off and the transistor Q3 is turned on. It becomes. For this reason, the current Iout1 of the transistor Q4 becomes zero, and the current Iout2 of the transistor Q7 is output. As a result, the surround mode by the surround circuit is deactivated.

図4は以上のスイッチSWのON/OFFによるサラウンドモードの動作/非動作状態の特性を示す図である。スイッチSWがOFFになっているときは、ノードN2の電圧Vn2は基準電圧Vthよりも低い電圧であり、トランジスタQ2がONして、電流Iout1が出力し、サラウンド回路によるサラウンドモードが動作状態にある。このときのサラウンド効果の強弱はサラウンド効果制御電圧Vcontによって設定される。   FIG. 4 is a diagram showing the characteristics of the operation / non-operation state of the surround mode depending on ON / OFF of the switch SW described above. When the switch SW is OFF, the voltage Vn2 at the node N2 is lower than the reference voltage Vth, the transistor Q2 is turned ON, the current Iout1 is output, and the surround mode by the surround circuit is in the operating state. . The strength of the surround effect at this time is set by the surround effect control voltage Vcont.

時刻t1でスイッチSWをONすると、ノードN2の電圧Vn2が、電流源I1の電流値とボツ音低減用コンデンサC2の容量値とで決まる時定数で上昇し、基準電圧Vthを超えると、サラウンド回路によるサラウンドモードが非動作状態となる。このように、サラウンドモードの動作状態から非動作状態への切替時は、ノードN2の電圧Vn2の上昇が緩慢となるので、電流Iout1の減少と電流Iout2の増大が緩慢に行われ、ボツ音の発生が抑制される。   When the switch SW is turned on at time t1, the voltage Vn2 of the node N2 rises with a time constant determined by the current value of the current source I1 and the capacitance value of the noise reduction capacitor C2, and when the reference voltage Vth is exceeded, the surround circuit The surround mode by becomes inactive. As described above, when switching from the operation mode of the surround mode to the non-operation state, the increase in the voltage Vn2 of the node N2 is slow, so that the decrease in the current Iout1 and the increase in the current Iout2 are performed slowly. Occurrence is suppressed.

また、時刻t2でスイッチSWをOFFすると、ノードN2の電圧Vn2が、抵抗R2の抵抗値とボツ音低減用コンデンサC2の容量値とで決まる時定数で下降し、基準電圧Vthを下回ると、サラウンド回路によるサラウンドモードが動作状態となる。このように、サラウンドモードの非動作状態から動作状態への切替時も、ノードN2の電圧Vn2の下降が緩慢となるので、電流Iout1の増大と電流Iout2の減少が緩慢に行われ、上記同様にボツ音の発生が抑制される。
特開2003−347862号公報
Further, when the switch SW is turned OFF at time t2, the voltage Vn2 of the node N2 falls with a time constant determined by the resistance value of the resistor R2 and the capacitance value of the noise reduction capacitor C2, and when it falls below the reference voltage Vth, The surround mode by the circuit is activated. As described above, when the surround mode is switched from the non-operating state to the operating state, the decrease in the voltage Vn2 of the node N2 becomes slow, so that the increase in the current Iout1 and the decrease in the current Iout2 are performed slowly. Occurrence of noise is suppressed.
JP 2003-347862 A

ところが、図3に示した従来のサラウンド制御回路では、サラウンド回路によるサラウンドモードの動作/非動作状態を切り替える際に発生するボツ音の低減を、ボツ音低減用コンデンサC2によって行っているため、ボツ音低減以外には全く効果のないコンデンサC2が別途必要となり、サラウンド制御回路を半導体集積回路で構成するとき、ボツ音低減用コンデンサC2の外付け用の端子が特別に必要となり、端子数が増大するという問題がある。   However, in the conventional surround control circuit shown in FIG. 3, the noise generated when the surround circuit switches between the operation mode and the non-operation state of the surround mode is reduced by the noise reduction capacitor C2. Capacitor C2, which has no effect other than sound reduction, is required separately, and when the surround control circuit is composed of a semiconductor integrated circuit, an external terminal for the noise reduction capacitor C2 is specially required and the number of terminals increases. There is a problem of doing.

本発明の目的は、ボツ音低減用の特別なコンデンサを不要にしながらもボツ音低減を図り、上記した問題を解決したサラウンド制御回路を提供することである。   An object of the present invention is to provide a surround control circuit that can reduce the noise while eliminating the need for a special capacitor for reducing noise, and solves the above problems.

請求項1にかかる発明のサラウンド制御回路は、オーディオ信号を整流した電圧を平滑する平滑用コンデンサを備え、該平滑用コンデンサに生じる電圧をサラウンド効果の強弱を設定するサラウンド効果制御信号として出力する第1の制御回路と、スイッチのON/OFF制御により比較電位を変化させることで比較回路を動作させ、該比較回路の出力によってサラウンドモードの状態を設定する第2の制御回路とを備えたサラウンド制御回路において、前記比較電位が生じるノードに、前記平滑用コンデンサおよび前記平滑用コンデンサの電荷を放電する放電素子をそれぞれ接続したことを特徴とする。
請求項2にかかる発明は、請求項1に記載のサラウンド制御回路において、前記スイッチがOFFのとき、前記サラウンドモードが動作状態となるよう前記比較回路の出力が設定されていることを特徴とする。
According to a first aspect of the present invention, there is provided a surround control circuit comprising a smoothing capacitor for smoothing a voltage obtained by rectifying an audio signal, and outputting a voltage generated in the smoothing capacitor as a surround effect control signal for setting the strength of the surround effect. Surround control comprising: a first control circuit; and a second control circuit that operates a comparison circuit by changing a comparison potential by ON / OFF control of a switch and sets a surround mode state by an output of the comparison circuit In the circuit, the smoothing capacitor and a discharge element for discharging the charge of the smoothing capacitor are respectively connected to a node where the comparison potential is generated.
According to a second aspect of the present invention, in the surround control circuit according to the first aspect, when the switch is OFF, the output of the comparison circuit is set so that the surround mode is in an operating state. .

本発明によれば、サラウンド効果制御信号を生成する平滑用コンデンサをボツ音低減用コンデンサとして共用するので、コンデンサの数を1個削減することができ、そのための外付け端子を削減することができる。   According to the present invention, since the smoothing capacitor that generates the surround effect control signal is shared as the noise reduction capacitor, the number of capacitors can be reduced by one, and the number of external terminals for that purpose can be reduced. .

図1は本発明の1つの実施例のサラウンド制御回路の構成を示す回路図である。本実施例は、図3で説明した第1の制御回路10と第2の制御回路20を一体化して、平滑用コンデンサC1をオーディオ信号の平滑用とボツ音低減用に共用したものである。すなわち、平滑回路3の平滑用コンデンサC1が接続されるノードNを、比較回路4の比較電位の生成点(トランジスタQ2のベースへの接続点)とし、そのノードNにスイッチSWと電流源I1の直列回路を接続したものである。電流源I2の電流値は、電流源I1の電流値に比べて十分小さな値である(I2<<I1)。なお、この電流源I2はこれに限らず放電素子であればよいので、抵抗R2に代えても良い。各部分の構成については、前述した図3で説明したのと同じであるので、説明を省略する。   FIG. 1 is a circuit diagram showing a configuration of a surround control circuit according to one embodiment of the present invention. In the present embodiment, the first control circuit 10 and the second control circuit 20 described with reference to FIG. 3 are integrated, and the smoothing capacitor C1 is shared for the purpose of smoothing the audio signal and reducing the noise. That is, the node N to which the smoothing capacitor C1 of the smoothing circuit 3 is connected is set as a comparison potential generation point (connection point to the base of the transistor Q2) of the comparison circuit 4, and the switch SW and the current source I1 are connected to the node N. A series circuit is connected. The current value of the current source I2 is sufficiently smaller than the current value of the current source I1 (I2 << I1). The current source I2 is not limited to this and may be a discharge element, and may be replaced with the resistor R2. The configuration of each part is the same as that described with reference to FIG.

図2は以上のスイッチSWのON/OFFによるサラウンドモードの動作/非動作状態の特性を示す図である。スイッチSWがOFFになっているときは、ノードNの比較電位は平滑回路3のサラウンド効果制御電圧Vcont(図4に示した電圧Vcontと同じ)によって決まり、その値は基準電圧Vthよりも低い電圧である。よって、トランジスタQ2がONして、電流Iout1が出力し、電流Iout2はゼロとなって、サラウンド回路によるサラウンドモードが動作状態にある。このときのサラウンド効果の強弱は電圧Vcontによって設定される。   FIG. 2 is a diagram showing the characteristics of the operation / non-operation state of the surround mode depending on ON / OFF of the switch SW described above. When the switch SW is OFF, the comparison potential of the node N is determined by the surround effect control voltage Vcont (same as the voltage Vcont shown in FIG. 4) of the smoothing circuit 3, and the value is a voltage lower than the reference voltage Vth. It is. Therefore, the transistor Q2 is turned on, the current Iout1 is output, the current Iout2 becomes zero, and the surround mode by the surround circuit is in the operating state. The strength of the surround effect at this time is set by the voltage Vcont.

時刻t1でスイッチSWをONすると、ノードNの電圧Vcontが、電流源I1の電流値と平滑用コンデンサC1の容量値とで決まる時定数で上昇し、基準電圧Vthを超えると、トランジスタQ2がOFFし、トランジスタQ3がONして、電流Iout1がゼロ、電流Iout2が出力するので、サラウンド回路によるサラウンドモードが非動作状態となる。このように、サラウンドモードが非動作状態であるので、電圧Vcontが高い電圧になっても、異常は発生しない。このようなサラウンドモードの動作状態から非動作状態への切替時は、ノードNの電圧Vcontの上昇が緩慢となるので、電流Iout1の減少と電流Iout2の増大は緩慢に行われ、ボツ音の発生が抑制される。   When the switch SW is turned on at time t1, the voltage Vcont at the node N rises with a time constant determined by the current value of the current source I1 and the capacitance value of the smoothing capacitor C1, and when the reference voltage Vth is exceeded, the transistor Q2 is turned off. Then, since the transistor Q3 is turned on, the current Iout1 is zero and the current Iout2 is output, the surround mode by the surround circuit is inactive. Thus, since the surround mode is inactive, no abnormality occurs even when the voltage Vcont becomes a high voltage. At the time of switching from the operation state of the surround mode to the non-operation state, the increase in the voltage Vcont of the node N becomes slow, so that the decrease in the current Iout1 and the increase in the current Iout2 are performed slowly, and a pop noise is generated. Is suppressed.

また、時刻t2でスイッチSWをOFFすると、ノードNの電圧Vcontが、平滑用コンデンサC1の容量値と電流源I2の電流値で決まる時定数で下降し、基準電圧Vthを下回ると、トランジスタQ2がONし、トランジスタQ3がOFFして、電流Iout1が出力し、電流Iout2がゼロなるので、サラウンドモードが動作状態となる。このようなサラウンドモードの非動作状態から動作状態への切替時も、ノードNの電圧Vcontの下降が緩慢となるので、電流Iout1の増大と電流Iout2の減少が緩慢に行われ、上記同様にボツ音の発生が抑制される。   Further, when the switch SW is turned off at time t2, the voltage Vcont at the node N decreases with a time constant determined by the capacitance value of the smoothing capacitor C1 and the current value of the current source I2, and when the voltage falls below the reference voltage Vth, the transistor Q2 is turned on. The transistor is turned on, the transistor Q3 is turned off, the current Iout1 is output, and the current Iout2 becomes zero, so that the surround mode is in an operating state. Even when the surround mode is switched from the non-operating state to the operating state, the decrease in the voltage Vcont of the node N becomes slow, so that the current Iout1 increases and the current Iout2 decreases slowly. Sound generation is suppressed.

本発明の1つの実施例のサラウンド制御回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the surround control circuit of one Example of this invention. 図1のサラウンド制御回路の制御特性図である。FIG. 2 is a control characteristic diagram of the surround control circuit of FIG. 1. 従来のサラウンド制御回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the conventional surround control circuit. 図3のサラウンド制御回路の制御特性図である。FIG. 4 is a control characteristic diagram of the surround control circuit of FIG. 3.

符号の説明Explanation of symbols

1:電圧/電流変換回路
2:整流回路
3:平滑回路
4:比較回路
1: Voltage / current conversion circuit 2: Rectifier circuit 3: Smoothing circuit 4: Comparison circuit

Claims (2)

オーディオ信号を整流した電圧を平滑する平滑用コンデンサを備え、該平滑用コンデンサに生じる電圧をサラウンド効果の強弱を設定するサラウンド効果制御信号として出力する第1の制御回路と、スイッチのON/OFF制御により比較電位を変化させることで比較回路を動作させ、該比較回路の出力によってサラウンドモードの状態を設定する第2の制御回路とを備えたサラウンド制御回路において、
前記比較電位が生じるノードに、前記平滑用コンデンサおよび前記平滑用コンデンサの電荷を放電する放電素子をそれぞれ接続したことを特徴とするサラウンド制御回路。
A first control circuit including a smoothing capacitor for smoothing a voltage obtained by rectifying the audio signal, and outputting a voltage generated in the smoothing capacitor as a surround effect control signal for setting the strength of the surround effect; and ON / OFF control of the switch A surround control circuit comprising: a second control circuit that operates the comparison circuit by changing the comparison potential according to the second control circuit, and sets a surround mode state by an output of the comparison circuit
A surround control circuit, wherein a smoothing capacitor and a discharge element for discharging the charge of the smoothing capacitor are connected to a node where the comparison potential is generated.
請求項1に記載のサラウンド制御回路において、
前記スイッチがOFFのとき、前記サラウンドモードが動作状態となるよう前記比較回路の出力が設定されていることを特徴とするサラウンド制御回路。

The surround control circuit according to claim 1,
The surround control circuit, wherein the output of the comparison circuit is set so that the surround mode is in an operating state when the switch is OFF.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05232149A (en) * 1992-02-20 1993-09-07 Nec Corp Peak holding circuit
JPH0818366A (en) * 1994-06-29 1996-01-19 Sony Corp Ic for audio
JP2003304133A (en) * 2002-04-09 2003-10-24 New Japan Radio Co Ltd Pop noise reducing circuit
JP2003318656A (en) * 2002-04-23 2003-11-07 Sanyo Electric Co Ltd Circuit for preventing shock sound
JP2003347862A (en) * 2002-05-30 2003-12-05 New Japan Radio Co Ltd Circuit for preventing pop sound

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05232149A (en) * 1992-02-20 1993-09-07 Nec Corp Peak holding circuit
JPH0818366A (en) * 1994-06-29 1996-01-19 Sony Corp Ic for audio
JP2003304133A (en) * 2002-04-09 2003-10-24 New Japan Radio Co Ltd Pop noise reducing circuit
JP2003318656A (en) * 2002-04-23 2003-11-07 Sanyo Electric Co Ltd Circuit for preventing shock sound
JP2003347862A (en) * 2002-05-30 2003-12-05 New Japan Radio Co Ltd Circuit for preventing pop sound

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