JPH11353040A - Power unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power unit improved in conversion efficiency. SOLUTION: This power unit is provided with a power circuit 100 for converting an input voltage Vin to an output voltage Vout and supplying the output voltage Vout to a load 160. The power circuit 100 is provided with plural voltage converting circuits 110 and 120 and a selector circuit 150 for selecting any one of plural voltage converting circuits 110 and 120 so as to improve the conversion efficiency of the power circuit 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for converting an input voltage into a desired voltage and supplying the desired voltage to a load.

[0002]

2. Description of the Related Art A conventional power supply device has only one kind of voltage conversion circuit. What kind of voltage conversion circuit the power supply device employs has been determined according to the use of the system in which the power supply device is incorporated.

As voltage conversion circuits, a voltage conversion circuit called a linear regulator (for example, a series regulator) and a voltage conversion circuit called a switching regulator are known.

[0004] The series regulator is characterized in that the amount of electric noise generated is extremely small and the stability of the output voltage is high. In the series regulator, the difference between the input voltage V _in and the output voltage V _out is applied to both ends of the control transistor. Further, the current flowing through the control transistor (that is, the input current I _in ) is directly used as the output current I in
It is supplied to the external load as _out. Therefore, the conversion efficiency eta _series of the series regulator is determined by the ratio of the way, the input voltage V _in regardless of the output current I _out output voltage V _out is represented by equation (1).

[0005]

Η _series = V _out * I _out / V _in * I _in = V _out
/ V _in (∵I _out = I _in ) The switching regulator is characterized in that energy loss due to voltage conversion is small and high conversion efficiency can be obtained with only a few external components. This, although the conversion efficiency of the switching regulator depends on the output current I _out, by chopping the input voltage V _in, be larger difference between the input voltage V _in and the output voltage V _out is to convert a high efficiency Because you can. The conversion efficiency η _switch of the switching regulator is determined by (Equation 2).

[0006]

## EQU2 ## The η _switch = V _out * I _out / V _in * I _in series regulator has been adopted in equipment such as radio equipment and measuring instruments that extremely dislike noise. Switching regulators are used in devices such as personal computers (particularly notebook computers) where low power consumption of the system is prioritized and heat generation of the power supply circuit itself is problematic. As described above, the series regulator and the switching regulator are properly used depending on the field of the system to which they are applied.

[0007]

[Problems to be solved by the invention] Series regulator
And the input voltage V_inIs the output voltage V_outWhen converting to
At the output voltage V_outIs the input voltage V_inSmall compared to
Energy loss due to the control transistor
Becomes very large. As a result, the conversion efficiency η_{seri es}Is poor
Become However, since the self-current is small, the conversion efficiency η
_seriesIs almost constant regardless of the output current.

The switching regulator requires a complicated circuit configuration and operation as compared with the series regulator, and requires a large amount of energy to operate the conversion circuit itself. When the output current is large, the operating energy of the conversion circuit becomes relatively small, so that the conversion efficiency η _switch
The drop in can be ignored. However, when the output current is small, the operation energy of the conversion circuit becomes relatively large, so that the conversion efficiency η _switch is reduced.

An object of the present invention is to provide a power supply circuit having improved conversion efficiency by combining a plurality of voltage conversion circuits.

[0010]

A power supply device according to the present invention includes a power supply circuit for converting an input voltage to an output voltage and supplying the output voltage to a load, wherein the power supply circuit includes a conversion circuit. A plurality of voltage conversion circuits having different efficiencies; and a selection circuit for selecting one of the plurality of voltage conversion circuits so as to improve the conversion efficiency of the power supply circuit. Is done.

[0011] The number of the plurality of voltage conversion circuits may be three or more.

A current detection circuit for detecting an output current flowing from the power supply circuit to the load, wherein the selection circuit selects one of the plurality of voltage conversion circuits according to the output current. Is also good.

[0013] The plurality of voltage conversion circuits may include a series regulator and a switching regulator.

The load is a semiconductor device including at least one functional block, the semiconductor device operates in each of a plurality of operation modes, and the selection circuit outputs a mode signal indicating an operation mode of the semiconductor device. Acceptance,
One of the plurality of voltage conversion circuits may be selected according to the mode signal.

The semiconductor device may further include a path switching circuit for switching a path between the voltage conversion circuit selected according to the mode signal and the semiconductor device.

The plurality of voltage conversion circuits include a series regulator and a switching regulator, the semiconductor device includes a memory and an arithmetic circuit, and the semiconductor device operates at least in a first mode and a second mode. ,
In the first mode, the path switching circuit switches the path so that an output voltage output from the series regulator selected by the selection circuit is supplied to the memory. In the second mode, the path switching circuit switches the path. The switching circuit may switch the path so that an output voltage output from the switching regulator selected by the selection circuit is supplied to the memory and the arithmetic circuit.

The plurality of voltage conversion circuits include a first series regulator, a second series regulator, and a switching regulator, and the semiconductor device includes a memory, a first arithmetic circuit, and a second arithmetic circuit, Operates at least in a first mode, a second mode, and a third mode, and in the first mode, the path switching circuit includes:
The path is switched such that an output voltage output from the first series regulator selected by the selection circuit is supplied to the memory, and in the second mode,
The path switching circuit switches the path so that an output voltage output from the second series regulator selected by the selection circuit is supplied to the memory and the first arithmetic circuit, and in the third mode, The path switching circuit switches the path so that an output voltage output from the switching regulator selected by the selection circuit is supplied to the memory, the first arithmetic circuit, and the second arithmetic circuit. Is also good.

The operation will be described below.

According to the first aspect of the present invention, it is possible to provide a power supply device having improved conversion efficiency by selecting one of the plurality of voltage conversion circuits. Thus, power consumption of the power supply device can be reduced.

According to the third aspect of the present invention, one of the plurality of voltage conversion circuits is selected according to the output current flowing from the power supply circuit to the load, so that at least a predetermined range of output current can be reduced. Thus, a power supply device having improved conversion efficiency can be provided.

According to the fifth aspect of the present invention, one of the plurality of voltage conversion circuits is selected according to the mode signal indicating the operation mode of the semiconductor device, thereby improving each operation mode of the semiconductor device. A power supply device having improved conversion efficiency can be provided.

According to the present invention, by switching the path between the voltage conversion circuit and the semiconductor device selected according to the mode signal, it is possible to prevent power from being supplied to unnecessary circuits. be able to. Thus, leakage current generated in the semiconductor device can be reduced. As a result, power consumption of the semiconductor device can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a configuration of a power supply circuit 100 according to Embodiment 1 of the present invention.

The power supply circuit 100, the input voltage V _in into a desired voltage, supplied to the load 160 and the desired voltage as an output voltage V _out. The load 160 is connected to the power supply circuit 100
Is provided outside.

The power supply circuit 100 includes a voltage conversion circuit 110,
120, a current monitor 140 for monitoring an output current I _out flowing from the power supply circuit 100 to the load 160, a voltage conversion circuit 110 according to a detection signal from the current monitor 140,
120 includes a selection circuit 150 for selecting one of them, and a reference voltage generation circuit 130 for generating a reference voltage _Vref .

Voltage conversion circuit 110 and voltage conversion circuit 120
According different conversion method and converts the input voltage V _in to an output voltage V _out.

In the example shown in FIG. 1, the number of voltage conversion circuits included in power supply circuit 100 is two. However, the present invention is not limited to this. The power supply circuit 100 may have three or more arbitrary number of voltage conversion circuits.

The current monitor 140 monitors the output current I _out, the current value of the output current I _out to output a detection signal indicating whether or not larger than the predetermined current value I _x.

The selection circuit 150 includes selection signals 151 and 15
2 is output. The selection signal 151 is output from the voltage conversion circuit 110
, And the selection signal 152 is supplied to the voltage conversion circuit 120. The selection circuit 150 determines which of the selection signals 151 and 152 is to be activated according to the detection signal from the current monitor 140.

For example, when the selection signal 151 becomes active, the voltage conversion circuit 110 is selected and the selection signal 152
Becomes active, the voltage conversion circuit 120 is selected.

The load 160 is commonly connected to the output of the voltage conversion circuit 110 and the output of the voltage conversion circuit 120. When the voltage conversion circuit 110 is selected, the output of the voltage conversion circuit 110 is set as the output voltage _Vout and the load 1
60, and the output of the voltage conversion circuit 120 enters a high impedance state. When the voltage conversion circuit 120 is selected, the output of the voltage conversion circuit 120 is supplied to the load 160 as the output voltage _Vout.
The output of 10 goes to a high impedance state. Thus, the output of the unselected voltage conversion circuit is high.
It becomes an impedance state. The output current I _out is a current flowing from the power supply circuit 100 to the load 160. Here, assuming that the resistance value of the load 160 is RL, according to Ohm's law, V
_out = I _out * RL holds.

The reference voltage generation circuit 130 generates the reference voltage V
_It can have any configuration for generating a _ref . For example, the reference voltage generation circuit 130 uses the resistance ladder to generate the reference voltage V
_ref may be generated, or a reference voltage V _ref may be generated using a bandgap circuit. The reference voltage V _ref is a voltage conversion circuit 11
0, 120.

FIG. 2 shows the output current I _out and the voltage conversion efficiency η.
The relationship is shown below. Here, it is assumed that the output voltage V _out is constant. In FIG. 2, η ₁ is a voltage conversion circuit 110
Η ₂ indicates the conversion efficiency of the voltage conversion circuit 120.

The current value of the output current I _out where η ₁ = η ₂ is defined as I _x . As shown in FIG. 2, when I _out <I _x , η ₁ > η ₂ , and when I _out > I _x , η ₁ <
a η _2. Therefore, when I _out <I _x , the voltage conversion circuit 110 is selected, and when I _out > I _x , the voltage conversion circuit 12 is selected.
Current monitor 140 and selection circuit 150 so as to select 0.
By designing the power supply circuit 100, the power supply circuit 100 having the optimum conversion efficiency η can be obtained regardless of the current value of the output current I _out .

According to the first embodiment, by selecting one of a plurality of voltage conversion circuits in accordance with the current value of the output current I _out, the highest for any value of the output current I _out A power supply circuit having conversion efficiency can be realized.

(Embodiment 2) FIG. 3 shows a configuration of a power supply circuit 200 according to Embodiment 2 of the present invention.

The power supply circuit 200 includes voltage conversion circuits 210 and 220 of different types. The voltage conversion circuit 210
Is a series regulator, and the voltage conversion circuit 220
It is a switching regulator.

[0039] Here, in this specification, the series regulator is defined as a voltage conversion circuit for obtaining a desired voltage by lowering using variable resistance of one of the input voltage V _in (including transistors) , a switching regulator generates an AC voltage by turning on and off the switching transistor input voltage V _in is input, the AC voltage by the voltage conversion circuit for obtaining a desired voltage by smoothing using LC filter Defined to be.

In FIG. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The power supply circuit 200 includes a series regulator 210, a switching regulator 220, a current monitor 140 for monitoring an output current I _out flowing from the power supply circuit 200 to the load 160, and a series regulator in response to a detection signal from the current monitor 140. It includes a selection circuit 150 for selecting one of the switching regulator 210 and the switching regulator 220, and a reference voltage generation circuit 130 for generating a reference voltage _Vref .

Selection signal 1 output from selection circuit 150
When 51 becomes active, the series regulator 21
0 is selected, and the output of the series regulator 210 is output as the output voltage _Vout . When the selection signal 152 output from the selection circuit 150 becomes active, the switching regulator 220 is selected, and the output of the switching regulator 220 is output as the output voltage _Vout via the LC filter 230. LC filter 230
Is provided outside the power supply circuit 200 and is used to smooth the output of the switching regulator 220.

FIG. 4 shows the output current I_outAnd voltage conversion efficiency η
The relationship is shown below. In FIG. 4, η_{s eries}(Dashed line)
Shows the conversion efficiency of the series regulator 210, and η_switch
(Solid thin line) shows the conversion effect of the switching regulator 220.
Rate, η_total(Solid bold line) shows the conversion of the power supply circuit 200
Shows efficiency.

[0044] As shown in FIG. 4, the conversion efficiency eta _series of the series regulator 210 regardless of the output current I _out, is determined by the ratio between the input voltage V _in and the output voltage V _out ((number 1) Reference ).

The conversion efficiency η _switch of the switching regulator 220 depends on the output current I _out . However, the switching regulator 220, by chopping the input voltage V _in, and the input voltage V _in the output voltage V
be greater the difference between the _out can be converted with high efficiency an input voltage V _in to an output voltage V _out ((number 2) reference). FIG.
As shown in (2), the conversion efficiency η _switch of the switching regulator 220 has a characteristic of peaking at the output current value _Ip . Therefore, if the output current value _Ip can be accurately predicted, a highly efficient power supply circuit can be obtained. However, as understood from FIG.
When the value of _out deviates significantly from the output current value I _p, the conversion efficiency _{eta: switch} deteriorates.

The conversion efficiency η _total of the power supply circuit 200 is obtained by optimally combining the conversion efficiency η _series and the conversion efficiency η _switch . Specifically, the output current I
current value _out is the series regulator 210 is selected when a predetermined current value I _a is smaller than the switching regulator 220 is selected if the current value of the output current I _out is equal to or greater than a predetermined current value I _a .

The current monitor 140 determines that the output current I _out is
It detects whether it is included in the range of I _out <I _{a or in} the range of I _a ≦ I _out , and outputs a detection signal indicating the detection result to the selection circuit 150.

FIG. 5 shows an example of a circuit configuration of the series regulator 210.

The series regulator 210 includes a comparator 212, a PMOS transistor MP01, and resistors R ₁ and R ₂ .

The comparator 212 has a reference voltage generation circuit.
Reference voltage V output from path 130 _refAnd resistance R₁, R_Two
Is input. comparator
The output of 212 is the gate of PMOS transistor MP01.
Connected to Resistance R₁, R_TwoIs the output voltage V_outSplit
Used to The output voltage Vout is changed to the resistance R₁To
Therefore, the dropped voltage is applied to one input of the comparator 212.
Supplied to power.

The output voltage V _out and the reference voltage V _ref satisfy the relationship shown in (Equation 3).

[0052]

V _out = V _ref * {(R ₁ + R ₂ ) / R ₂ } The selection signal 151 serves as an enable signal for the comparator 212. The comparator 212 operates only when the enable signal is at the H level. That is, when the enable signal is at the H level and V _ref > V _out , the comparator 212 outputs an H level signal. When the enable signal is at the H level and V _ref <V _out , the comparator 212 outputs An L level signal is output. As a result, the PMOS transistor MP01 outputs the output voltage V _out
It is turned on and off according to.

When the enable signal is at the L level, the comparator 212 always outputs a signal at the H level. As a result, the PMOS transistor MP01 is turned off. As a result, the output of the series regulator 210 enters a high impedance state.

The circuit configuration shown in FIG. 5 is an example of the circuit configuration of the series regulator 210. The series regulator 210 can have any circuit configuration having the same function as the circuit configuration shown in FIG.

FIG. 6 shows a switching regulator 220.
An example of the circuit configuration of FIG.

The switching regulator 220 includes a comparator 222, AND elements 224 and 226, and switching transistors MP10 and MN10. The switching transistor MP10 is a PMOS transistor. The switching transistor MN10 is N
It is a MOS transistor.

The comparator 222 functions as a switching control circuit for controlling on / off of the switching transistors MP10 and MN10. Comparator 222
, The reference voltage _Vref and the output voltage _Vout output from the reference voltage generation circuit 130 are input. Comparator 2
The output of 22 is supplied to one input of AND elements 224, 226.

The selection signal 152 is output from the AND elements 224,
26 to the other input. The output of the AND element 224 is connected to the gate of the switching transistor MP10. The output of the AND element 226 is connected to the gate of the switching transistor MN10.

Switching transistors MP10, MN
10 is output through the LC filter 230 to the output voltage V
It is output as _out. LC filter 230 includes a coil L and a capacitor C. One end of the coil L is connected to the outputs of the switching transistors MP10 and MN10, and the other end is connected to the output voltage _Vout . Capacitor C
Is connected to the output voltage _Vout , and the other end is grounded.

When the selection signal 152 is at the H level,
The following operation is performed. That is, when V _out > V _ref , the comparator 222 outputs an H-level signal. As a result, the switching transistor MP10 turns off and the switching transistor MN10 turns on. If V _out <V _ref , the comparator 222
Outputs an L level signal. As a result, the switching transistor MP10 turns on and the switching transistor MN10 turns off. By turning on and off the switching transistors MP10 and MN10 in this manner, the switching transistor MP10
A current flows toward the filter 230, or a current flows from the LC filter 230 to the switching transistor MN10.

The circuit configuration shown in FIG. 6 is an example of the circuit configuration of the switching regulator 220. The switching regulator 220 can have any circuit configuration having the same function as the circuit configuration shown in FIG.

FIG. 7 shows the LC filter 23 shown in FIG.
5 shows a waveform of a current flowing through the coil L of 0 and a waveform of a voltage applied to both ends of the coil L. In FIG. 7, tON indicates a period during which the switching transistor MP10 is turned on, and tOFF indicates a period during which the switching transistor MP10 is turned off.

As shown in FIG. 7, by turning on / off the switching transistor MP10, the coil L
And the voltage applied to both ends of the coil L change. When the on / off of the switching transistor MP10 is periodically repeated, the switching transistor M
(Equation 4) is obtained from the fact that the current values at the time of P10 on / off switching are equal.

[0064]

[Number 4] _{I max -I min = (V in} -V out) / L * tON
= Where _{V out / L * tOFF V out} = tON / (tON + tOFF) * V in, I max denotes the maximum value of the current flowing through the coil L, I _min is the minimum value of the current flowing through the coil L.

[0065] From equation (4), by changing the duty ratio of the period for chopping the input voltage V _in, it can be seen that changing the output voltage V _out.

When the switching transistor MP10 is on, energy is stored in the coil L through the switching transistor MP10. When the switching transistor MP10 turns off, the switching transistor MN10 turns on. As a result, the energy of the coil L is charged to the capacitor C through the switching transistor MN10. Simply put, this is the principle of a switching regulator.

FIG. 8 shows the current monitor 140 and the selection circuit 15
An example of a circuit configuration of 0 is shown.

The current monitor 140 is connected to the current comparator 1
41 inclusive. The output current I _out is input to the + input terminal of the current comparator 141. Current comparator 1
The reference current _Ia is input to the negative input terminal 41. The current comparator 141 outputs an H level signal when the current input to the + input terminal is equal to or larger than the current input to the − input terminal. That is, the current comparator 141 outputs an L level signal when I _out <I _a , and outputs an H level signal when I _a ≦ I _out .

The selection circuit 150 includes inverters 150a to 150a.
150c.

The selection circuit 150 is configured to set the selection signal 151 to an H level and set the selection signal 152 to an L level when an L level signal is output from the current monitor 140. This is because, in the case of I _out <I _a , η _switch <η _series (see FIG. 4), so that selecting the series regulator 210 has higher conversion efficiency than selecting the switching regulator 220.

The selection circuit 150 is configured to set the selection signal 151 to an L level and set the selection signal 152 to an H level when an H level signal is output from the current monitor 140. This is because, when I _a ≦ I _out , η _series ≦ η _switch (see FIG. 4), so that selecting the switching regulator 220 has higher conversion efficiency than selecting the series regulator 210.

As described above, the selection signal 151 is supplied to the comparator 212 of the series regulator 210 (FIG. 5).
Is used as an enable signal for activating. The selection signal 152 is output from the switching regulator 22
0 is input to AND elements 224 and 226 (FIG. 6).

By controlling the levels of the selection signals 151 and 152 as described above, the series regulator 2 is controlled.
When 10 is selected, the output of the switching regulator 220 is in a high impedance state, and when the switching regulator 220 is selected, the output of the series regulator 210 is in a high impedance state. This prevents the output of the series regulator 210 and the output of the switching regulator 220 from colliding.

In the example shown in FIG. 3, the power supply circuit 2
The number of voltage conversion circuits included in 00 is two. But,
The present invention is not limited to this. The power supply circuit 200 can have any number of voltage conversion circuits of three or more.

(Embodiment 3) FIG. 9 shows a configuration of a semiconductor device 300 according to Embodiment 3 of the present invention. Semiconductor device 3
00 includes the power supply circuit 200 described in the second embodiment. The semiconductor device 300 is formed on a single semiconductor chip.

Semiconductor device 300 further includes CPU 310. Output voltage V _out output from power supply circuit 200
Is supplied to the CPU 310 as the power supply voltage _Vdd . As described above, in the example illustrated in FIG. 9, the CPU 310 corresponds to the load of the power supply circuit 200.

The semiconductor device 300 includes a CPU 310
Memory and digital signal processor (DS)
A semiconductor circuit such as P) may be included. In FIG.
For simplicity, only the power supply circuit 200 and the CPU 310 are shown as components of the semiconductor device 300.

As described in the second embodiment, power supply circuit 200 includes series regulator 210 and switching regulator 220. The power supply circuit 200, the input voltage V _in is supplied via a terminal 322. Input voltage V _in is supplied to the series regulator 210 and the switching regulator 220.

[0079] series regulator 210, the input voltage V _in and converted to the desired voltage, the terminal 32 the desired voltage
4 for output. Thus, the output voltage V _out
Is obtained.

[0080] The switching regulator 220 generates an AC voltage based on the input voltage V _in, and supplies the AC voltage to the LC filter 230 through a terminal 326. L
The C filter includes a coil L and a capacitor C, and is provided outside the semiconductor device 300. LC filter 2
An output voltage V _out is obtained as the output of the output 30.

The output voltage V _out is supplied to a terminal 328 via an external wiring 332 provided outside the semiconductor device 300.
To the semiconductor device 300 and supplied to the power supply port 330 of the CPU 310 as the power supply voltage _Vdd .

The LC circuit 230 is connected to the semiconductor device 300
, It is not necessary to output the output of the power supply circuit 200 to the outside of the semiconductor device 300. In this case, the output voltage _Vout may be supplied to the power supply port 330 of the CPU 310 via an internal wiring (not shown) provided inside the semiconductor device 300.

(Embodiment 4) FIG. 10 shows a configuration of a power supply device 560 according to Embodiment 4 of the present invention. Power supply 56
0, the mode signal 551 output from the CPU 550
, One of the series regulator 210 and the switching regulator 220 included in the power supply circuit 500 is selected.

Power supply device 560 includes a power supply circuit 500, a selection circuit 520, a path switching circuit 530, and an LC filter 230.

Power supply circuit 500 includes a series regulator 210 and a switching regulator 220. Reference voltage V generated by reference voltage generation circuit 130
_ref is supplied to the series regulator 210 and the switching regulator 220. The series regulator 210 and the switching regulator 220
Since the configuration and operation are the same as those described in the second embodiment, description thereof is omitted here.

The output of the series regulator 210 is supplied to the semiconductor device 510 via the path switching circuit 530. The output of the switching regulator 220 is supplied to the semiconductor device 510 via the LC filter 230 and the path switching circuit 530. The semiconductor device 510 includes the power supply device 5
This corresponds to a load of 60.

The semiconductor device 510 has a plurality of functional blocks that can be executed independently of each other. One of the plurality of functional blocks is, for example, the memory 511. Another one of the plurality of functional blocks is, for example, the arithmetic circuit 512.

CPU 550 outputs a mode signal 551 indicating an operation mode in which semiconductor device 510 operates. For example, the fact that the mode signal 551 is at the H level indicates that the operation mode of the semiconductor device 510 is the sleep mode. The fact that the mode signal 551 is at the L level indicates that the operation mode of the semiconductor device 510 is the normal mode.

In the sleep mode, the memory 511 stores
Only the content holding operation for holding the content of the information stored in the memory 511 is performed, and the arithmetic circuit 512 does not operate. In the normal mode, both the memory 511 and the arithmetic circuit 512 operate.

The power supply 560 supplies power only to the memory 511 in the sleep mode, and supplies power to both the memory 511 and the arithmetic circuit 512 in the normal mode. Thus, the semiconductor device 51
The function block to which power is supplied among the plurality of function blocks included in the semiconductor device 510 is changed according to the operation mode of “0”. This makes it possible to prevent power from being supplied to unnecessary function blocks in the sleep mode. As a result, leakage current can be prevented, and power consumption of the semiconductor device 510 can be reduced.

Here, the power supply required for the memory 511 to perform the internal holding operation is only required to provide an output current _Iout corresponding to the leak current of the memory 511.
Therefore, it is understood that the conversion efficiency of the power supply circuit 500 is optimized by selecting the series regulator 210 having a high conversion efficiency with a small output current _Iout in the sleep mode.

In a conventional semiconductor circuit using CMOS,
In the mode in which the operation of the semiconductor circuit is stopped (that is, the sleep mode), it is not necessary to stop the supply of power to the semiconductor circuit. This is because the leakage current of each transistor included in the semiconductor circuit was at a negligible level. However, as the miniaturization of the semiconductor process progresses and the threshold value of the transistor decreases in order to realize high-speed operation at a low power supply voltage, the leak current cannot be ignored.
Unless power supply to unnecessary circuits is stopped in the sleep mode, it has become difficult to reduce the power consumption of the semiconductor circuit. However, even in the sleep mode, it is necessary to supply power to a memory that loses its contents when the power is turned off. Power is supplied to the memory 511 in the sleep mode for this reason.

When operation mode of semiconductor device 510 is the sleep mode (ie, when mode signal 551 is at H level), selection circuit 520 selects series regulator 210, and the operation mode of semiconductor device 510 is normally set. Mode (that is, the mode signal 55
When 1 is at the L level), the switching regulator 220 is selected. Such a selection is made by the mode signal 5
This is achieved by determining the levels of the selection signals 151 and 152 in accordance with the level of 51.

The path switching circuit 530 responds to the path switching signal 552 output from the CPU 550,
The path between 0 and the semiconductor device 510 is switched.

Specifically, when the series regulator 210 is selected by the selection circuit 520, the path switching circuit 530 electrically connects the output of the series regulator 210 and the memory 511, and The output and the arithmetic circuit 512 are electrically separated. Thus, in the sleep mode, the output voltage V _out output from the series regulator 210 can be supplied only to the memory 511.

When the switching regulator 220 is selected by the selection circuit 520, the path switching circuit 530 electrically connects the output of the switching regulator 220 to the memory 511 and the arithmetic circuit 512. Thereby, in the normal mode, the output voltage V _out output from the switching regulator 220 is stored in the memory 5.
11 and the arithmetic circuit 512.

FIG. 11 shows a configuration example of the path switching circuit 530. The path switching circuit 530 includes the PMOS transistor 5
32, and a logic circuit 531 that controls the PMOS transistor 532 in accordance with the path switching signal 552.

In the sleep mode, the logic circuit 531 is configured so that the PMOS transistor 532 is turned off. Thus, in the sleep mode, the output voltage V _out output from the series regulator 210 is supplied only to the memory 511.

In the normal mode, the logic circuit 531 is configured so that the PMOS transistor 532 is turned on. Thus, in the normal mode, the output voltage V _out output from the switching regulator 220 is supplied to both the memory 511 and the arithmetic circuit 512.

FIG. 12 shows the relationship between the path switching signal 552 output from the CPU 550 and the functional blocks to which power is supplied.

The relationship shown in FIG. 12 can be realized by inputting a mode signal 551 to the path switching circuit 530 instead of the path switching signal 552. In this case, the mode signal 551 is directly
What is necessary is just to input to the gate of the S transistor 532.

By turning on the PMOS transistor 532 when the series regulator 210 is selected by the selection circuit 520, the output voltage V _out output from the series regulator 210 is supplied to both the memory 511 and the arithmetic circuit 512. Can be supplied. Alternatively, by turning off the PMOS transistor 532 when the switching regulator 220 is selected by the selection circuit 520, the output voltage V _out output from the switching regulator 220 can be supplied only to the arithmetic circuit 512. Such supply of the output voltage V _out can be achieved by appropriately modifying the logic of the selection circuit 520 and / or the path switching circuit 530.

As described above, the path switching circuit 530 transmits the output voltage V _out from one voltage conversion circuit selected by the selection circuit 520 among the plurality of voltage conversion circuits included in the power supply circuit 500 to the semiconductor device 510. It is possible to supply one or more arbitrary functional blocks among a plurality of included functional blocks. For example, when the semiconductor device 510 includes a first function block and a second function block, the line switching circuit 530 outputs the output voltage V _out from the selected voltage conversion circuit only to the first function block. , Second
, Or selectively to both the first and second functional blocks.

Here, a functional block refers to an arbitrary block for executing a predetermined function. A memory or an arithmetic circuit is an example of a functional block, and the present invention is not limited to the use of a specific functional block such as a memory or an arithmetic circuit.

The power supply device 560 except for the LC filter 230, the CPU 550, and the semiconductor device 510 can be formed on a single semiconductor chip. With current technology,
The LC filter 230 is preferably provided outside the semiconductor chip. However, in the future, all the components shown in FIG. 10 may be formed on a single semiconductor chip by incorporating the LC filter 230 also in the semiconductor chip.

(Embodiment 5) FIG. 13 shows a configuration of a power supply device 660 according to Embodiment 5 of the present invention. Power supply 66
0, the mode signal 551 output from the CPU 550
, One of the series regulator 210a, the series regulator 210b, and the switching regulator 220 included in the power supply circuit 600 is selected.

Power supply device 660 includes power supply circuit 600, selection circuit 620, path switching circuit 630, and LC filter 230.

The power supply circuit 600 includes a series regulator 210a, 210b and a switching regulator 220.
And Reference voltage V _ref generated by the reference voltage generating circuit 130, the series regulator 210a, 2
10b and the switching regulator 220.

Series regulators 210a, 210b
Will be described later with reference to FIGS. 17 (a) and 17 (b). The switching regulator 220 may have, for example, the configuration shown in FIG.

Series regulators 210a, 210b
Is output to the semiconductor device 61 via the path switching circuit 630.
0 is supplied. The output of the switching regulator 220 is supplied to the semiconductor device 610 via the LC filter 230 and the path switching circuit 630. Semiconductor device 610
Corresponds to the load of the power supply device 660.

The semiconductor device 610 has a plurality of functional blocks that can be executed independently of each other. One of the plurality of functional blocks is, for example, the memory 611. Another one of the plurality of functional blocks is, for example, the arithmetic circuit 612. The arithmetic circuit 612 includes a micro control unit (MCU) 613 and a digital signal processor (DSP) 614.

CPU 550 outputs a mode signal 551 indicating an operation mode in which semiconductor device 610 operates. For example, the mode signal 551 being “00” means that the operation mode of the semiconductor device 610 is a sleep mode (hereinafter, referred to as a sleep mode).
"First mode"). The fact that the mode signal 551 is “01” means that the memory 611 and the MCU
613 (hereinafter, referred to as “second mode”). The mode signal 551 is "10"
Means that the memory 611, the MCU 613, and the DSP 6
14 (hereinafter, referred to as “third mode”).

For example, when the semiconductor device 610 is used as a part of a communication system, there are a standby state in which communication is sent and a call state after receiving communication. The standby state corresponds to the second mode, and the talking state corresponds to the third mode.

In the standby state, the MCU 613 and the memory 61
1 works, but DSP 614 does not work. In the standby state, the MCU 613 does not consume much power because it performs intermittent operation or operates according to a low frequency. The current consumption of the MCU 613 in the standby state is, for example, 5 mA.

In the call state, the MCU 613 and the DSP 61
4 and the memory 611 operate. More power is consumed in the call state than in the standby state. The current consumption of the MCU 613 and the DSP 614 in the call state is, for example, 500 mA.

The sleep mode of the semiconductor device 610 corresponds to the first mode. In the sleep mode, only the content holding operation for holding the content of the information stored in the memory 611 is performed. The operation of retaining the content of the memory 611 is achieved by providing the memory 611 with a current corresponding to a leak current of the memory 611. Therefore, by reducing the leak current of the memory 611, the memory 6
11, the amount of current required for the content holding operation can be reduced. For example, by applying a bias voltage to the substrate to raise the threshold value of the MOS transistor, the memory 61
1 can be reduced. This allows
The current required for the content holding operation of the memory 611 can be reduced to 50 μA. The memory 611 includes a register, DRA
It may be a volatile memory represented by M, SRAM, or the like.

The power supply 660 supplies power only to the memory 611 in the first mode, supplies power to the memory 611 and MCU 613 in the second mode, and supplies power to the memory 611, MCU 613, and DSP 614 in the third mode. It is configured as follows. As described above, the function block to which power is supplied among the plurality of function blocks included in the semiconductor device 610 is changed according to the operation mode of the semiconductor device 610. This makes it possible to prevent power from being supplied to unnecessary function blocks in the sleep mode. As a result, leakage current can be prevented, and power consumption of the semiconductor device 610 can be reduced.

When the operation mode of the semiconductor device 610 is the first mode (ie, when the mode signal 551 is “00”), the selection circuit 620 selects the series regulator 210b, and the operation mode of the semiconductor device 610 is selected. Is the second mode (that is, the mode signal 551).
Is “01”), the series regulator 21
0a is selected and the operation mode of the semiconductor device 610 is the third mode (that is, the mode signal 551 is set to “1”).
0 "), the switching regulator 220
Select Such selection is achieved by determining the levels of the selection signals 151a, 151b, 152 according to the value of the mode signal 551.

The path switching circuit 630 responds to the path switching signal 552 output from the CPU 550 by
The path between 0 and the semiconductor device 610 is switched.

Specifically, when the series regulator 210b is selected by the selection circuit 620,
The path switching circuit 630 includes the series regulator 210b
Is electrically connected to the memory 611, the output of the series regulator 210b and the arithmetic circuit 612 (MCU6).
13 and the DSP 614). Thus, in the first mode, the series regulator 210
It becomes possible to supply the output voltage _Vout output from b only to the memory 611.

When the series regulator 210a is selected by the selection circuit 620, the path switching circuit 630 electrically connects the output of the series regulator 210a to the memory 611 and the MCU 613, and connects the output of the series regulator 210a to the DSP 614. And is electrically separated. Thus, in the second mode, the output voltage V _out output from the series regulator 210a
Can be supplied to the memory 611 and the MCU 613.

The switching circuit is selected by the selection circuit 620.
When the estimator 220 is selected, the
The path 630 is connected to the output of the switching regulator 220.
Connect the memory 611, MCU 613 and DSP 614
Connect pneumatically. As a result, in the third mode, the switch
Output voltage V output from switching regulator 220
_outTo the memory 611, the MPU 613 and the DSP 614.
Can be supplied to

FIG. 15 shows a configuration example of the path switching circuit 630. The path switching circuit 630 includes the PMOS transistor 6
32, 633 and a PMOS according to the path switching signal 552.
Logic circuit 631 for controlling transistors 632 and 633
And

In the first mode, the logic circuit 6 is turned off so that both the PMOS transistors 632 and 633 are turned off.
31 are configured. Thus, in the first mode,
The output voltage V _out output from the series regulator 210b is supplied only to the memory 611.

In the second mode, the PMOS transistor
632 is turned on, and the PMOS transistor 633 is turned off.
The logic circuit 631 is configured so as to be turned off. this
In the second mode, the series regulator 210
output voltage V output from a _outIs the memory 611 and
It is supplied to the MCU 613.

In the third mode, the logic circuit 6 is turned on so that both the PMOS transistors 632 and 633 are turned on.
31 are configured. Thereby, in the third mode,
The output voltage V _out output from the switching regulator 220 is stored in the memory 611, the MCU 613, and the DSP 6
14.

FIG. 16 shows the relationship between the path switching signal 552 output from the CPU 550 and the functional blocks to which power is supplied.

The path switching circuit 630 is connected to the power supply circuit 6
00 among the plurality of voltage conversion circuits included in
0 output voltage from one voltage conversion circuit selected by
Pressure V _outAre replaced with a plurality of functional blocks included in the semiconductor device 610.
Locks can be supplied to one or more optional functional blocks.
And enable. For example, the semiconductor device 610 is the first device
Function block, second function block, and third function block
In the case where the line switching circuit 630 includes
Output voltage V from voltage conversion circuit_outTo the first function block.
Function block only, the second function block only, the third function block
Block, or the first, second, and third function blocks.
Can be selectively supplied to any combination of
You.

FIG. 17A shows a series regulator 2
10 shows a configuration example of 10a. FIG. 17B shows a configuration example of the series regulator 210b.

The series regulator 210a includes ten PMOS transistors MP0 to MP9 connected in parallel.
As an output transistor 310a. The PMOS transistors MP1 to MP9 have the same size.

The series regulator 210b connects one PMOS transistor MP0 to the output transistor 310.
Included as b. Therefore, the series regulator 210b
Magnitude of the output current I _out that is output from the 1/10 of the magnitude of the output current I _out that is output from the series regulator 210a.

Series regulators 210a, 210b
To obtain the same response characteristics, the comparator 300
b is one of the driving ability of the comparator 300a.
/ 10 is enough.

[0133] Figure 14 shows an example of the relationship between the output current I _out and the voltage conversion efficiency η when converting the input voltage V _in (= 3.3V) the output voltage V _out (= 2.5V) .

[0134] Series region of the conversion efficiency is the highest output current I _out of the regulator 210b corresponds to a region of the first mode, the range of the conversion efficiency is the highest output current I _out of the series regulator 210a is in the region of the second mode Correspondingly, the voltage conversion characteristics of the series regulators 210a and 210b and the switching regulator 220 can be designed such that the region of the output current _Iout where the conversion efficiency of the switching regulator 220 is the highest corresponds to the region of the third mode.

The series regulator 210b is selected in the first mode, the series regulator 210a is selected in the second mode, and the switching regulator 220 is selected in the third mode. Thus, the voltage conversion circuit having the highest voltage conversion efficiency is selected in any of the first, second, and third modes.

The reason why the range of the output current I _out (load current) in which the series regulator can achieve high conversion efficiency is limited is as follows. (A) The reason why the conversion efficiency is degraded when the output current I _out (load current) decreases. , (B) output current I
_An explanation will be given separately for reasons why the conversion efficiency deteriorates when _out (load current) increases.

(A) The reason why the conversion efficiency is degraded when the output current I _out (load current) is small. The series regulator requires less self-current for the conversion operation than the switching regulator. There was almost no deterioration in efficiency (see FIG. 4). But,
In a series regulator, the conversion efficiency deteriorates as the load current approaches the value of the self-current, and this deterioration cannot be ignored. As shown in FIG. 14, the conversion efficiency of the series regulator 210a deteriorates in a region where the load current is small (for example, in the region of the first mode). Therefore, in order to achieve higher conversion efficiency in the region of smaller load current, a series regulator that operates with smaller self-current is required. The series regulator 210b is
It is designed so that high conversion efficiency can be realized in a small load current region where high conversion efficiency cannot be realized by a. By combining the series regulators 210a and 210b, high conversion efficiency can be realized in the first mode region and the second mode region.

(B) The reason why the conversion efficiency deteriorates when the output current I _out (load current) increases. Although not shown in FIG. 14, the conversion efficiency of the series regulator 210b is in the region where the load current is large (for example, the second In the mode region), the conversion efficiency is lower than the conversion efficiency of the series regulator 210a. The reason is that the upper limit of the load current that can be supplied by the series
This is because the conversion efficiency is degraded as the load current increases, because it is limited by the current supply capacity of 0b. Therefore, the series regulator 210a shown in FIG. 17A and the series regulator 210b shown in FIG. 17B are configured to have different current supply capacities.

The power supply device 660 excluding the LC filter 230, the CPU 550, and the semiconductor device 610 can be formed on a single semiconductor chip. With current technology,
The LC filter 230 is preferably provided outside the semiconductor chip. However, in the future, all the components shown in FIG. 13 may be formed on a single semiconductor chip by incorporating the LC filter 230 also in the semiconductor chip.

In the example shown in FIG.
Are three voltage conversion circuits. However, the present invention is not limited to this. The power supply circuit 100 may have any number of four or more voltage conversion circuits.

In all the embodiments described above, it is not always necessary to select one of the plurality of voltage conversion circuits so that the conversion efficiency of the power supply circuit is optimized. For example, one of the plurality of voltage conversion circuits is selected such that the conversion efficiency of the selected voltage conversion circuit is higher than the conversion efficiency of at least one voltage conversion circuit not selected among the plurality of voltage conversion circuits. Power supply devices that do this are included within the scope of the present invention. Thus, the power supply device that improves the conversion efficiency of the power supply circuit by selecting one of the plurality of voltage conversion circuits is all included in the scope of the present invention.

[0142]

According to the present invention, it is possible to provide a power supply device having improved conversion efficiency by selecting one of a plurality of voltage conversion circuits. Thus, power consumption of the power supply device can be reduced.

Furthermore, by selecting one of the plurality of voltage conversion circuits according to the output current flowing from the power supply circuit to the load, the conversion efficiency is improved at least for a predetermined range of output current. A power supply can be provided.

Further, by selecting one of a plurality of voltage conversion circuits according to a mode signal indicating the operation mode of the semiconductor device, a power supply device having improved conversion efficiency in each operation mode of the semiconductor device Can be provided.

Further, by switching the path between the voltage conversion circuit and the semiconductor device selected according to the mode signal, it is possible to prevent power from being supplied to unnecessary circuits. Thus, leakage current generated in the semiconductor device can be reduced. As a result, power consumption of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a power supply circuit 100 according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between an output current I _out and a voltage conversion efficiency η.

FIG. 3 is a diagram showing a configuration of a power supply circuit 200 according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a relationship between an output current I _out and a voltage conversion efficiency η.

FIG. 5 is a diagram showing a configuration example of a series regulator 210.

FIG. 6 is a diagram showing a configuration example of a switching regulator 220.

FIG. 7 is a diagram showing a waveform of a current flowing through a coil L of the LC filter 230 and a waveform of a voltage applied to both ends of the coil L.

FIG. 8 is a diagram showing a configuration example of a current monitor 140 and a selection circuit 150.

FIG. 9 is a diagram showing a configuration of a semiconductor device 300 according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a power supply device 560 according to Embodiment 4 of the present invention.

11 is a diagram illustrating a configuration example of a path switching circuit 530. FIG.

FIG. 12 shows a path switching signal 5 output from the CPU 550.
FIG. 5 is a diagram showing a relationship between a functional block 52 and a functional block to which power is supplied.

FIG. 13 is a diagram showing a configuration of a power supply device 660 according to Embodiment 5 of the present invention.

FIG. 14 is a diagram illustrating an example of a relationship between an output current I _out and a voltage conversion efficiency η.

FIG. 15 is a diagram illustrating a configuration example of a path switching circuit 630.

FIG. 16 shows a path switching signal 5 output from the CPU 550.
FIG. 5 is a diagram showing a relationship between a functional block 52 and a functional block to which power is supplied.

17A is a diagram illustrating a configuration example of a series regulator 210a, and FIG. 17B is a diagram illustrating a configuration of a series regulator 210b.
FIG. 3 is a diagram showing an example of the configuration of FIG.

[Explanation of symbols]

 100, 200 power supply circuit 110, 120 voltage conversion circuit 130 reference voltage generation circuit 140 current monitor 150 selection circuit 151, 152 selection signal 160 load 210, 210a, 210b series regulator 220 switching regulator 230 LC filter 500, 600 power supply circuit 510, 610 Semiconductor device 511, 611 Memory 512, 612 Arithmetic circuit 613 MCU 614 DSP 520, 620 Selection circuit 530, 630 Path switching circuit 550 CPU 551 Mode signal 552 Path switching signal 560, 660 Power supply

Continued on the front page (72) Inventor Masayoshi Kinoshita 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. Person Jun Kajiwara 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture (72) Inventor Shinichi Yamamoto 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (8)

[Claims] 1. A power supply device comprising a power supply circuit for converting an input voltage to an output voltage and supplying the output voltage to a load, wherein the power supply circuit comprises: a plurality of voltage conversion circuits having different conversion efficiencies; A selection circuit for selecting one of the plurality of voltage conversion circuits so as to improve the conversion efficiency of the power supply circuit.
Power supply. 2. The power supply device according to claim 1, wherein the number of the plurality of voltage conversion circuits is three or more. 3. A current detection circuit for detecting an output current flowing from the power supply circuit to the load, wherein the selection circuit selects one of the plurality of voltage conversion circuits according to the output current. The power supply device according to claim 1, wherein: 4. The power supply device according to claim 1, wherein said plurality of voltage conversion circuits include a series regulator and a switching regulator. 5. The semiconductor device according to claim 1, wherein the load is a semiconductor device including at least one functional block, the semiconductor device operates in each of a plurality of operation modes, and the selection circuit is a mode indicating an operation mode of the semiconductor device. The power supply device according to claim 1, wherein the power supply device receives a signal, and selects one of the plurality of voltage conversion circuits according to the mode signal. 6. The power supply device according to claim 5, further comprising a path switching circuit that switches a path between the voltage conversion circuit selected according to the mode signal and the semiconductor device. 7. The plurality of voltage conversion circuits include a series regulator and a switching regulator, the semiconductor device includes a memory and an arithmetic circuit, and the semiconductor device has at least a first mode and a second mode. Operates, in the first mode, the path switching circuit switches the path so that an output voltage output from the series regulator selected by the selection circuit is supplied to the memory, and in the second mode, 7. The power supply device according to claim 6, wherein the path switching circuit switches the path such that an output voltage output from the switching regulator selected by the selection circuit is supplied to the memory and the arithmetic circuit. . 8. The plurality of voltage conversion circuits include a first series regulator, a second series regulator, and a switching regulator, the semiconductor device includes a memory, a first operation circuit, and a second operation circuit, The semiconductor device operates at least in a first mode, a second mode, and a third mode. In the first mode, the path switching circuit outputs an output from the first series regulator selected by the selection circuit. The path is switched so that a voltage is supplied to the memory. In the second mode, the path switching circuit outputs an output voltage output from the second series regulator selected by the selection circuit to the memory and the memory. The path is switched so as to be supplied to the first arithmetic circuit. In the third mode, the path switching circuit The power supply device according to claim 6, wherein the path is switched such that an output voltage output from the switching regulator selected by the selection circuit is supplied to the memory, the first arithmetic circuit, and the second arithmetic circuit. .