JP2010063290A - Power supply control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply control circuit of high conversion efficiency by suppressing fluctuation of an output voltage. <P>SOLUTION: The power supply control circuit is equipped with: the first control circuit which, upon inputting a first command signal for instructing the generation of an output voltage at a target level from an input voltage, controls the conductive state of a first transistor where the input voltage is applied to an input electrode according to a difference between a first feedback voltage corresponding to the output voltage and a first voltage corresponding to the target level; an error amplifying circuit which charges/discharges a capacitor at the voltage corresponding to a difference between a second feedback voltage corresponding to the output voltage and a second reference voltage corresponding to the target level; a second control circuit which, upon inputting a second command signal for instructing the generation of the output voltage at the target level from the input voltage, controls on/off of a second transistor where the input voltage is applied to the input electrode according to the voltage of the capacitor; and a charge circuit which charges the capacitor at a charge voltage corresponding to the level of input voltage upon inputting a first command signal, and stops charging the capacitor at the charge voltage upon inputting a second command signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power supply control circuit.

  When a desired output voltage is generated from a voltage of a battery or the like and supplied to a load, a switching power supply circuit is often used. In general, the conversion efficiency when the switching power supply circuit generates a desired output voltage is high at a heavy load when the current flowing through the load is large, and low at a light load when the current flowing through the load is small. Therefore, in order to improve the conversion efficiency at light load, a power supply control circuit that generates a desired output voltage by switching from a switching power supply circuit to a linear regulator may be used (for example, Patent Document 1).

  FIG. 3 shows an example of a power supply control circuit 100 that can switch between an LDO (Low Dropout) regulator 500 and a switching power supply circuit 510. The power supply control circuit 100 controls the operation of the control circuit 200 for generating the output voltage Vout by the LDO regulator 500 according to the control signal CONT1 output from the microcomputer (not shown), and according to the control signal CONT2. This is a circuit for controlling the operation of the switching control circuit 210 for generating the output voltage Vout by the switching power supply circuit 510.

  For example, the control circuit 200 stops the operation of the LDO regulator 500 when the control signal CONT1 becomes a low level (hereinafter referred to as L level), and turns off the LDO regulator 500 when the control signal CONT1 becomes a high level (hereinafter referred to as H level). Make it work. Specifically, when the control signal CONT1 becomes L level, the generation of the bias currents of the error amplifier circuit 300 and the reference voltage circuit 310 is stopped. On the other hand, when the control signal CONT1 becomes H level, generation of the bias current of the error amplifier circuit 300 and the reference voltage circuit 310 is started. Therefore, the error amplifier circuit 300 compares the voltage obtained by dividing the output voltage Vout with the voltage of the reference voltage circuit 310 so that the output voltage Vout becomes a desired level, and controls the on-resistance of the PMOS transistor 320. .

  For example, the switching control circuit 210 stops the operation of the switching power supply circuit 510 when the control signal CONT2 becomes L level, and operates the switching power supply circuit 510 when the control signal CONT2 becomes H level. Specifically, when the control signal CONT2 becomes L level, generation of bias currents of the reference voltage circuit 400, the error amplification circuit 410, the triangular wave oscillation circuit 420, the comparator 430, and the drive circuit 440 in the switching control circuit 210 is generated. Is stopped. On the other hand, when the control signal CONT2 becomes H level, generation of bias currents of the respective circuits constituting the switching control circuit 210 is started. Therefore, the error amplifier circuit 410 generates a voltage Ve corresponding to the difference between the voltage of the reference voltage circuit 400 and the voltage obtained by dividing the output voltage Vout. The comparator 430 compares the voltage Ve with the triangular wave from the triangular wave oscillation circuit 420 and outputs a PWM (Pulse Wide Modulation) signal Vpwm. The drive circuit 440 turns on the PMOS transistor 450 based on the L level of the PWM signal Vpwm, and turns off the PMOS transistor 450 based on the H level of the PWM signal Vpwm. Further, the output voltage Vout that changes when the PMOS transistor 450 is turned on / off is negatively fed back to the error amplifier circuit 410 via the voltage dividing resistor as described above. Therefore, the output voltage Vout is controlled by the switching control circuit 210 so as to have a desired level.

  By the way, when the control signal CONT2 is at the L level, the bias current of each circuit in the switching control circuit 210 is stopped, so that the voltage Ve output from the error amplifier circuit 410 is reduced to 0V. In order to set the output voltage Vout to a desired level when the control signal CONT2 becomes H level, the comparator 430 needs to output a PWM signal Vpwm having a duty ratio determined by the input voltage Vin and the desired output voltage Vout. There is. Therefore, as shown in FIG. 4, for example, when the control signal CONT2 becomes H level at time T1, the error amplifier circuit 410 responds to the difference between the voltage of the reference voltage circuit 400 and the voltage obtained by dividing the output voltage Vout. The capacitor 600 starts to be charged with the voltage. Then, the error amplifier circuit 410 increases the voltage Ve until time T2 when the duty ratio of the PWM signal Vpwm becomes a duty ratio determined by the input voltage Vin and the desired output voltage Vout.

Thus, even when the control signal CONT2 becomes H level at time T1, the switching control circuit 210 cannot generate the desired output voltage Vout until time T2. Therefore, when the operation of the LDO regulator 500 is stopped and the switching power supply circuit 510 is operated when the load changes from a light load to a heavy load, the output voltage Vout decreases. Therefore, for example, in Patent Document 1, when the load changes from a light load to a heavy load, the LDO regulator 500 is operated until the switching power supply circuit 510 generates a desired output voltage Vout until the output voltage Vout. Is suppressed.
JP 2003-9515 A

  Incidentally, the period TA until the control signal CONT2 becomes H level and the switching power supply circuit generates the desired output voltage Vout varies depending on the level of the input voltage Vin. Specifically, for example, when the input voltage Vin from the battery is low, compared with the case where the input voltage Vin from the battery is high, the L level of the PWM signal Vpwm is generated in order to generate the output voltage Vout at a desired level. It is necessary to increase the duty ratio. That is, when the input voltage Vin decreases, the error amplifier circuit 410 needs to increase the voltage Ve to a higher voltage. Thus, the period TA changes according to the level of the input voltage Vin. Therefore, when using a battery or the like having a large fluctuation in the input voltage Vin, it is necessary to lengthen the period TA in order to suppress a decrease in the output voltage Vout when the load changes from a light load to a heavy load. In addition, in the period TA, the LDO regulator 500 is operating for the purpose of preventing the output voltage Vout from being lowered, even though it is under heavy load, so that there is a problem that conversion efficiency deteriorates.

  The present invention has been made in view of the above problems, and an object thereof is to provide a power supply control circuit with high conversion efficiency while suppressing fluctuations in output voltage.

  In order to achieve the above object, the power supply control circuit of the present invention, when a first instruction signal instructing generation of an output voltage of a target level from an input voltage is input, the first feedback voltage according to the output voltage and the A first control circuit for controlling a conduction state of a first transistor in which the input voltage is applied to an input electrode according to a difference from a first reference voltage according to a target level; and a second feedback according to the output voltage. An error amplifying circuit for charging and discharging a capacitor with a voltage according to a difference between the voltage and a second reference voltage according to the target level; and a second instruction signal for instructing generation of the output voltage at the target level from the input voltage Is input, the second control circuit that controls on / off of the second transistor applied with the input voltage to the input electrode according to the voltage of the capacitor, and when the first instruction signal is input, Input power Charging the capacitor with a charging voltage corresponding to the level of, when the second instruction signal is input, characterized in that it comprises a charging circuit that stops charging of the capacitor by the charging voltage.

  A power supply control circuit with high conversion efficiency can be provided while suppressing fluctuations in output voltage.

At least the following matters will become apparent from the description of the present specification and the accompanying drawings.
FIG. 1 is a diagram showing a configuration of a power supply control circuit 10 according to an embodiment of the present invention. The power supply control circuit 10 is used, for example, to generate a desired output voltage Vout to be supplied to a load from an input voltage Vin that is a voltage of a battery. The power supply control circuit 10 operates the LDO regulator 20 to generate the output voltage Vout when the control signal CONT from the microcomputer (not shown) is at L level, and the switching power supply when the control signal CONT is at H level. This is a circuit for operating the circuit 21. Note that the load (not shown) of this embodiment is, for example, a DSP (Digital Signal Processor), and the microcomputer sets the control signal CONT to the L level in the standby state where the DSP current consumption is low, and the DSP consumption. In an operating state with a large amount of current, the control signal CONT is set to H level. That is, the microcomputer operates the LDO regulator 20 when the DSP to which the output voltage Vout is applied is lightly loaded, and operates the switching power supply circuit 21 when the DSP is heavyly loaded. The L level control signal CONT in the present embodiment corresponds to the first instruction signal of the present invention, and the H level control signal CONT in the present embodiment corresponds to the second instruction signal of the present invention.

  The power supply control circuit 10 includes a control circuit 30, a switching control circuit 31, and a charging circuit 32. Although terminals are not shown in FIG. 1, it is assumed that the power supply control circuit 10 and the PMOS transistors 43 and 55 in this embodiment are integrated.

  When the control signal CONT becomes L level, the control circuit 30 (first control circuit) operates the LDO regulator 20 including the control circuit 30, the PMOS transistor 43, and the resistors R1 and R2 to generate a desired output voltage from the input voltage Vin. It is a circuit that generates Vout. The control circuit 30 stops the operation of the LDO regulator 20 when the control signal CONT becomes H level. The control circuit 30 includes a reference voltage circuit 40, an error amplifier circuit 41, and a buffer circuit 42.

  The reference voltage circuit 40 is a circuit that generates a reference voltage Vref1 (first reference voltage) of a predetermined level such as a band gap voltage.

  The error amplifier circuit 41 is a circuit that amplifies a difference between the reference voltage Vref1 and a voltage Vfb1 (first feedback voltage) obtained by dividing the output voltage Vout by resistors R1 and R2.

  The buffer circuit 42 is a circuit that buffers the output of the error amplifying circuit 40 so that the on-resistance of the PMOS transistor 43 (first transistor) that is a power transistor can be controlled.

  In the present embodiment, the voltage Vfb1 corresponding to the output voltage Vout is fed back to the inverting input terminal of the error amplifier circuit 41. Therefore, the error amplifier circuit 41 controls the on-resistance of the PMOS transistor 43 via the buffer circuit 42 so that the voltage Vfb1 matches the level of the reference voltage Vref1. As a result, the LDO regulator 20 generates an output voltage Vout at a desired level.

  In the present embodiment, when the control signal CONT becomes L level, the reference voltage circuit 40, the error amplifier circuit 41, and the buffer circuit 42 in the control circuit 30 are operated to generate a bias current. . Further, when the control signal CONT becomes H level, the generation of the bias current for operating each circuit in the control circuit 30 is stopped. Further, the buffer circuit 42 assumes that the output becomes H level when the control signal CONT becomes H level.

  When the control signal CONT becomes H level, the switching control circuit 31 operates the switching power supply circuit 21 including the switching control circuit 31, the PMOS transistor 55, the diode D1, the inductor L1, the capacitors C1 and C2, and the resistors R3 to R5. , A circuit for generating a desired output voltage Vout from the input voltage Vin. Further, when the control signal CONT becomes L level, the operation of the switching power supply circuit 21 is stopped. The switching control circuit 31 includes a reference voltage circuit 50, an error amplification circuit 51, a triangular wave oscillation circuit 52, a comparator 53, and a drive circuit 54. Note that the triangular wave oscillation circuit 52, the comparator 53, and the drive circuit 54 of the present embodiment correspond to a second control circuit of the present invention.

  The reference voltage circuit 50 is a circuit that generates a reference voltage Vref2 (second reference voltage) of a predetermined level such as a band gap voltage.

  The error amplification circuit 51 (error amplification circuit) is a circuit that amplifies the difference between the reference voltage Vref2 and the voltage Vfb2 (second feedback voltage) obtained by dividing the output voltage Vout by the resistors R3 and R4. In the error amplifier circuit 51 of this embodiment, a resistor for performing phase compensation of the feedback loop of the switching power supply circuit 21 between the inverting input terminal to which the voltage Vfb2 is input and the output of the error amplifier circuit 51. R5 and capacitor C2 are connected. In the present embodiment, a voltage at a node where the output of the error amplifier circuit 51 and the capacitor C2 are connected is a voltage Ve.

  The triangular wave oscillation circuit 52 is a circuit that outputs a triangular wave Vosc having a predetermined period. The triangular wave Vosc in the present embodiment is a signal having the same rise time and fall time, but is not limited thereto. For example, it may be a sawtooth-shaped triangular wave whose rise time is longer than the fall time.

  The comparator 53 is a circuit that compares the output from the error amplifier circuit 51 with the triangular wave Vosc and outputs a PWM signal Vpwm (comparison signal). In the present embodiment, the voltage Ve is input to the inverting input terminal of the comparator 53, and the triangular wave Vosc is input to the non-inverting input terminal of the comparator 53. Therefore, when the level of the triangular wave becomes lower than the level of the voltage Ve, the PWM signal Vpwm becomes L level, and when the level of the triangular wave becomes higher than the level of the voltage Ve, the PWM signal Vpwm becomes H level. In the present embodiment, the period occupied by the L level in one cycle of the PWM signal Vpwm is defined as the duty ratio of the PWM signal Vpwm.

  When the PWM signal Vpwm is at L level, the drive circuit 54 outputs an L level drive signal to turn on the PMOS transistor 55. When the PWM signal Vpwm is at H level, an H level drive signal is output to turn off the PMOS transistor 55.

  The input voltage Vin is applied to the source electrode of the PMOS transistor 55 (second transistor), and the drain electrode is connected to the cathode of the diode D1 and one end of the inductor L1. Further, since the inductor L1 and the capacitor C1 constitute an LPF (Low Pass Filter), the voltage change at the cathode of the diode D1 is smoothed. When the PMOS transistor 55 is turned on, the cathode of the diode D1 rises to the input voltage Vin, so that the output voltage Vout that is the charging voltage of the capacitor C1 also rises. On the other hand, when the PMOS transistor 55 is turned off, the cathode of the diode D1 becomes a voltage lower than the ground GND by the forward voltage of the diode D1, so that the voltage output voltage Vout decreases. In the present embodiment, when the voltage Vfb2 becomes higher than the reference voltage Vref2, the capacitor C2 is discharged and the voltage Ve decreases. For this reason, the duty ratio of the PWM signal Vpwm decreases, and the output voltage Vout decreases. On the other hand, when the voltage Vfb2 becomes lower than the reference voltage Vref2, the capacitor C2 is charged and the voltage Ve increases. For this reason, the duty ratio of the PWM signal Vpwm increases, and the output voltage Vout increases. As described above, the output voltage Vout of the present embodiment is controlled to be a desired level based on the reference voltage Vref2.

  In the present embodiment, when the control signal CONT becomes H level, a bias current for operating each of the reference voltage circuit 50, the error amplifier circuit 51, the triangular wave oscillation circuit 52, and the comparator 53 is generated. . In addition, when the control signal CONT becomes L level, the generation of the bias current for operating each of the above-described circuits in the switching control circuit 31 is stopped. Further, the drive circuit 54 of the present embodiment assumes that the output becomes H level when the control signal CONT becomes L level.

  The charging circuit 32 generates a charging voltage Vc corresponding to the input voltage Vin. When the control signal CONT becomes L level, the charging circuit 32 charges the capacitor C2 with the charging voltage Vc, and when the control signal CONT becomes H level, This circuit stops charging. In other words, the charging circuit 32 is a circuit that supplies the initial voltage Ve when the switching power supply circuit 21 starts operating when the operation of the switching power supply circuit 21 is stopped.

  The charging circuit 32 includes a reference voltage circuit 60, an error amplification circuit 61, a switch circuit 62, and resistors R6 and R7.

  The reference voltage circuit 60 is a circuit that generates a reference voltage Vref3 (third reference voltage) of a predetermined level such as a band gap voltage.

  The reference voltage Vref3 is applied to the non-inverting input terminal of the error amplifier circuit 61, and the other end of the resistor R6 to which the input voltage Vin is applied to one end is connected to the inverting input terminal. Further, a resistor R 7 is connected between the inverting input terminal of the error amplifier circuit 61 and the output of the error amplifier circuit 61. Therefore, the error amplifier circuit 61 operates as an inverting amplifier circuit that inverts and amplifies the input voltage Vin with a gain corresponding to the resistance values of the resistors R6 and R7. Here, when the voltage of the node of the output of the error amplifier circuit 61 is the charging voltage Vc, the charging voltage Vc is Vc = Vref3−R7 / R6 (Vin−Vref3). Note that the reference voltage circuit 60, the error amplifier circuit 61, and the resistors R6 and R7 in the present embodiment correspond to the inverting amplifier circuit of the present invention.

  The switch circuit 62 is a circuit that is turned on when the control signal CONT is at the L level and turned off when the control signal CONT is at the H level. For example, a transmission gate circuit can be used. Further, the charging voltage Vc is applied to one end of the switch circuit 62, and the other end is connected to a node to which the capacitor C2 and the inverting input terminal of the comparator 53 are connected. Therefore, when the control signal CONT is at the L level, the capacitor C2 is charged with the charging voltage Vc, so that the voltage Ve becomes Ve = Vc. Therefore, when the charging voltage Vc is supplied to the capacitor C2 as an initial voltage and the control signal CONT becomes H level, the comparator 53 can generate the PWM signal Vpwm having a duty ratio corresponding to the level of the charging voltage Vc.

  Incidentally, the duty ratio for generating the desired output voltage Vout is uniquely determined by the level of the input voltage Vin and the level of the desired output voltage Vout. In the present embodiment, since the amplitude of the triangular wave Vosc and the center level of the amplitude are respectively predetermined levels, the level of the voltage Ve for obtaining a desired duty ratio is uniquely determined according to the level of the input voltage Vin. It will be. As described above, in the present embodiment, the relational expression Ve = Vc = Vref3−R7 / R6 (Vin−Vref3) is established between the input voltage Vin and the voltage Ve. Therefore, in this embodiment, the resistance values of the resistors R6 and R7 and the level of the reference voltage Vref3 are set so that the desired output voltage Vout can be obtained when the input voltage Vin changes.

  Here, the operation of the power supply control circuit 10 when the DSP (not shown) as the load is changed from the standby state to the operating state and the microcomputer (not shown) changes the control signal CONT from the L level to the H level will be described.

  First, when the control signal CONT is at the L level, the LDO regulator 20 operates to generate a desired output voltage Vout from the input voltage Vin. On the other hand, the operation of the switching control circuit 31 is stopped. Further, since the switch 62 in the charging circuit 32 is on, the capacitor C2 is charged with the charging voltage Vc, and the charging voltage Vc is supplied as the initial voltage.

  Next, when the control signal CONT becomes H level, the operation of the LDO regulator 20 is stopped. Further, since the switch 62 is turned off, the charging of the capacitor C2 by the charging voltage Vc is stopped. Further, since a bias current for operating each of the reference voltage circuit 50, the error amplifier circuit 51, the triangular wave oscillation circuit 52, and the comparator 53 in the switching control circuit 31 is generated, the switching control circuit 31 starts operating. To do. As described above, since the level of the voltage Ve is equal to the charging voltage Vc, the comparator 53 outputs the PWM signal Vpwm corresponding to the level of the charging voltage Vc when the control signal CONT becomes H level. In the present embodiment, the voltage Vc is changed according to the level of the input voltage Vin so that the desired output voltage Vout is generated even when the level of the input voltage Vin changes. That is, as shown in FIG. 2, when the input voltage Vin is high, the charging circuit 32 decreases the voltage Vc, so the comparator 53 outputs the PWM signal Vpwm having a small duty ratio. On the other hand, when the input voltage Vin is low, the charging circuit 32 increases the voltage Vc, so the comparator 53 outputs a PWM signal Vpwm having a large duty ratio. Thus, when the control signal CONT becomes H level, the switching power supply circuit 21 immediately generates the output voltage Vout having the same level as the desired output voltage Vout generated by the LDO regulator 20. Therefore, when the power supply control circuit 10 switches the operation from the LDO regulator 20 to the switching power supply circuit 21, it is possible to suppress fluctuations in the output voltage Vout.

  The power supply control circuit 10 of the present embodiment configured as described above operates the control circuit 30 in order to operate the LDO regulator 20 that generates the desired output voltage Vout when the control signal CONT becomes L level. Further, the charging circuit 32 generates a voltage Vc that decreases as the input voltage Vin increases. The charging circuit 32 charges the capacitor C2 with the voltage Vc when the control signal CONT is at the L level. When the control signal CONT becomes H level, the switching control circuit 31 starts to operate in order to operate the switching power supply circuit 21 that generates the desired output voltage Vout. Then, the charging circuit 32 stops charging the capacitor C2. Since the switching control circuit 31 generates the PWM signal Vpwm based on the voltage Vc that decreases as the input voltage Vin increases, for example, compared with a case where the voltage Vc decreases to 0 V, the desired output voltage Vout Can be generated quickly. Therefore, fluctuations in the output voltage Vout are suppressed. In addition, since the power supply control circuit 10 of the present embodiment generates the output voltage Vout in one of the LDO regulator 20 and the switching power supply circuit 21, the output voltage Vout is generated using both circuits. Compared to the case, the conversion efficiency can be improved.

  In the present embodiment, the charging circuit 32 generates the voltage Vc that decreases as the input voltage Vin increases, that is, the voltage Vc that decreases the duty ratio of the PWM signal Vpwm when the input voltage Vin increases. . The switching control circuit 31 generates a PWM signal Vpwm that can generate a desired output voltage Vout based on the voltage Vc, and controls on / off of the PMOS transistor 55. As a result, the switching power supply circuit 21 immediately generates the output voltage Vout at the same level as the desired output voltage Vout generated by the LDO regulator 20, so that the conversion efficiency can be improved while suppressing the fluctuation of the output voltage Vout. .

  In this embodiment, the difference between the input voltage Vin and the reference voltage Vref3 is generated by the error amplification circuit 61 and the inverting amplification circuit including the resistors R6 and R7, and the charge voltage Vc is generated. Vc = Vref3−R7 / R6 (Vin-Vref3). In this embodiment, each of the resistors R6 and R7 realizes the same type of resistor with an integrated circuit, and the reference voltage Vref uses a band gap voltage or the like as described above. Therefore, the charging voltage Vc is a highly accurate voltage with little variation. For this reason, since the accuracy of the initial voltage of the voltage Ve in the switching control circuit 21 can be improved, in this embodiment, when the control signal CONT becomes H level, the PWM signal Vpwm having a desired duty ratio can be generated with high accuracy. That is, when the control signal CONT becomes H level, the desired output voltage Vout can be generated with high accuracy, so that the conversion efficiency can be improved while suppressing the fluctuation of the output voltage Vout.

  In the present embodiment, when the L-level control signal CONT for operating the LDO regulator 20 is input to the switching control circuit 31, the PMOS transistor 55 is turned off. That is, the operation of the switching power supply 21 is stopped. Further, when an H level control signal CONT for operating the switching power supply circuit 21 is input to the control circuit 30, the PMOS transistor 43 is turned off. That is, the operation of the LDO regulator 20 is stopped. Therefore, it is possible to reliably prevent the LDO regulator 20 and the switching power supply circuit 21 from operating together, thereby improving the conversion efficiency.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  In the present embodiment, the PMOS transistors 43 and 55 are integrated. However, for example, the PMOS transistor 55 may not be integrated and may be configured by a discrete transistor.

  In the present embodiment, the reference voltage circuits 40, 50, and 60 are used. For example, the reference voltage from the reference voltage circuit that generates the reference voltage regardless of the level of the control signal CONT is used as the error amplification circuit. Even if the signals are supplied to the non-inverting input terminals 41, 51 and 61, the same effects as in the present embodiment can be obtained.

  The switching power supply circuit 21 of the present embodiment is a chopper type circuit. However, for example, even if it is a synchronous rectification type switching power supply circuit using an NMOS transistor instead of the diode D1, the same effect as that of the present embodiment can be obtained. Obtainable. At this time, the drive circuit 54 drives not only the PMOS transistor 55 but also the above-described NMOS transistor.

It is a figure which shows the power supply control circuit 10 which is one Embodiment of this invention. 4 is a diagram for explaining the operation of the power supply control circuit 10. FIG. It is a figure which shows an example of a power supply control circuit. It is a figure for demonstrating operation | movement of a power supply control circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Power supply control circuit 20 LDO (Low Dropout) regulator 21 Switching power supply circuit 30 Control circuit 31 Switching control circuit 40, 50, 60 Reference voltage circuit 41, 51, 61 Error amplification circuit 42 Buffer circuit 43, 55 PMOS transistor 52 Triangular wave oscillation circuit 53 Comparator 54 Drive Circuit 62 Switch Circuit R1-R7 Resistor C1, C2 Capacitor D1 Diode L1 Inductor

Claims (4)

When a first instruction signal for instructing generation of an output voltage of a target level from the input voltage is input, according to a difference between a first feedback voltage corresponding to the output voltage and a first reference voltage corresponding to the target level. A first control circuit for controlling a conduction state of a first transistor in which the input voltage is applied to an input electrode;
An error amplifying circuit that charges and discharges a capacitor with a voltage according to a difference between a second feedback voltage according to the output voltage and a second reference voltage according to the target level;
When a second instruction signal for instructing generation of the output voltage at the target level is input from the input voltage, the second transistor to which the input voltage is applied to the input electrode is turned on / off according to the voltage of the capacitor. A second control circuit for controlling;
When the first instruction signal is input, the capacitor is charged with a charging voltage corresponding to the level of the input voltage, and when the second instruction signal is input, charging of the capacitor with the charging voltage is stopped. A charging circuit;
A power supply control circuit comprising: The power supply control circuit according to claim 1,
The charging circuit is
When the first instruction signal is input, the capacitor is charged with the charging voltage such that a period during which the second transistor is turned off becomes longer as the level of the input voltage increases, and the second instruction signal Is input, the charging of the capacitor by the charging voltage is stopped,
A power supply control circuit. The power supply control circuit according to claim 1 or 2,
The error amplification circuit includes:
When the level of the second feedback voltage is higher than the level of the second reference voltage, the capacitor is discharged so that the voltage of the capacitor decreases, and the level of the second feedback voltage is lower than the level of the second reference voltage. If so, charge the capacitor so that the voltage of the capacitor rises,
The second control circuit includes:
The comparison signal for controlling on / off of the second transistor is set to a voltage of the capacitor and a triangular wave of a predetermined cycle so that the period during which the second transistor is turned off becomes longer as the voltage level of the capacitor decreases. Including a comparison circuit that outputs based on
The charging circuit is
An inverting amplifier circuit that outputs the charging voltage, the level of which decreases when the level of the input voltage increases, according to the difference between the input voltage and a third reference voltage of a predetermined level;
When the first instruction signal is input, the capacitor is turned on to charge the capacitor with the charging voltage, and when the second instruction signal is input, the capacitor is turned off to stop charging the capacitor with the charging voltage. A switch circuit to
Including,
A power supply control circuit. The power supply control circuit according to any one of claims 1 to 3,
The first control circuit includes:
When the second instruction signal is input, the first transistor is turned off,
The second control circuit includes:
When the first instruction signal is input, the second transistor is turned off;
A power supply control circuit.

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