JPS60191513A - Digital type integration circuit - Google Patents

Abstract

PURPOSE:To switch the frequency characteristic of an integration circuit in response to a mode command signal by forming the titled circuit with a variable frequency dividing means, a gate means and an up-down counter. CONSTITUTION:A clock pulse S1 is frequency-divided at a prescribed frequency dividing ratio in response to the mode command signal at a variable frequency dividing means 4 and its frequency division output S2 is used as an input to the gate means 5. When an input digital signal D1 is coincident with a prescribed value D0, the gate means 5 inhibits the frequency division output S2 and when said signal D1 is dissident with the value D0, the output S2 is taken as a gate output S3, and is used as a clock input of an up-down counter 6. At least one bit of the most significant digit of the signal D1 is inputted to the counter 6 as an up-down signal and a gate output S3 is subjected to up or down count. Then an output digital signal D2 is obtained from the counter 6. Thus, the frequency characteristic of the integration circuit is switched in response to the mode command signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital integration circuit that obtains a binary output digital signal by adding integral characteristics to a binary input digital signal.

Structure of a conventional example and its problems FIG. 1 shows a conventional example of an analog type integrating circuit, and FIG. 2 shows its operating waveform diagram.

The components of the analog integration circuit are an operational amplifier 1, an input resistor 2. This is the return capacitor 3. Now, the input voltage E,
When a potential difference occurs at E2, a current flows through the input resistor 2, and the return capacitor 3 is charged with an electric charge, resulting in the output voltage E. changes. Output voltage E. As shown in Fig. 2, when El>E2, the potential decreases (~1., 14~t5), x, 4z2
When the potential stops (1, ~t2+t3~14.15~
), and when E+<E2, the potential moves upward (t2 to t3). The transfer function G(s) of this circuit is G(s)
=-・・・・・・・・・・・・・・・ (1) T. However, T=CB, C is the capacitance value 1R of the return capacitor 3, and S is the resistance value of the input resistor 2. That is, it has integral characteristics.

Note that the magnitude of the current flowing through the input resistor 2 is Q2[, the input voltage E1. Since it is proportional to the potential difference of E2, charging and discharging of the charge of the feedback capacitor 3 is also proportional. However, the slope of the potential of the output voltage E, ) shown in FIG. 2 changes in proportion to the potential difference between E+ + E2.

When converting such an integrating circuit into an integrated circuit (IC), three bins for input/output and an external OR component are required, and the external connection by converting into an IC hinders the reduction of the number of parts and the number of pins. Ta. Furthermore, it is susceptible to variations in OR components, changes in power supply voltage, changes in temperature, changes over time, and the like. Kirani,
If it is desired to switch the frequency characteristics to multiple modes using a mode command signal, there is a problem in that more external parts are required.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and provides an entire digital integration circuit in which all the components are digitalized and characteristics can be switched by a mode command signal.

Structure of the Invention The present invention comprises: variable frequency dividing means for switching the frequency division ratio of a clock pulse in response to a mode command signal; and gate means for prohibiting the output of the variable frequency dividing means when an input digital signal is a predetermined value. an up-down counter that uses at least one most significant bit of the input digital signal as an up-down signal input and that uses the output of the gate means as a clock input; It is a digital integration circuit that obtains signals, and all components are digitized. In addition, a second frequency dividing means is used in place of the gate means, and the output of the variable frequency dividing means is divided into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value. If this is used as a clock for an up/down counter, the performance as an integrating circuit can be further improved.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is an operating waveform diagram thereof, and FIG. 5 is a frequency characteristic curve showing integral characteristics.

In FIG. 3, 4 is a variable frequency dividing means, 5 is a gate means,
6 is an amplifier down counter, Dl is an input digital signal, D2 is an output digital signal, Sl is a clock pulse, S2 is a frequency division output, and S3 is a gate output.

The clock pulse S1 is frequency-divided by the variable frequency dividing means 4 at a predetermined frequency division ratio according to the mode command signal, and the frequency-divided output S2 is inputted to the gate means 5. In the gate means 5, the input digital signal is at a predetermined value.

When it matches (D1=D,), the frequency division output S2f is prohibited, and when the discrepancy CD+\Do), the frequency division output Szk gate output S
3 and is used as the clock input of the up/down counter 6. On the other hand, at least one most significant bit of the input digital signal D1 is input to the up/down counter 6 as an up/down signal, and the gate output S5 is counted up or down. The up/down counter 6 is configured to obtain an output digital signal D2.

To explain the operation of FIG. 3 in more detail with reference to FIG. 4, the operation of the up/down counter 6 is switched up or down (or down or up) depending on whether the input digital signal R is greater or less than a predetermined value Do. There is. That is, the relationship between Dl and Do of the output D2 is D,>'D.

(! or Dl<D.), up count (t2~t
3), D, -Do, the count stops (t1 to t2.
t3~t4゜t5~), D, < D. (Katsutaha Dl
〉Do), count down (~11.14~t5)
It is configured to allow

Here, to detect whether D,>Do or Dl<Do, at least one most significant bit of the input digital signal may be used. That is, apart from the case where the input digital signal D1 is 6 bits and the predetermined value Do is 100000 (this is the case where the most significant bit of ID is 1 and the lower bits are all 0), when the most significant bit of D1 is 1, Dl〉Do, 0
When Dl<Do, it is possible to easily detect whether the size is large or small. In this case, similar detection is possible even if the predetermined value is 011111.

The above example is a predetermined value. V of input digital signal D1
In this case, it is possible to set it to a value of %, ``!y4, and in this case, it is sufficient to use the 2-bits of d, the most ''-position as an up/down signal, and in this case, the detection Nodame logic circuit (decoder) is required.

On the other hand, the gate 1/means 5 decodes the input digital signal D1, obtains a forbidden signal when Dl-Do, and outputs the frequency-divided signal S.
2 gate output is prohibited.

Here, the time constant T in equation (1) can be expressed as 2.18k"""""""""""""' (2) However, fck ni 1, up/down counter 6 This clock frequency f.k is the frequency of the frequency-divided output S2 obtained by dividing the frequency of the clock pulse S1 by the variable frequency dividing means 4 according to the mode command change, and the frequency is equal to fl.f2.k. By dividing the frequency so that f, it is possible to switch the frequency characteristics of the integrating circuit as shown in FIG. 5, which is the object of the present invention.

Next, FIG. 6 is a block diagram showing a second embodiment of the present invention, where 7 is a first frequency dividing means, 8 is a second frequency dividing means, 9 is an up/down signal, and Do is A predetermined value, Dl is an input digital signal, D2 is an output digital signal, S4 is a clock pulse, S5 is a first frequency-divided output, and S6 is a second frequency-divided output.

The first frequency dividing means 7 corresponds to the variable frequency dividing means 4 shown in FIG. 3, and receives the clock pulse S4 and the mote command signal as input, and serves for switching the frequency characteristics as described above. The second frequency dividing means 8 receives the frequency divided output S5 of the first frequency dividing means 7, divides the frequency into a frequency proportional to the absolute value of the difference between the input digital signal D1 and the predetermined value Do, and outputs the frequency divided output S6. This is used as the clock input for the up/down counter 9. This allows up-counting and down-counting in proportion to the human digital signal D1 (proportional to lDj-DO'l). This is a digital implementation of the conventional example shown in FIG. 1 in which the feedback capacitor is charged and discharged in proportion to the input potential difference. Here, the frequency f of equation (2). k is the lowest frequency of the second divided output S6, that is, D
This is the frequency when the absolute value of the difference between l and Do is 1 (lD+Dol"1).Then, the output digital signal D2 is used as the output of the up/down counter 9, as in the first embodiment (Fig. 3). 1 Furthermore, the first
The up/down counter 6.9 of the second embodiment decodes the counting output D2 and inputs it when D2 is the maximum value and the minimum value.

A function is added to prohibit the input of S6 and to disable the clock input with the next down command when the maximum value is detected, and with the Lth up command when the minimum value is detected. Overflow and underflow of the up/down counter 6.9 can be prevented.

However, if a plurality of necessary clock pulses are available, it is not necessary to use a clock selection means using a mode command signal instead of the variable frequency division means 4 and the first frequency division means 7. 'Effects of the invention: As is clear from the above explanation, all the constituent elements can be digitalized and the frequency characteristics of the integrating circuit can be switched according to the mode command signal, which is suitable for LC implementation, and its practical effects are is thick.

[Brief explanation of the drawing]

Fig. 1 is an electrical connection diagram showing the conventional configuration of an analog integrating circuit, Fig. 2 is its operating waveform diagram, Fig. 3 is a block diagram of an embodiment of the digital integrating circuit of the present invention, and Fig. 4 is FIG. 5 is a diagram of its operating waveforms, FIG. 5 is a frequency characteristic curve diagram thereof, and FIG. 6 is a block diagram of another embodiment of the present invention. 4-...Variable frequency dividing means, 6 Gate means, 6°9...
up/down counter, 7 first frequency dividing means, 8- second
Frequency division means. Name of agent: Patent attorney Toshi Isamu Nakao and 1 other person 1st
Figure 3, Figure 2 Figure 4 River θ

Claims (2)

[Claims] (1) Variable frequency dividing means for switching the frequency division ratio of the clock pulse according to a mode command signal, gate means for prohibiting the output of the variable frequency dividing means when the input digital signal is a predetermined value, and An up/down counter is provided with at least one upper bit as an amplifier down signal input and the output of the gate means as a clock input, and the up/down counter outputs an output digital signal corresponding to the lower command signal. A digital integrating circuit characterized by (). (2) A first frequency dividing means that switches the frequency division ratio of the clock pulse according to a mode command signal, and divides the output of the first frequency dividing means into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value. and an up/down counter that uses at least one most significant bit of the input digital signal as an amplifier down signal input and an output of the second frequency divider as a clock input, A digital integrating circuit characterized by obtaining an output digital signal corresponding to a down counter or υ mode command signal.