JPS60223226A - Camera - Google Patents

Abstract

PURPOSE:To increase the A/D conversion speed by stopping the charged electric charge of a capacitor with the reference voltage and starting a conversion action. CONSTITUTION:A switching transistor Q1 is turned on with application of a charging/discharging pulse phid. Then a capacitor C starts discharging. When the inter-terminal voltage VD of the capacitor C is reduced less than the input voltage Vin, the output of a voltage comparator A1 is set at 1. The output of a comparator A2 is set O when the voltage VD is reduced less than the reference voltage Vref. A clock pulse emerges at the output Vout while the terminal voltage of the capacitor C is kept at a level between 1 and 0. The digital value of the input voltage is calculated by measuring the period of the clock pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a camera using an AD (analog-digital) conversion circuit (particularly a voltage one-time conversion type AD conversion circuit).

A circuit as shown in FIG. 5 is generally known as a one-time voltage conversion type A-D conversion circuit.

As shown in the figure, one voltage comparator A has positive and negative input terminals. A constant current source circuit I is connected between the power supply Vcc terminal and the ground potential terminal. and a charging/discharging circuit consisting of a switching transistor Q0 connected in series with a capacitor Co and a switching transistor Q0 connected in parallel to the capacitor Co, and an analog input voltage Vin is applied to the positive input terminal of the voltage comparator, and a negative input Apply the output voltage of the above charging/discharging circuit to the terminal 1,
Switching transistor Q of the above charge/discharge circuit. The voltage converter A is driven by clock pulses φd arriving at regular intervals. ■ Output of. The inverted output m obtained by inverting the charge/discharge clock pulse voltage by an inverter circuit and the successively arriving clock pulses φ are applied to the input of the AND logic circuit L6, and this AN
The output Vout of the D logic circuit is taken out as a converted output.

An outline of the operation of this circuit is as follows.

First, the photodischarge clock pulse φd reaches a high level 'H' (
When the switching transistor Q becomes “1” level),
is turned on, which causes capacitor C to turn on.

The charging charge is this transistor Q. is discharged through. If the capacitance of the capacitor Co is made small, this discharge will occur relatively quickly, so that the voltage between the terminals of the capacitor Co will be OV. Since this voltage becomes lower than the input voltage Vin, its output Vo becomes "H" level. Next, the charging/discharging clock pulse φd immediately goes to L'' (“
When the voltage reaches the "H" level, the inverted output Tm becomes "H" level.

This is the switching transistor Q. is turned off, the discharge path of the capacitor Co is cut off, and the capacitor Co is charged by the current from the constant current source I0 so that the voltage across the capacitor Co gradually increases. If the "L" level period of φd is Td, then the maximum charging voltage V wax of the capacitor Co is. During this period when φd is at “°L” level,
Capacitor C.

While the charging voltage of A is lower than the input voltage Vin, the voltage comparator A
. ■ Output voltage. becomes “H” level, therefore, AN
The waveform of the successively arriving clock pulses φ is output as is at the output VouL of the D logic circuit L6. Then, when the charging voltage exceeds the input voltage Vin, the voltage comparator A. Since the input state of changes, its output V.

is inverted and becomes "L" level. Therefore, the date of the AND logic circuit L6 is closed, and the output Vout becomes ``Ll level. Therefore, by measuring the time t1 at which the clock pulse appears on the output Vout, or by measuring the number of clock pulses by using a counter circuit, etc. By counting, the value of the analog input voltage can be known.

However, the above conversion circuit has the following drawbacks.

(1) As mentioned above, in a general integral type A-D converter circuit as shown in Figure 5, the charge accumulated in the capacitor CO is discharged at a zero potential, and then the charge is discharged until the input voltage is reached. Since this circuit is operated based on the time of , it takes time for charging and discharging, which slows down the conversion speed.

(2) Since the transistor Q0 repeats on-off operations many times, a phenomenon occurs in which a residual voltage is generated, and as a result, the terminals of the capacitor may not be completely at the ground level during discharge, i.e. ,
The ground level will be different for each operation, so there is no doubt that the conversion is accurate.

(3) There are manufacturing variations in the design value of the on-resistance of the transistor Q0, and as a result, the discharge time constant differs from product to product, resulting in poor reproducibility in mass production, making it impossible to improve yield.

Therefore, an object of the present invention is to improve the accuracy of a camera using an A-D conversion circuit.

The present invention will be specifically described below using examples and with reference to the drawings.

FIG. 1 (A> is a circuit diagram showing an example of an A-D conversion circuit used in the camera of the present invention, and as shown in the figure, two
The first one has two input terminals (+ and -) and one output terminal.
and second voltage comparators A, A2, and a constant current source circuit (2) between the power supply voltage Vcc terminal and the ground potential terminal. 1 and capacitor C
o are connected in series, and this capacitor Co and constant current source circuit I
. , and a charging/discharging circuit 1 comprising a pn switching transistor Q connected between the connection point and the ground potential terminal, and the positive (+) input terminal of the first voltage comparator A1 has an analog An input voltage Vin is applied, the negative (-) input terminal is connected to the output point of the charging/discharging circuit 1, and the positive (+) input terminal of the second voltage comparator A2 is connected to the output of the charging/discharging circuit 1. A voltage is applied to the negative (-) input terminal, which is set to a reference voltage Vaef that is lower than the lowest value of the input analog voltage Vin as a guideline. Note that this input analog voltage Vin depends on the application, for example, in the case of an exposure display system for a camera IC as described later, it is impossible for the voltage based on the surrounding brightness to be completely zero potential, so It is sufficient to set the voltage corresponding to the time, etc. as the minimum value, and set a voltage slightly lower than this as the reference voltage. The base of the switching transistor Q1 is connected to the output of a NAND logic circuit-1 logic circuit L1 which uses the pulse φd that arrives after a certain period of time and the output V2 of the second voltage comparator A2 as two inputs. (2) Applying the charging/discharging signal v4 via the impark circuit L2 that inverts the voltage comparator A,
, A2's output V 11v2, the output φd of the inverter circuit L5 that inverts the pulse φd, and the clock pulse φ.

An AND logic circuit powered by four people is provided, and its output is Vout.

The circuit operation with this circuit configuration is as follows. FIG. 1(B) is a voltage waveform diagram for explaining the operation of the above circuit. This will be explained below using FIGS. 1(A) and 1(B). In the following operation description, the arrival interval of charging/discharging pulse φd,
Clock pulse φ. Figure 1 (B) shows the relationship between the period of arrival of
It shall be set as follows.

First, when the power supply voltage Vcc is applied, the capacitor Co of the charging/discharging circuit 1 in the above circuit is connected to the constant current source circuit I.
. , and the voltage Vn at its terminal is at the Vcc level (the dashed line in FIG. 1(B) shows the voltage waveform of Vo). If the analog input voltage is at the level of the waveform shown by the solid line at Vn in FIG. ) input terminal voltage (Vo) is higher than the positive (+) input terminal voltage (Vi port), so it is at a low level (“0゛l), and the reference voltage If VRef satisfies the above conditions and is set to have the waveform of the number of points shown at Vn in FIG. 1(B), the output V2 of the second voltage comparator A2 becomes a positive (+) input. If the terminal voltage (V o ) is negative (
-) is higher than the voltage (VRef) at the input terminal, so it becomes a high level (“1”). A at this time
The output Vout of the ND logic circuit is the voltage comparator A.
Since the output ■1 of , is a low level (“0”), even if the other inputs are at a low level, the level will remain low (0”).
Output.

Next, when the charging/discharging pulse φd is applied (becomes "1" level) at the timing shown in FIG. 1
``level'', the NAND logic circuit-1 and its output (2) become 0'' level. This is the inverter L
2's output v4 becomes "1" level and turns on the switching transistor Q1. With this Q turned on, the capacitor Co starts discharging, and therefore the capacitor Co
The inter-terminal voltage Vn decreases toward the ground (GND) level.

The state of each of the above output points changes depending on the stage during which the voltage Vo between the terminals of the capacitor Co is decreasing. That is, the voltage Vo between the terminals of the capacitor Co decreases,
When the input voltage becomes lower than Vin, the voltage comparator A of mi
As the positive (+) input voltage (Via) increases, the output of , is inverted and becomes a high level (“1”), and the voltage VD between the terminals of the capacitor Co becomes lower than the reference voltage VRef. , the second voltage comparator A2 becomes lower level (“
O゛).

When the output v2 of the voltage comparator A2 of j12 becomes 0'' level, the output v5 of the NAND logic circuit w!rLt
is inverted to the 111 I+ level, so the output V of the inverter is also inverted to the 0'' level.

Therefore, at this timing, the switching transistor Q is turned off, and the capacitor Co starts charging again.

This charging increases the terminal voltage V of the capacitor co.

If we pay attention to the input state of the AND logic circuit L4 at the timing when the output voltage v2 of the second voltage comparator A2 is inverted to the "1" level, we can see that the first voltage comparator A , the output V.

becomes "1" level, and at this stage the charging/discharging pulse φd
Since is at the “0” level, the inverted signal f
6dli"l" level, the output Vout
clock pulse φ. comes out as is.

Furthermore, when the terminal voltage VD exceeds the potential of the input voltage Vin due to charging of the capacitor Co, the first voltage comparator AI
As the negative (-) input voltage (VD) increases, the output of Vout is inverted to a low level (“O゛). Therefore, the output Vout of the above AND circuit becomes a low level (“0”).
) is the output.

From the above, it is possible to calculate the digital value of the input voltage by measuring the period t1 of the clock pulse appearing in the output Vout or by measuring the number of arriving clock pulses with a counter circuit or the like. can.

In addition, when the input voltage Vin is relatively low, a clock pulse appears at the output Vout after going through the same operation as described above (for example, during period t2 in the figure), so the clock pulse at this time Digital conversion is performed by measuring the time or number of arrivals.

A-to-D conversion will be performed in the same manner thereafter.

According to the present invention described above, various effects as shown below can be obtained.

(1) Rather than completely discharging the charge in the capacitor Go of the charging/discharging circuit 1 to zero potential, it is stopped just below the reference voltage V*ef and then charged, so that this charging voltage exceeds the reference voltage VRef. Since the conversion operation is started at a certain time, the conversion speed is faster than in the conventional case where the conversion operation is started after the electric potential has been completely discharged to zero.

(2) Due to the frequent on and off operations of transistor Q1, a residual voltage is generated there.
Although there may be a problem that the capacitor Co is not completely discharged, the above problem can be ignored because the present invention does not require an operation to completely discharge the capacitor Co. Therefore, conversion accuracy is improved.

(3) Even if the on-resistance of the transistor Q varies somewhat from the design value, in the present invention, the capacitor C(1
Since the circuit is not completely discharged to zero potential, but is stopped near the reference voltage VRef, the above-mentioned variations do not have a large influence on the discharge time constant like in conventional circuits. However, the yield can be greatly improved.

FIG. 2 shows the voltage comparator A1. FIG. 2 is a circuit diagram showing an example of a specific circuit of A2.

As shown in the figure, the above circuit includes an emitter-coupled 1P transistor Q2. Input int to the base of Q, i-mouth 2
is applied, the common emitter is connected to the power supply Vcc terminal via the constant current source circuit I0, and the collector is connected to the constant current source circuit I, respectively. 39 Connect to the ground (GND) terminal via A4, take out the output Vout from the output point of the output circuit in which the load resistor RL and the npn) transistor Q4 are connected in series, and the base of the transistor Q4 is connected to the collector of the emitter-coupled transistor Q. It becomes connected to. By using a voltage comparator with such a configuration, the degree of integration can be improved.

In addition, the voltage comparator may have any specific configuration.

FIG. 3 shows an A-D converter circuit for a camera according to the present invention.
FIG. 3 is a block diagram when used in the exposure display system of C.

As shown in the figure, the illuminance of the subject is detected by a photoelectric converter 2. On the other hand, the set aperture value and shunter speed value are converted into voltages, and then logarithmically converted by a logarithmic compressor to obtain an aperture voltage F and a speed voltage S. Both of these three are input to the arithmetic circuit 8 to obtain an output responsive to each voltage value.

Then, this output is amplified by the amplifier 4, this amplified output is converted into a digital value by the A-D converter B5 of the present invention, this digital value is measured by the counter circuit 6, and this measured value is input to the decoder 7. This decoder 7
By lighting up the 7 photodiodes 8 at the positions to be displayed, an appropriate exposure value is obtained.

If the above-mentioned A-D converter 5 is used in such a system, accurate exposure display can be performed.

FIG. 4 shows another embodiment of the A/D conversion circuit of the present invention. This circuit is characterized by a constant current circuit I forming a charging/discharging circuit 1. is composed of transistors Q and .about.Q9, whose operation is controlled by a switching transistor Q1.degree., and further includes a logic circuit, .about.L I O.

FIG. 4(B) shows the operating waveforms of the circuit. According to this embodiment, the terminal voltage of the capacitor Co is the reference voltage VRe.
After reaching f, charging is stopped until the next clock pulse arrives, and the capacitor terminal voltage is held at VRef. This allows the time required to charge from VRef to an unknown input voltage to be accurately digitalized. This can reduce conversion errors compared to the case where the timing at which the terminal voltage of the capacitor Co reaches Vaef in the embodiment shown in FIG. 1 is not synchronized with the clock pulse.

Next, referring to the waveform diagram in FIG. 4(B),
The operation of the circuit will be explained in detail.

(1) Time t. Previously; clock signal φ. The time at which the control pulse φd obtained by dividing the frequency of φd changes from low to high. Previously, regarding the terminal voltage Vo of the capacitor, the input voltage Vin, and the reference voltage VRef, Vo>Vin
, V o > V Ref holds true.

Therefore, the output V of the first voltage comparator A is low level, the output V of the second voltage comparator A2 is high level, the output V of the NAND circuit L1 is high level, and the inverter circuit L
2's output V4 becomes low level, and the discharging transistor Q0 is turned off. On the other hand, the output V of the inverter circuit L5 connected to the output V of the second voltage comparator A2 becomes low level, and the clock input terminal (φ) receives the clock signal φ. is applied, and the output 5 of the inverter circuit L5 is applied to its data input terminal (D>).
The output v6 of the tube (hereinafter referred to as F/F) L6 is low level, the output ■8 of the NAND circuit L7 is high level, the output ■ of the inverter circuit is low level, and the control transistor Q1° is turned off. Become. Therefore, constant current source circuit I
0, a constant current flows from the reference voltage V+zef through the resistor to the diode-connected transistors Q, Qs, so a charging current flows to the capacitor Co through the emitter-collector path of the charging transistor Q5, and the terminal voltage VD
will rise.

(2) Time t. ; At time t0 when the control pulse φd changes from low to high, ■ changes from high to low, and ■
, changes from low to high. Therefore, the discharging transistor Q is turned on, and the terminal voltage Vo of the capacitor Co
decreases rapidly.

(3) Time tl: Time 1 when Vo becomes equal to or less than Vin. , Vl changes from low to high, but other voltages v
2 to v8 retain their respective states before time t1.

(4) Time tz; Voka VRef or less and null time h1m
Then, Vl changes from high to low, V3 changes from low to high, and V4 force f changes from high to low, so
Discharge transistor Q. is off. On the other hand, ■2 becomes low, so v5 becomes high. Luka, D type F/F
The output V6 of Ls maintains the previous low level. ■7
8 maintains a high level, and 8 maintains a low level, so a charging current flows to the capacitor Go via the emitter-collector path of the charging transistor Q5, and the terminal voltage V
D starts to rise.

(5) At time t, when the control pulse φd changes from high to low, each of the voltages V1 to V8 maintains its previous state.

(6) Time t4; clock signal φ. At time t, when the clock signal φ0 changes from high to low, the D-type F/F Ls updates the data of the output signal. . However, since v7 is held at a high level and V8 is held at a low level, charging of the capacitor Co continues.

(7) Time t5; Time tsl when Vo power is equal to or higher than VRef
As a result, v2 changes from low to high, but since 2 and 2 are held at high level and 2 and low level, the discharging transistor Q0 is off.

On the other hand, at this time L5, ■ changes from high to low, but since the output v6 of the D-type F/F L6 maintains the previous high level, V7 becomes low and v6 becomes high, and the control transistor Q ,. is on, and charging transistor Q5 is off.

Therefore, at this time t5, the discharging transistor Q0 and the charging transistor Q5 are simultaneously turned off, so that the terminal voltage Vo of the capacitor CO is held at a voltage slightly higher than the reference voltage Vtrer.

(8) Time t6; clock signal φ. Time t when changes from high to low. In response to the low level V5, the output Vl of the D type F/F'L becomes low level and becomes %
V? is at high level, ■8 is at low level, control transistor QIG is turned off, and charging transistor Q5 is turned off.
is turned on. On the other hand, due to the low level ■4, the discharging transistor Q0 is turned off, the terminal voltage Vo of the capacitor Co starts to rise again, and the AND circuit L
Clock signal φ from the output of 4. A counting output pulse Vout synchronized with is obtained.

(9) Time t: Time t when Vo becomes equal to or greater than Vin
, smell, ■ changes from high to low, and the count output pulse Vout of the AND circuit also becomes low level.

On the other hand, the other voltages v2 to v8 maintain their respective previous states.

(10) Time La: At time t8 when the control pulse φd changes from low to high, ■3 changes from high to low, ■
, changes from low to high, the discharging transistor Q0 is turned on, and the terminal voltage VD of the capacitor Co rapidly decreases, repeating the operation from time to t7 described above.

As is clear from the above operation description, the clock signal φ is activated after the terminal voltage Vo of the capacitor Co reaches the reference voltage V Ref. Before the voltage changes from high to low, the photodischarge is interrupted and the terminal voltage VD is held at a value close to the reference voltage VRef, and the clock signal φ. At time t6 when the voltage changes from high to low, charging to this hold value or the input voltage Vin starts, and at the same time, the clock signal φ. , the AD conversion error can be made small.

[Brief explanation of the drawing]

FIG. 1(A) and FIG. 4(A) are circuit diagrams showing an example of an A-D converter used in the camera of the present invention.
Figures (B) and 4 (B) are voltage waveform diagrams for explaining the operation, Figure MS2 is a circuit diagram showing an example of a voltage comparator, and Figure 3 is a circuit diagram showing an example of the application of the present invention. FIG. 5 is a circuit diagram showing an example of a conventional A-D converter. 1... Charge/discharge circuit, 2... Photoelectric converter, 3... Logarithmic compressor, 4... Amplifier, 5... A-D converter, 6... Count circuit, 7... Decoder, 8... 7 Otodiode, Q
,,Q,-Q,. ...Transistor, Co...Capacitor, ■. ll0I-In14... constant current source circuit, L1~
Llo...logic circuit, RL...load resistance, A,,A,,
A2...Voltage comparator. Figure 1 (A) 'j,, 1 Vcc □6NO Figure 2 Figure 3 Figure 4 (A) Figure 4 (B) Figure 5 -1

Claims (1)

[Claims] 1. A camera that produces the illuminance, aperture value, and shutter speed value of the subject and converts them into digital values by an A-D converter circuit that outputs the calculated values, and the A-D converter circuit has at least two input terminals and It consists of first and second voltage comparators each having one output terminal, a charging/discharging capacitor, a charging means connected to the charging/discharging capacitor, and a discharging switching means connected to the charging/discharging capacitor. a charging/discharging circuit, wherein an input voltage is applied to one input terminal of the first voltage comparator, a terminal voltage of the charging/discharging capacitor is applied to the other input terminal, and a charging/discharging circuit is provided. This is an A-D converter circuit in which the terminal voltage of the charging/discharging capacitor is applied to one input terminal of the device, and a reference voltage set according to the relationship 1 with the above input voltage is applied to the other input terminal. Then, a clock signal is applied to the lock input terminal, and the data input terminal is applied to the second lock input terminal.
further comprising a delay type 7-lip 70.yp for controlling the charging means in response to a signal at the output terminal of the voltage comparator; When the voltage becomes lower than the reference voltage, the output of the second voltage comparator causes the discharging switching means to become non-conducting, and the delay type 7
The output of the flip 70 knob increases the terminal voltage by controlling the charging means, and when the terminal voltage reaches the reference voltage due to this increase, the output of the delay type flip 70 triggers the charging operation of the charging means. When the level of the clock signal changes to a predetermined state, the output of the delay type 7-lip 70 is controlled by controlling the charging means. The terminal voltage is raised again, and measurement of the clock signal is started based on the outputs of the first and second voltage comparators and the output of the delay type flip 70, and the terminal voltage is determined to be the value of the input voltage. When the above occurs, the measurement of the click signal is stopped based on the outputs of the first and second voltage comparators and the output of the delayed 7-lip 70-tub. .