JPS62614B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a camera using an AD (analog-digital) conversion circuit (particularly a voltage-time conversion type AD conversion circuit).

A circuit as shown in FIG. 5 is generally known as a voltage-time conversion type AD conversion circuit.

As shown in the figure, a constant current source circuit I0 and a capacitor Co are connected in series between one voltage comparator _A0 having positive and negative input terminals, a power supply Vcc terminal and a ground potential terminal, and a constant current source circuit _I0 and a capacitor Co are connected in series. The analog input voltage Vin is applied to _the positive input terminal of the voltage comparator, and the output voltage of the charge/discharge circuit is applied to the negative input terminal of the voltage comparator. is applied, and the switching transistor Q ₀ of the charge/discharge circuit is driven by clock pulses φd arriving at regular intervals, and the output V ₀ of the voltage converter A ₀ is
and an inverter circuit for charging and discharging clock pulse voltage.
The inverted output inverted by _L5 and the successively arriving clock pulse φ are connected to an AND logic circuit.
applied to the input of L ₆ and the output of this AND logic circuit
This is to extract Vout as a conversion output.

An outline of the operation of this circuit is as follows.

First, when the charging/discharging clock pulse φd becomes a high level "H"("1" level), the switching transistor _Q0 is turned on, whereby the charge in the capacitor _C0 is discharged via this transistor _Q0 . If the capacitance of the capacitor Co is made small, this discharge will occur relatively quickly, so the voltage between the terminals of the capacitor Co will be 0V. Since this voltage is lower than the input voltage Vin, its output
_V0 becomes "H" level. Next, the charging/discharging clock pulse φd immediately goes to "L" level ("0" level), and its inverted output goes to "H" level.

At this time, the switching transistor Q ₀ is turned off and the discharge path of the capacitor Co is cut off, and the capacitor Co is charged by the current from the constant current source I ₀ so that the voltage across it gradually increases. Ru. If the “L” level period of φd is Td, the maximum charging voltage Vmax of capacitor Co is I ₀ Td/C
It becomes o. During this period when φd is at the “L” level, the maximum charging voltage Vmax of the capacitor Co becomes I ₀ Td/Co. During the period when φd is at “L” level, the voltage comparator A ₀
The output voltage V ₀ becomes “H” level, and therefore,
The waveform of the successively arriving clock pulses φ is output as is at the output Vout of the AND logic circuit _L6 . When the charging voltage exceeds the input voltage Vin, the input state of the voltage comparator A ₀ changes, so its output V ₀ is inverted and becomes the "L" level. Therefore, the gate of the AND logic circuit _L6 is closed, and the output Vout becomes "L" level. Therefore, the value of the analog input voltage can be determined by measuring the time t during which a clock pulse appears on the output Vout, or by counting the number of clock pulses using a counter circuit or the like.

However, the above conversion circuit has the following drawbacks.

(1) As mentioned above, in a general integral type A-D converter circuit as shown in Figure 5, the charge accumulated in the capacitor Co is discharged to zero potential, and then the charge is discharged until the input voltage is reached. Since this circuit is operated based on time,
It takes time to charge and discharge, which slows down the conversion speed.

(2) Since the transistor Q ₀ repeats on-off operations many times, a phenomenon occurs in which a residual voltage is generated, and as a result, the terminals of the capacitor may not be completely at the ground level during discharge. That is, the ground level differs for each operation, and therefore accurate conversion cannot be performed.

(3) There are manufacturing variations in the design value of the on-resistance of the transistor Q ₀ , and as a result, the discharge time constant differs from product to product, resulting in poor reproducibility when mass-produced, making it impossible to improve yield.

Therefore, the object of the present invention is to
The objective is to improve the accuracy of cameras using D conversion circuits.

The present invention will be specifically described below using examples and with reference to the drawings.

FIG. 1A shows A-D used in the camera of the present invention.
It is a circuit diagram showing an example of a conversion circuit, and as shown in the figure, first and second voltage comparators A ₁ and A ₂ have two input terminals (+ and -) and one output terminal.
A constant current source circuit I ₀₁ and a capacitor Co are connected in series between the power supply voltage Vcc terminal and the ground potential terminal, and an npn switching transistor is connected between the connection point between the capacitor Co and the constant current source circuit I ₀₁ and the ground potential terminal. The analog input voltage Vin is applied to the positive (+) input terminal of the first voltage comparator _A1 , and the negative (- ₎ input terminal of the first voltage comparator A1 is is connected to the output point of the charge/discharge circuit 1, the positive (+) input terminal of the second voltage comparator _A2 is connected to the output point of the charge/discharge circuit 1, and the negative (-) input terminal of the second voltage comparator A2 is connected to the output point of the charge/discharge circuit 1. applies a voltage with the lowest value of the input analog voltage Vin as a guideline and a voltage lower than that as the reference voltage V _Ref . Note that this input analog voltage Vin
Depending on the application, for example, in the case of an exposure display system for a camera IC as described later, it is impossible for the voltage based on the surrounding brightness to be completely zero potential, so it is necessary to correspond to rainy weather at that time. The voltage may be set as the minimum value, and a voltage slightly lower than this may be set as the reference voltage. The base of the switching transistor Q ₁ is connected to a NAND logic circuit _{L 1} which has two inputs, the pulse φd that arrives after a certain period of time, and the output V ₂ of the second voltage comparator A ₂ , and this logic circuit. Output of circuit L ₁ V ₅
A charge/discharge signal V ₄ is applied via an inverter circuit L ₂ that inverts the pulse φd, and outputs V ₁ and V ₂ of the voltage comparators A ₁ and A ₂ and an output φd of an inverter circuit L ₅ that inverts the pulse φd. AND logic circuit _L4 having four inputs of clock pulse _φ0 is provided, and its output is set as Vout.

The circuit operation with this circuit configuration is as follows. FIG. 1B is a voltage waveform diagram for explaining the operation of the above circuit. This will be explained below using FIGS. 1A and 1B. In the following operation description, the charging/discharging pulse φd
It is assumed that the relationship between the arrival interval of clock pulse φ0 and the arrival period of clock pulse _φ0 is set as shown in FIG. 1B.

First, when the power supply voltage Vcc is applied, the capacitor Co of the charging/discharging circuit 1 in the above circuit is charged with the power supply voltage Vcc via the constant current source circuit _I01 .
The voltage V _D at that terminal is at the Vcc level (the dashed line in FIG. 1B shows the voltage waveform of V _D ).
If the analog input voltage is at the level of the waveform shown by the solid line at V _D in Figure 1B, the output potential of the first voltage comparator _A1 at this time is
V ₁ is the negative (-) input terminal voltage V _D is positive (+)
Since it is higher than the voltage _Vin at the input terminal _of If the waveform is set to have the number of points shown above, the output V ₂ of the second voltage comparator A ₂ will be the voltage V _D at the positive (+) input terminal and the voltage V _Ref at the negative (-) input terminal. Since it is higher than , it becomes a high level (“1”). At this time, the output Vout of the AND logic circuit L ₄ is the output V ₁ of the voltage comparator A ₁ above.
Since is at a low level (“0”), it outputs a low level (“0”) no matter what level the other inputs are.

Next, when the charging/discharging pulse φd is applied (becomes "1" level) at the timing shown in FIG. 1B, the " ₁ " level of this φd and the output "1'' level opens the NAND logic circuit _L1 , and its output _V5 becomes the "0" level. As a result, the output _V4 of the inverter _L2 becomes "1" level, and the switching transistor
Turn on _Q1 . This Q ₁ on causes the capacitor Co to start discharging and thus the capacitor Co
The terminal-to-terminal voltage V _D decreases toward the ground (GND) level.

The state of each of the above output points changes depending on the stage during which the voltage V _D between the terminals of the capacitor Co is decreasing. That is, when the voltage V _D between the terminals of the capacitor Co decreases and becomes lower than the input voltage Vin, the output of the first voltage comparator _A1 becomes inverted as the positive (+) input voltage Vin increases. When the voltage V _D between the terminals of the capacitor Co becomes lower than the reference voltage V _Ref , the second voltage comparator A ₂ outputs its negative (-) input voltage V _Ref.
The higher the value becomes, the lower the level (“0”) becomes.

In the stage where the output V ₂ of this second voltage comparator A ₂ becomes “0” level, the output of the NAND logic circuit L ₁
Since V ₅ will be inverted to “1” level,
The output _V4 of the inverter is also inverted to "0" level. Therefore, at this timing, the switching transistor _Q1 is turned off, and the capacitor Co starts charging again.

Due to this charging, the terminal voltage of the capacitor Co is V _D
If we pay attention to the input state of the AND logic circuit L ₄ at the timing when the output voltage V 2 of the second voltage _{comparator A 2} is inverted to the “1” level when the output voltage V 2 becomes higher than the reference voltage V Ref, the first voltage comparison Output V ₁ of device A ₁
is at the "1" level, and since the charging/discharging pulse φd is at the "0" level at this stage, its inverted signal is at the "1" level, so the clock pulse _φ0 is output as is at the output Vout. .

Furthermore, when the terminal voltage V _D exceeds the potential of the input voltage Vin due to charging of the capacitor Co, the output of the first voltage comparator A ₁ becomes low due to the negative (-) input voltage V _D becoming high. Inverted to level (“0”). Therefore, the output Vout of the above AND circuit _L4
is a low level (“0”) output.

From the above, it is possible to calculate the digital value of the input voltage by measuring the period _t1 of the clock pulse appearing in the output Vout or by measuring the number of arriving clock pulses with a counter circuit, etc. .

Furthermore, when the input voltage Vin is relatively low, a clock pulse appears at the output Vout after the same operation as above (for example, during period _t2 in the figure).
Therefore, digital conversion can be performed by measuring the arrival time or number of clock pulses at this time.

A-to-D conversion will be performed in the same manner thereafter.

According to the present invention described below, various effects as shown below can be obtained.

(1) Rather than completely discharging the charge in the capacitor Co of the charging/discharging circuit 1 to zero potential, it is stopped just below the reference voltage V _Ref and then charged until the charging voltage exceeds the reference voltage V _Ref . Since the conversion operation is started at a certain time, the conversion speed is faster than in the conventional case where the conversion operation is started after the electric potential has been completely discharged to zero.

(2) Frequently turning on and off the transistor _Q1 may cause a residual voltage to be generated there, causing the problem that the capacitor Co may not be completely discharged. However, in the present invention, the capacitor Co is completely discharged. Since no discharge operation is required, the above problem can be ignored. Therefore, conversion accuracy is improved.

(3) Even if the on-resistance of transistor _Q1 varies somewhat from the design value, in the present invention, the capacitor Co is not completely discharged to zero potential, but is stopped near the reference voltage V _Ref . Therefore, since the above-mentioned variations do not have a large influence on the discharge time constant as in the conventional circuit, the yield can be greatly improved even when mass-produced.

FIG. 2 is a circuit diagram showing an example of a specific circuit of voltage comparators A ₁ and A ₂ in the A-D conversion circuit used in the camera of the present invention.

The above circuit is an emitter-coupled type as shown in the figure.
Input in ₁ , in ₂ to the base of npn transistors Q ₂ , Q ₃
is applied, the common emitter is connected to the power supply Vcc terminal via the constant current source circuit _I0 , the collector is connected to the ground (GND) terminal via the constant current source circuits _I03 and _I04 , and the load resistor R The output Vout is taken out from the output point of an output circuit in which _{an L} and an npn transistor _Q4 are connected in series, and the base of the transistor _Q4 is connected to the collector of the emitter-coupled transistor _Q5 . By using a voltage comparator with such a configuration, the degree of integration can be improved.

In addition, the voltage comparator may have any specific configuration.

FIG. 3 is a block diagram when the A-D conversion circuit according to the present invention is used in an exposure display system of a camera IC.

As shown in the figure, the illuminance of the subject is detected by a photoelectric converter 2. On the other hand, the set aperture value and shutter speed value are converted into voltages, and then logarithmically converted by a logarithmic compressor to obtain an aperture voltage F and a speed voltage S. Both of these three are input to the arithmetic circuit 8 to obtain an output responsive to each voltage value. Then, this output is amplified by an amplifier 4,
This amplified output is converted into a digital value by the A-D converter 5 of the present invention, this digital value is measured by the counter circuit 6, and this measured value is input to the decoder 7. By lighting up the photodiode 8 at the position to be displayed, an appropriate exposure value is obtained.

If the above A-D converter 5 is used in such a system, accurate exposure display can be achieved.

FIG. 4 shows another embodiment of the A/D conversion circuit of the present invention. The feature of this circuit is that the constant current circuit _I0 forming the charge/discharge circuit 1 is composed of transistors _Q5 to _Q9 , and its operation is performed by switching transistors.
_Q10 , and logic circuits _L5 to _L10 are added. Fourth
Figure B shows the operating waveforms of the circuit. According to this embodiment, the terminal voltage of the capacitor Co is the reference voltage V _R
After reaching _ef , charging is stopped until the next clock pulse arrives, and the capacitor terminal voltage is held at V _Ref . This allows the time required to charge from V _Ref to an unknown input voltage to be accurately digitized. This can reduce conversion errors compared to the case where the timing at which the terminal voltage of the capacitor Co reaches V _Ref in the embodiment shown in FIG. 1 is not synchronized with the clock pulse.

Next, referring to the waveform diagram in FIG. 4B,
The operation of the circuit will be explained in detail.

(1) Before time t ₀ : Before time t ₀ when the control pulse φd obtained by dividing the clock signal φ ₀ changes from low to high, the terminal voltage V _D of the capacitor, the input voltage Vin, and the reference voltage Regarding V _Ref , the relationships of V _D > Vin and V _D > V _Ref hold true.

Therefore, the output V ₁ of the first voltage comparator A ₁ is low level, the output V ₂ of the second voltage comparator A ₂ is high level, the output V ₃ of the NAND circuit L ₁ is high level, and the inverter circuit L The output V ₄ of ₂ becomes low level, and the discharge transistor Q ₀ is turned off. On the other hand, the output _V5 of the inverter circuit _L5 connected to the output V of the second voltage comparator _A2 becomes low level, the clock signal _φ0 is applied to its clock input terminal φ, and the inverter circuit L5 is connected to its data input terminal D. Delay type flip-flop to which output _V5 of circuit _L5 is applied (hereinafter referred to as D type F/F)
The output V ₆ of L ₆ is low level, the output V ₈ of NAND circuit L ₇ is high level, the output of inverter circuit L ₈
V ₈ goes low level and control transistor Q ₁₀
is off. Therefore, in the constant current source circuit _I0 , a constant current flows from the reference voltage V _Ref through the resistor to the diode-connected transistors _Q8 and _Q9 , so that a constant current flows to the capacitor Co through the emitter-collector path of the charging transistor _Q5 . A charging current flows and the terminal voltage V _D rises.

(2) Time t ₀ ; At time t ₀ when the control pulse φd changes from low to high, V ₃ changes from high to low, and V ₄ changes from low to high. Therefore,
The discharging transistor Q ₀ is turned on, and the terminal voltage V _D of the capacitor C ₀ drops rapidly.

(3) Time t ₁ ; At time t ₁ when V _D becomes less than Vin, V ₁ changes from low to high, but the other voltages V ₂ to _{V 8} maintain their respective states before time t ₁ . do.

(4) Time t ₂ ; At time t ₂ when V _D becomes less than V _Ref , V ₂ changes from high to low, V ₃ changes from low to high, and V ₄ changes from high to low. , the discharge transistor Q ₀ is turned off. On the other hand, as V ₂ becomes low, V ₅ becomes high, but the output V ₆ of the D-type F/F L ₆ maintains the previous low level. V ₇ holds high level and V ₈ holds low level, so
A charging current flows into the capacitor _C0 through the emitter-collector path of the charging transistor _Q5 , and the terminal voltage _VD starts to rise.

(5) Time t ₃ ; At time t ₃ when the control pulse φd changes from high to low, each of the voltages V ₁ to V ₈ maintains its previous state.

(6) Time t ₄ ; At time t ₄ when the clock signal φ ₀ changes from high to low, when the clock signal φ ₀ changes from high to low, the D-type F/F
Since _L6 updates the data of the output signal, its output _V6 changes to high level. However, since _V7 is held high and _V8 is held low, charging of capacitor Co continues.

(7) Time t ₅ ; At time t ₅ when V _D becomes equal to or higher than V _Ref , V ₂ changes from low to high, but V ₃ remains at high level and V ₄ remains at low level, so that no discharge occurs. transistor Q ₀ is off.

On the other hand, at time _t5 , _V5 changes from high to low, but the output _V6 of the D-type F/F _L6 maintains the previous high level, so _V7 becomes low and _V8 becomes high. Therefore, the control transistor _Q10 is turned on and the charging transistor _Q5 is turned off.

Therefore, at this time _t5 , the discharging transistor _Q0 and the charging transistor _Q5 are turned off simultaneously, so that the terminal voltage _VD of the capacitor Co is held at a voltage slightly higher than the reference voltage V _Ref .

(8) Time t ₆ ; At time t ₀ when the clock signal φ ₀ changes from high to low, the output V ₆ of the D-type F/F L ₆ becomes low level in response to the low level V ₅ , and V ₇ is at a high level, _V8 is at a low level, the control transistor _Q10 is turned off, and the charging transistor _Q5 is turned on. On the other hand, due to the low level of V ₄ , the discharging transistor Q ₀
turns off, the terminal voltage V _D of capacitor Co starts to rise again, and AND circuit L ₄
A counting output pulse Vout synchronized with the clock signal _φ0 is obtained from the output of the clock signal φ0.

(9) Time t ₇ ; At time t ₇ when V _D is higher than Vin, V ₁ changes from high to low and the AND circuit
The count output pulse Vout of _L4 also becomes low level. On the other hand, the other voltages _V2 to _V8 maintain their respective previous states.

(10) Time t ₈ ; At time t ₈ when the control pulse φd changes from low to high, V ₃ changes from high to low, V ₄ changes from low to high, and the discharge transistor Q ₀ turns on. Then, the terminal voltage V _D of the capacitor Co rapidly decreases, and the operation from time t ₁ to _{t 7} described above is repeated.

As is clear from the above operation description, after the terminal voltage V _D of the capacitor Co reaches the reference voltage V _Ref and before the next clock signal φ ₀ changes from high to low, charging and discharging are interrupted and the terminal voltage V _D is the reference voltage V _R
A is held at a value close to _ef , and at time _t6 when the clock signal _φ0 changes from high to low, charging to this hold value or to the input voltage Vin starts, and counting of the clock signal _φ0 starts. -D
Conversion errors can be made small.

[Brief explanation of the drawing]

1A and 4A are circuit diagrams showing an example of an A-D converter used in the camera of the present invention, and FIGS. 1B and 4B are voltage waveforms for explaining its operation. 2 is a circuit diagram showing an example of a voltage comparator, FIG. 3 is a block diagram showing an example of application of the present invention, and FIG. 5 is a circuit diagram showing an example of the application of the present invention. FIG. 2 is a circuit diagram showing an example. 1... Charge/discharge circuit, 2... Photoelectric converter, 3...
Logarithmic compressor, 4...Amplifier, 5...A-D converter, 6...Counter circuit, 7...Decoder, 8...
...Photodiode, Q ₀ , Q ₁ - Q ₁₀ ... Transistor, Co ... Capacitor, I ₀ , I ₀₁ - _{I 04} ... Constant current source circuit, L ₁ - L ₁₀ ... Logic circuit, R _L ... Load resistance, A ₀ , A ₁ , A ₂ ...voltage comparator.

Claims (1)

[Claims] 1. An arithmetic circuit that outputs appropriate exposure value information based on the input of subject illuminance information, aperture value information, and shutter speed information, and an arithmetic circuit that outputs appropriate exposure value information from the output of the input information, and The camera includes an A-D conversion circuit that converts into a digital value, wherein the A-D conversion circuit includes at least first and second voltage comparators each having two input terminals and one output terminal. a charging/discharging capacitor; a charging/discharging circuit comprising a charging means connected to the charging/discharging capacitor; and a discharging switching means connected to the charging/discharging capacitor; The information on the appropriate exposure value from the output of the arithmetic circuit is applied to the input terminal of , the terminal voltage of the charge/discharge capacitor is applied to the other input terminal, and one input of the second voltage comparator is applied. It is an A-D conversion circuit in which the terminal voltage of the charging/discharging capacitor is applied to one terminal, and the reference voltage set in relation to the information on the appropriate exposure value is applied to the other input terminal, and its clock input is further comprising a delay type flip-flop to which a clock signal is applied and whose data input terminal controls the charging means in response to the signal at the output terminal of the second voltage comparator; When the terminal voltage becomes lower than the reference voltage due to the discharge of the charging/discharging capacitor, the output of the second voltage comparator makes the discharging switching means non-conductive, and the output of the delay flip-flop changes. increases the terminal voltage by controlling the charging means, and when the terminal voltage reaches the reference voltage due to this increase, the output of the delay type flip-flop interrupts the charging operation of the charging means. By this, the terminal voltage is held at a value close to the reference voltage, and then when the level of the clock signal changes to a predetermined state, the output of the delay type flip-flop controls the charging means to increase the terminal voltage again. At the same time, measurement of the clock signal is started based on the outputs of the first and second voltage comparators and the output of the delay type flip-flop, and when the terminal voltage exceeds the value of the appropriate exposure value information. The measurement of the clock signal is stopped based on the outputs of the first and second voltage comparators and the output of the delay type flip-flop, and digital information of the appropriate exposure value digitized by the stopped measurement clock signal is read. A camera characterized by obtaining.