JPS63261172A - Frequency detecting circuit - Google Patents
Frequency detecting circuitInfo
- Publication number
- JPS63261172A JPS63261172A JP9444487A JP9444487A JPS63261172A JP S63261172 A JPS63261172 A JP S63261172A JP 9444487 A JP9444487 A JP 9444487A JP 9444487 A JP9444487 A JP 9444487A JP S63261172 A JPS63261172 A JP S63261172A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuits
- output
- exclusive
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 238000001514 detection method Methods 0.000 claims abstract description 13
- 238000007599 discharging Methods 0.000 claims description 3
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 abstract 1
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 abstract 1
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 abstract 1
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 abstract 1
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 abstract 1
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 abstract 1
- KIWSYRHAAPLJFJ-DNZSEPECSA-N n-[(e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enyl]pyridine-3-carboxamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/CNC(=O)C1=CC=CN=C1 KIWSYRHAAPLJFJ-DNZSEPECSA-N 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 7
- 239000013256 coordination polymer Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101100113576 Arabidopsis thaliana CINV2 gene Proteins 0.000 description 1
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
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- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は所定周波数以上の信号を検出する検出回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detection circuit that detects a signal having a predetermined frequency or higher.
従来、この種の周波数検出回路はワンショットマルチバ
イブレータ回路及び積分回路によって構成されるＦ−Ｖ
変換回路の出力を、非反転入力端子に基準の定電圧源を
接続したコンパレータの反転入力端子に接続し、前記コ
ンパレータの出力により周波数検出を行っている。Conventionally, this type of frequency detection circuit is an F-V composed of a one-shot multivibrator circuit and an integrating circuit.
The output of the conversion circuit is connected to the inverting input terminal of a comparator whose non-inverting input terminal is connected to a reference constant voltage source, and the frequency is detected by the output of the comparator.
第３図に従来の構成を示す。波形整形回路３１と、ワン
ショットマルチバイブレータ回路３２及び積分回路３３
によシ構成されるＦ −Ｖ変換回路３４と、とのＦ−Ｖ
変換回路３４の出力と定電圧源（Ｖｒｅｔｏ ）を入力
とするヒステリシス特性を持ったコンパレータ３５とを
備えた構成となっている。FIG. 3 shows a conventional configuration. A waveform shaping circuit 31, a one-shot multivibrator circuit 32, and an integrating circuit 33
The F-V conversion circuit 34 configured by
The comparator 35 has a hysteresis characteristic and receives the output of the conversion circuit 34 and a constant voltage source (Vreto) as input.
動作において、入力端子３０にある周波数（ｆｏ）のパ
ルス波（ＰＷ、ｏ）が印加されると回路３１を通シ、回
路３２によってＰＷＱは第４図の様々パルス幅が一定の
パルス波（ＰＷ］）に変換さｎ−る。１このパルス波Ｐ
Ｗｌは回路３３によシ直流電圧（ＶＣＯＵＴ ）に変換
される。この時、ＰＷＩの振幅（Ｖｃｃ）、ＰＷｌの一
周期におけるハイレベル（ＴＯＮ）、ｏウレベ＃（ＴＯ
ＦＦ）とＶＣＯＵＴの関係は
で表わさ扛、第５図の様に周波数）ｌよシ変化する。In operation, when a pulse wave (PW, o) with a certain frequency (fo) is applied to the input terminal 30, the circuit 31 passes through the circuit 32, and the circuit 32 converts PWQ into a pulse wave (PW, o) with various pulse widths constant as shown in FIG. ]) is converted to n-ru. 1 This pulse wave P
Wl is converted into a DC voltage (VCOUT) by circuit 33. At this time, the amplitude of PWI (Vcc), the high level in one cycle of PWl (TON),
The relationship between FF) and VCOUT is expressed as , which changes with frequency) as shown in FIG.
この特性を用いコンパレータ３５の非反転入力端子に定
電圧源によシ検出周波数（ＴｆＨｌ）に応じた電圧（Ｖ
ｒｅｆＯ）を加え反転入力端子に加わるＶＣＯＵＴとの
関係が
Ｖ Ｃ０ＵＴ≧■ｒｅｆｏ ’・・
−（２）と々った時コンパレータ３５の出力３６にて第
５図の様に周波数を検出する様になっていた。Using this characteristic, a constant voltage source is applied to the non-inverting input terminal of the comparator 35 to generate a voltage (V
refO) and VCOUT applied to the inverting input terminal is V C0UT≧refO '...
-(2) When the frequency is exceeded, the frequency is detected at the output 36 of the comparator 35 as shown in FIG.
前述した従来の周波数検出回路においては回路３３が抵
抗（ＲＡ）と一端が接地さ唱、ているコンデンサ（ＣＡ
）とで構成されている為、ＣＡの充放電によりＶＣＯＵ
Ｔに時定数の分だけ遅れが生じその結果ＴｆＨ１の検出
によるＣ０Ｍ０ＶＴＲも遅れが生じるという欠点がある
。In the conventional frequency detection circuit described above, the circuit 33 consists of a resistor (RA) and a capacitor (CA) whose one end is grounded.
), due to charging and discharging of CA, VCOU
There is a drawback that there is a delay in T by a time constant, and as a result, there is also a delay in C0M0VTR due to the detection of TfH1.
ここで、現実的な（集積回路における）周波数検出時間
の遅れを求めてみる。Here, let's find a realistic delay in frequency detection time (in an integrated circuit).
第５図に示す様に、ある周波数（ｆｌ）がＩＮ端子に印
加された時Ｆ−Ｖ変換回路３４によって直流電圧に変換
されコンパレータ３５の入力端子に印加される電圧をＶ
ｌとする。又ｆｌが他のある周波数（ｆｚ）に急激に変
化した時Ｆ −Ｖ変換回路３４によって直流電圧に変換
されコンパレータの入力端子に印加さ扛る電圧をｖ２と
すると入力周波数が急激に変化した場合の応答時間Ｔは
、（ｆ＋＜ｆｚ 、 Ｖｌ＜Ｖ２）
で表わされる。As shown in FIG. 5, when a certain frequency (fl) is applied to the IN terminal, it is converted into a DC voltage by the F-V conversion circuit 34 and the voltage applied to the input terminal of the comparator 35 is V.
Let it be l. Also, when fl suddenly changes to a certain other frequency (fz), the voltage that is converted to a DC voltage by the F-V conversion circuit 34 and applied to the input terminal of the comparator is v2, and when the input frequency suddenly changes. The response time T is expressed as (f+<fz, Vl<V2).
ここで（３）式に現実の直を代入し応答時間Ｔを求めて
みる。Here, the response time T is calculated by substituting the actual speed into equation (3).
抵抗Ｒ，Ａ＝１にΩ、コンデンサＣＡ＝１６μＦ直流電
圧Ｖｌ ＝ ０．５ Ｖ 、 直流電圧Ｖ２＝ ２．０
■とした場合を考えると
＝ ２２．２ （ｍ Ｓ ）
とな９、Ｆ−Ｖ変換助１路３４に積分回路３３を用いた
従来の周波数検出回路は入力周波数の急激な変化に対し
て上記の式で求めたＴ＝２２．２ｍｓ の応答の遅れを
生じる。Resistor R, A = 1Ω, capacitor CA = 16 μF DC voltage Vl = 0.5 V, DC voltage V2 = 2.0
Considering the case of ■ = 22.2 (m S )9, the conventional frequency detection circuit using the integrating circuit 33 in the F-V conversion auxiliary circuit 34 has the above-mentioned problem in response to sudden changes in the input frequency. This results in a response delay of T=22.2 ms, which is calculated using the equation.
本発明の周波数検出回路は、充電用吐き出し型定電流回
路と、入力ロウレベル時動作する吸い込み型定電流回路
と、一端が接地されたコンデンサを非反転入力とし反転
入力には定電圧源が接続されヒステリシス特性を持った
コンパレータとを有する回路を二組備え、一方の出力は
排他的論理和の一人力に接続される。排他的論理和のも
う一方の入力には前記吸い込み型定電流回路の入力が接
続され、その排他的論理和の出力はラッチ回路のセット
端子に接続される。又前記ヒステリシス特性を持ったコ
ンパレータのもう一方の出力は前記ラッチ回路のリセッ
トｆＡ子に接続される。The frequency detection circuit of the present invention includes a source-type constant current circuit for charging, a sink-type constant current circuit that operates when the input is at a low level, a capacitor whose one end is grounded as a non-inverting input, and a constant voltage source connected to the inverting input. Two sets of circuits each having a comparator with hysteresis characteristics are provided, and the output of one is connected to the single output of the exclusive OR. The input of the sink type constant current circuit is connected to the other input of the exclusive OR, and the output of the exclusive OR is connected to the set terminal of the latch circuit. The other output of the comparator having hysteresis characteristics is connected to the reset fA terminal of the latch circuit.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例であ’）、ＩＣ０Ｍ １〜Ｉ
Ｃ０Ｍ４は定電圧源、ＶｒｅｆｌおよびＶｒｅｆ２は定
電圧源％Ｑ１およびＱ２はＮＰＮトランジスタ、ＣＰ、
Ｃｈはコンデンサ、２００および３００はヒステリシス
特性を持つコンパレータ、ＩＮＶＩ〜Ｉ Ｎ Ｖ ３ｉ
ｊ（／Ａ−夕回路、Ｎ０Ｒ１−ＮＯＲ４はノア回路であ
り、図示のように接続されている。FIG. 1 shows an embodiment of the present invention'), IC0M 1 to I
C0M4 is a constant voltage source, Vrefl and Vref2 are constant voltage sources % Q1 and Q2 are NPN transistors, CP,
Ch is a capacitor, 200 and 300 are comparators with hysteresis characteristics, INVI~INV 3i
j(/A-NOR circuit, N0R1-NOR4 are NOR circuits, and are connected as shown in the figure.
ｔＮｖ２ 、ＩＮＶ３おｊびＮＯＲ，１−ＮＯＲ４によ
って排他的論理和を構成し、ＳＲはＳＲラッチ回路であ
る。ｑは入力端子である。tNv2, INV3 and NOR, 1-NOR4 form an exclusive OR, and SR is an SR latch circuit. q is an input terminal.
ｑに入力するパルス信号が７・イソベル時、ＮＰＮトラ
ンジスタＱｌ−Ｑ２はオフし、定電流源ＩＣ０Ｍ１によ
ってコンデンサＣＰは充電され、又、定電流源Ｉ Ｃｏ
ｔ−１３によってコンデンサＣｈも充電される。一方ｑ
に入力するパルス信号がロウレベル時ＮＰＮトランジス
タＱｌ−Ｑ２はオンｌ定電流源ＩＣＱＭ ２によってコ
ンデンサＣＰは放′屯され、又、定電流源Ｉ ＣＯＭ
４によってコンデンサａｈも放電される。When the pulse signal input to q is 7 isobels, the NPN transistors Ql-Q2 are turned off, the capacitor CP is charged by the constant current source IC0M1, and the constant current source ICo
Capacitor Ch is also charged by t-13. On the other hand, q
When the pulse signal input to is low level, the NPN transistor Ql-Q2 is turned on. The capacitor CP is discharged by the constant current source ICQM2, and the constant current source ICOM
4, the capacitor ah is also discharged.
周波数検出はコンデンサｃｈの電圧Ｖｃｈ＞Ｖｒｅｆ２
になった時行わｆＬる。周波数ＴｆＨｚの検出方法は入
力端子ｑに入力されるパルス信号のハイレベル１．の立
上りで検出している。コンパレータ２００の放電時定数
で決丑るｔｐｌｉｓ几ラッチ回うＳＲのセット入力ＳＫ
、コンパレータ３００の出力を５Ｉ−ｔ、のりセット入
力ＲＫそれぞれ入力している。ここで、コンパレータ３
００の出力Ｋ Ｋおけるパルス幅ｔｐ２は排他的論理和
の出力Ｋにおけるパルス幅ｔｐｌとの間でｔｐ２＞ｔｐ
ｌの関係を持たしている。従って第２図で表わさ乳る様
、Ｔ ｆ Ｈｚ≦ｔ１ではｔｐ２＞ｔｐｌの為ＳＲラッ
チ回路の出力は、リセット状態でロウレベルとなってい
る０、シかしＴ ｆ Ｈｚ ） ｔ １となるとコンデ
ンサｃｈ電圧■。ｈ ＞ Ｖ ｒｅｆ ２となりコンパ
レータ３００の出力がロウレベルとなる、その為ＳＲラ
ッチ回路のリセット状態が解除されＳＲラッチ回路の出
力がハイレベルとなシ周波数を検出する。この時の周波
数検出の遅れはノア回路インバータ回路の遅れであり通
常数１．０ ｎ Ｓとなる。Frequency detection is the voltage of capacitor ch>Vref2
It is done when it becomes fL. The frequency TfHz is detected by detecting the high level 1. of the pulse signal input to the input terminal q. It is detected at the rising edge of . SR set input SK that rotates the tplis latch determined by the discharge time constant of the comparator 200
, the output of the comparator 300 is inputted to 5I-t and the glue set input RK, respectively. Here, comparator 3
The pulse width tp2 at the output K of 00 and the pulse width tpl at the output K of the exclusive OR is tp2>tp.
It has a relationship of l. Therefore, as shown in Figure 2, when T f Hz ≦ t1, since tp2 > tpl, the output of the SR latch circuit is 0, which is low level in the reset state. ch voltage■. h > V ref 2, and the output of the comparator 300 becomes low level. Therefore, the reset state of the SR latch circuit is released, and the output of the SR latch circuit becomes high level, and the frequency is detected. The delay in frequency detection at this time is the delay of the NOR circuit inverter circuit, and is usually several 1.0 nS.
以上説明した回路を用いる事によシ、本発明は従来Ｆ−
Ｖ変換回路内におけるコンデンサの充放電による周波数
検出の遅れが数１０ｍ５生じていたのに対し回路内のイ
ンバータ回路、ノア回路のみの遅れ（通常数１． Ｑ
ｎ Ｓ ）になシ、きわめて周波数検出における応答時
間の遅れをいちじるしく少なくする効果がある。By using the circuit described above, the present invention can be applied to the conventional F-
The delay in frequency detection caused by charging and discharging the capacitor in the V conversion circuit used to be several tens of meters, but the delay in only the inverter circuit and NOR circuit in the circuit (usually several tens of meters)
n S ) has the effect of significantly reducing the response time delay in frequency detection.
第１図は本発明の一実施例を示す回路図、第２図は第１
図におけるタイミングチャート、第３図は従来例図、第
４図および第５図は第３図におけるタイミングチャート
及び士”−Ｖグラフとタイミングチャートである。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a diagram of a conventional example, and FIGS. 4 and 5 are a timing chart, a V graph, and a timing chart in FIG. 3.
Claims (1)
びコンデンサと、前記コンデンサに並列に結合され入力
信号によって制御される放電用電流源と、前記コンデン
サの電圧を基準電圧と比較するコンパレータとを有する
回路を二組備え、一方の回路出力を排他的論理和手段の
一方の入力に加え、前記排他的論理和手段の他方の入力
に前記入力信号を加え、前記排他的論理和手段および他
方の回路の出力をラッチ回路のセット端子およびリセッ
ト端子にそれぞれ供給したことを特徴とする周波数検出
回路。a current source and a capacitor connected in series between first and second potential terminals; a discharging current source coupled in parallel to the capacitor and controlled by an input signal; and a comparator that compares the voltage of the capacitor with a reference voltage. The output of one circuit is applied to one input of the exclusive OR means, the input signal is applied to the other input of the exclusive OR means, and the output of the circuit is applied to one input of the exclusive OR means, and the input signal is applied to the other input of the exclusive OR means. A frequency detection circuit characterized in that the output of the circuit is supplied to a set terminal and a reset terminal of a latch circuit, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094444A JPH0769360B2 (en) | 1987-04-17 | 1987-04-17 | Frequency detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094444A JPH0769360B2 (en) | 1987-04-17 | 1987-04-17 | Frequency detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63261172A true JPS63261172A (en) | 1988-10-27 |
| JPH0769360B2 JPH0769360B2 (en) | 1995-07-26 |
Family
ID=14110429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62094444A Expired - Lifetime JPH0769360B2 (en) | 1987-04-17 | 1987-04-17 | Frequency detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0769360B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013088281A (en) * | 2011-10-18 | 2013-05-13 | Denso Corp | Frequency measuring instrument |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866367U (en) * | 1981-10-30 | 1983-05-06 | 日本電気ホームエレクトロニクス株式会社 | Pulse period discrimination circuit |
-
1987
- 1987-04-17 JP JP62094444A patent/JPH0769360B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866367U (en) * | 1981-10-30 | 1983-05-06 | 日本電気ホームエレクトロニクス株式会社 | Pulse period discrimination circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013088281A (en) * | 2011-10-18 | 2013-05-13 | Denso Corp | Frequency measuring instrument |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0769360B2 (en) | 1995-07-26 |
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