JPS62219818A - Voltage/pulse period converter - Google Patents

Abstract

PURPOSE:To output a square pulse always stable in period with respect to a constant input signal by providing a clock pulse generating circuit generating a stable pulse and an A/D converter generating a digital signal proportional accurately to the input signal. CONSTITUTION:A clock pulse generating circuit 4 generates a clock pulse signal 9, a counter circuit 3 counts the signal 9 and outputs a count output signal 8. The input voltage signal 6 is converted into a digital output signal 7 by an A/D converter 1. The digital output signal 7 and the count output signal 8 are inputted to an XOR circuit 2 and when the two signals are coincident, a logic output signal 10 of the XOR circuit 2 rises, the counter circuit 3 is reset simultaneously and the logic output signal 10 descends again. Further, the pulse output signal 12 of a T flip-flop 5 is inverted by the trailing edge of the logic output signal 10. The operation above is repeated and a pulse output signal 12 of 50% duty is obtained from a pulse output terminal 13 of the T flip-flop 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a voltage/pulse period converter for generating pulses with a repetition period proportional to an input voltage.

2. Description of the Related Art In recent years, with the development of electronic circuits, various conversion devices have become necessary, and in particular, there has been a demand for a voltage/pulse period conversion device that converts a voltage signal into a pulse period due to the simplicity of signal processing.

A conventional voltage/pulse period conversion device will be explained with reference to FIGS. 4 and 6.

In FIG. 4, a frequency setting section 21 that sets the frequency of the output signal includes a bias resistor 27, 28 and a DC power supply 2.
It is composed of a voltage dividing circuit consisting of 9 circuits. This divided voltage is then input to the non-inverting input terminal of the operational amplifier 26.
A DC power supply 29 is connected to the inverting input terminal via a charging resistor 24.
is not applied.

This operational amplifier 26 is negatively connected via a capacitor 26, and a charge/discharge switching transistor 3o is connected to an inverting input terminal via a discharge resistor 36. A diode 31. is connected to the base of the transistor 30. A bias resistor 13 is connected.

The amplitude limiting circuit 23, which receives the voltage signal output from the output terminal 41 of the integrating circuit 22 configured as described above, limits the amplitude. The amplitude limiting circuit 23 includes a comparator which inputs the output of the integrating circuit 22 and the signal of the voltage input terminal 40 via a field effect transistor 33 connected thereto, and a diode 35 . Bias resistor 37. Pull-down resistor 3
It is composed of 4.

With the above configuration, the charge/discharge switching transistor 30 is turned off.
When F, if voltage VT is applied to voltage input terminal 40,
The operational amplifier 2e charges the capacitor 26 through the charging resistor 24 so that the voltage is the same as the voltage divided by the bias resistors 27 and 28, and the voltage signal at the output terminal 41 becomes a straight line as shown in FIG. begins to decrease. At the same time, the field effect transistor 33 of the amplitude limiting circuit 23 is turned off, and the voltage at the non-inverting input terminal 38 of the comparator 32 becomes 0.
[v], and the voltage signal at the output terminal 41 becomes smaller than o (V), the voltage signal at the output terminal 42 becomes as shown in FIG.
), turn the charging/discharging transistor 3° to O.
I'll end up doing N.

When the charging/discharging transistor 3o is turned on, the voltage charged in the capacitor 26 by the operational amplifier 26 is passed through the discharging resistor 36 so as to have the same potential as the divided voltage of the bias resistors 27 and 28. discharge, output terminal 41
The voltage signal begins to increase in a straight line as shown in FIG. At the same time, the field effect transistor 33 of the amplitude limiting circuit 23 is turned on, the voltage V7 applied to the voltage input terminal 40 is applied across the resistor 34, the voltage at the non-inverting input terminal 38 of the comparator 32 becomes equal to vT, and the output When the voltage signal at the terminal 41 becomes larger than vT, the output voltage of the comparator 32 is inverted again, the charging/discharging switching transistor 3o is turned off, the above-mentioned state is repeated, and the output terminals 41 and 42 are respectively set to ), triangular wave signals and square wave pulse signals as shown in (b) are obtained.

The amplitude of the voltage signal at the output terminal 41 was equal to the voltage vT applied to the voltage input terminal 40, and a square wave pulse with a period T proportional to the voltage V7 was obtained at the output terminal 42 of the comparator 32.

Problems to be Solved by the Invention However, in such a conventional configuration, the charging/discharging time of the square wave pulse depends on the resistance values of the charging resistor and discharging resistor, the emitter-collector voltage of the charging/discharging switching transistor, etc. Therefore, there was a problem in that these constants fluctuated due to variations in the elements, making it impossible to obtain a stable square wave pulse signal at the output terminal 42.

FIG. 6 shows the input voltage Vτ applied to the voltage input terminal 40.
In this characteristic diagram, curve A showing the relationship between the input voltage V7 and the period T is as follows.
Due to variations in the elements, there is variation in the shaded area 9, which is unstable.

The present invention solves these problems.

It is an object of the present invention to provide a voltage/period conversion device that outputs pulses with a stable period for a constant input voltage.

Means for Solving the Problem In order to solve this problem, the voltage/pulse period conversion device of the present invention includes an A/D converter that generates a digital output signal proportional to an input signal, and a clock that generates a clock pulse signal. a pulse generation circuit; a counter circuit that counts the output signal of the clock pulse generation circuit and outputs a count output signal corresponding to the counted count value; a digital output signal of the A/D converter; an exclusive OR circuit that inputs a count output signal and outputs a logic output signal when the Okayama force signal matches;
The counter circuit is provided with a flip-flop circuit having a pulse output terminal that inputs the logic output signal of the exclusive OR circuit and inverts the output signal, and the counter circuit inputs the logic output signal to the reset input terminal, and receives the logic output signal from the logic output signal. The configuration is such that the count value is reset.

Function: With this configuration, the counter circuit counts clock pulses, and when the count output signal of the counter circuit and the digital output signal of the A/D converter match, the exclusive OR circuit emits a logical output signal and converts the signal into In response, the output signal of the flip-flop circuit is inverted and the count value of the counter circuit is reset. If the digital output signal and the count output signal match again, the flip-flop circuit inverts the output signal again to obtain a pulse.

By repeating this operation, the input voltage is converted into pulses with a constant period.

EXAMPLE Hereinafter, an example of the present invention will be explained based on FIGS. 1 to 3. In FIG. 1, an A/D converter 1 converts an input voltage signal 6 into a digital output signal 7. The clock pulse generation circuit 4 converts the generated clock pulse signal 9 into
The counter circuit 3 counts the clock pulse signals and obtains a count output signal 8 corresponding to the count value. An exclusive OR circuit (hereinafter referred to as an XOR circuit) 2 which receives the count output signal 8 and the digital output signal 7 outputs a logical output signal 1o when the Okayama power signals 7 and 8 match. This output signal 1o is output to the T-type flip-flop circuit 6 and the reset input terminal 11 of the counter circuit 3.

The T-type flip-flop circuit inverts the H level and L level by the OR output signal, and the counter circuit resets the count value.

The operation of the voltage/pulse period converter having the above configuration will be explained with reference to FIG. 2.

The clock pulse generation circuit 4 generates a clock pulse signal 9 shown in FIG. 2, the counter circuit 3 counts the clock pulse signal 9, and outputs a count output signal 8 corresponding to the counted value. Input voltage signal 6 is A/D converter 1
is converted into a digital output signal 7. This digital output signal 7 and count output signal 8 are input to the XOR circuit 2, and when the two signals match, the logic output signal 1o of the XOR circuit 2 rises as shown in FIG.
At the same time, the counter circuit 3 is reset and the logic output signal 1
0 falls again. Furthermore, when the logic output signal 1o falls, the pulse output signal 13 of the T-type flip-flop 6
is reversed. By repeating the above operations, a pulse output signal 12 with a duty ratio of 50% is obtained from the pulse output terminal 13 of the T-type flip-flop 6.

As shown in FIG. 2, the time for the pulse output signal 12 to invert is determined by the time required for the count output signal 8 to count up and match the digital output signal 7 after the counter circuit 3 is reset. , the period T of the pulse output signal 12 is inversely proportional to the frequency of the clock pulse signal 4 compared to the voltage of the input voltage signal 6 and the voltage-to-digital output conversion rate of the A/D converter 1, so the period T of the pulse output signal 13 is is T=α·vT/fT, where vT is the voltage fT of the input voltage signal 6, and the frequency α of the clock pulse signal 9 is the voltage-to-digital output conversion rate of the A/D converter 1.

Note that the frequency fT of the clock pulse signal 9 is easy to stabilize, and the voltage-digital output conversion rate α of the A/D converter 1 is also stable, so a stable square wave pulse signal can be obtained for a constant input voltage vT. It will be done.

FIG. 3 is a characteristic diagram showing the relationship between the input voltage vT of the input voltage signal 6 and the period T of the pulse output signal.

As is clear from this characteristic diagram, according to this embodiment, the input voltage vT and the period T of the pulse output signal are in a proportional relationship.
The input voltage VT can be accurately converted into a period T.

, Effects of the Invention As described above, according to the present invention, a clock pulse generation circuit that generates stable pulses and an A/D:1 converter that generates a digital signal in exact proportion to an input signal are used. Since the voltage/pulse period conversion device is constructed using the above-mentioned voltage/pulse period converter, it is possible to always output a square wave pulse with a stable period in response to a constant input signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a voltage-pulse period converter according to an embodiment of the present invention, FIG. 2 is a timing chart showing each signal of the voltage-pulse period converter, and FIG. 3 is a voltage-pulse period converter. 4 is an electric circuit diagram showing a conventional voltage pulse period converting device, FIG. 6 is a timing chart showing each signal of the voltage/pulse period converting device, and FIG. Figure 6 shows the same voltage 11/
It is a relationship diagram between the input voltage VT and the period T of the <Russ period conversion device. 1...A/D converter, 2...10
8 circuits, 3...counter circuits, 4...
Clock pulse generation circuit, 6...T-type flip-flop circuit, 13...pulse output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Illustration A(le Vr(vl)

Claims (1)

[Claims] A/D that generates a digital output signal proportional to the input signal
a converter, a clock pulse generation circuit that generates a clock pulse signal, a counter circuit that counts output signals of the clock pulse generation circuit and outputs a count output signal corresponding to the counted count value, and the A/D converter. and an exclusive OR circuit which inputs the digital output signal of and the count output signal of the counter circuit and outputs a logic signal when both output signals match, and inputs the logic output signal of the exclusive OR circuit, A voltage/pulse period conversion device comprising a flip-flop circuit having a pulse output terminal for inverting an output signal, wherein the counter circuit inputs a logic output signal to a reset input terminal and resets a counter value by the logic output signal.