KR950006077Y1 - Voltage/frequency transducer - Google Patents

Abstract

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Description

Voltage / frequency converter

1 is a positive voltage / frequency converter circuit diagram.

2A and 2B are circuit connection diagrams in the reset mode and the integral mode of the frequency generator 1;

3 is an output waveform diagram of the frequency generator 1 of FIG.

4 is a converter circuit diagram of the present invention.

5 is a circuit diagram for explaining the operation of the present invention when a positive voltage input.

6A to 6D and 7A to 7D are waveform diagrams of respective portions of FIG. 4 at the input of a positive voltage and a negative voltage.

* Explanation of symbols for main parts of the drawings

1: Frequency generator OP1: Operational Amplifier

CP1, CP11, CP12: comparators NAND1 to NAND4: NAND gate

MM1, MM11: Monostable Multivibrator FF1: Flip-flop

FET1, FET2: Field Effect Transistor

The present invention relates to voltage-to-frequency conversion, and more particularly, to a voltage / frequency converter capable of converting both positive and negative voltages into frequencies so that the voltage can be counted as a digital value.

In general, the positive voltage / frequency converter used in the output terminal of the frequency generator 1 converts the positive voltage Vin input through the resistor Rin into a frequency waveform thereof, as shown in FIG. Is connected to the inverting input terminal of the comparator CP1, and its output terminal is connected to the trigger terminal of the monostable multivibrator MM1 to shape the frequency waveform of the frequency generating section 1, and the frequency as the output signal. The generating unit 1 is configured to be controlled, and looks at this as follows.

When the low potential signal is output from the monostable multivibrator MM1, as shown in FIG. 2B, the switch S1 is connected to the output terminal of the operational amplifier OP1 so that the frequency generator 1 operates in the integral mode. The capacitor Cint is charged by the input voltage Vin, and the output voltage of the operational amplifier OP1 is lowered.

As described above, when the output voltage of the operational amplifier OP1 is lowered and the time T1 elapses, the non-inverting input voltage of the comparator CP1 becomes higher than the inverting input, so that a high-potential signal is output therefrom. The high potential signal is outputted during the time Tos set by the capacitor Cos.

The switch S1 as shown in FIG. 2A is connected to the inverting input terminal by the high potential output signal of the monostable multivibrator MM1, so that the frequency generator 1 operates in the reset mode. Cint is discharged to increase the output voltage of the operational amplifier OP1.

Since the times Tos and T1 are determined by the capacitor Cos and the positive input voltage Vin, respectively, T1 is changed according to the input voltage Vin, so that the positive input voltage from the frequency generator 1 The frequency for Vin is output.

The frequency waveform output from the frequency generator 1 is compared with the reference voltage by the comparator CP1, and the waveform is shaped since the high potential pulse with Tos + T1 is output from the monostable multivibrator MM1.

Therefore, a positive voltage is converted to a frequency corresponding thereto, but if the input voltage is negative, the corresponding frequency is not output, which is inconvenient.

Accordingly, the present invention is described in detail by the accompanying drawings as a transducer designed to output a frequency corresponding to both positive and negative input voltage as follows.

In the converter of the present invention, as shown in FIG. 4, the capacitor Cint is connected between the inverting input terminal and the output terminal, and the output terminal of the operational amplifier OP1 to which the input voltage Vin is applied to the inverting input terminal side is referred to. Common connection with the inverting input terminal and the non-inverting input terminal of negative and positive input voltage (Vin) comparators (CP11) and (CP12) for which voltages are set, respectively, and these output terminals are for power-up (+ Vs) Commonly connected to the input terminals S and R of the cathodes of the diodes D1 and D2 and the flip-flop FF1, respectively, and a power supply (+ Vs) is connected to the trigger terminal Tr. ), The output terminal Q of the monostable multivibrator MM11 connected through the diodes D1 and D2 is commonly connected to one input terminal of the NAND gates NAND3 and NAND4, and the flip is connected to the other input terminal. Output terminal Q1 of the flop FF1, ( ) Are connected to the NAND gates NAND3 and NAND4 so that the frequencies for the negative voltage and the positive voltage are output, and the on / off control of the field effect transistors FET1 and FET2 is controlled at this frequency. The capacitor Cint is configured to be discharged, and its operation and effects are as follows.

First, when the input voltage Vin is positive, the capacitor Cint is charged, and the negative voltage, which is the output voltage of the operational amplifier OP1, is lowered so that the non-inverting input voltage of the comparator CP11 is always higher than the inverting input voltage. Therefore, a high potential signal is output therefrom, and a low potential signal is output from this comparator CP12 when it becomes equal to the reference voltage set at the inverting input terminal of the comparator CP12.

Therefore, the high potential and low potential signals are input to the input terminals S and R of the flip-flop FF1, respectively, and the output terminals Q1 and ( The low potential and high potential signals are respectively output to NAND gates and input to one input terminal of the NAND gates NAND3 and NAND4.

On the other hand, the diode D2 is turned on by the low potential output signal of the comparator CP12 so that the monostable multivibrator MM11 is triggered by the low potential signal, which is the voltage across the diode D2, to the output terminal Q. As shown in FIG. 6C, a high potential signal having a pulse width Tos set by the capacitor Cos is output and applied to the other input terminal of the NAND gates NAND3 and NAND4.

Therefore, high potential and low potential signals are respectively output from the NAND gates NAND3 and NAND4, and the field effect transistors FET1 and FET2 are turned on and off, respectively.

At this time, the charging voltage of the capacitor Cint is discharged through the variable resistor VR1 and the resistors R9 and R13 to increase the output voltage of the operational amplifier OP1 and output a high potential signal from the comparator CP12.

As a result, since the diode D2 is also turned off, a high potential signal is applied to the monostable multivibrator MM11 so that it is not triggered, and thus a low potential signal is output. Is output.

Accordingly, the field effect transistor FET2 is turned on, thereby charging the capacitor Cint.

That is, the output signal of the comparator CP11 is always high potential, and as the positive input voltage Vin is charged and discharged to the capacitor Cint and compared with the reference voltage in the comparator CP12, its output signal is either high potential or low potential. In addition to the delegation, since the capacitor Cint is discharged by the field effect transistor FET2, a frequency conversion circuit for positive voltage is formed as shown in FIG.

Thus, when the waveform diagram of FIG. 6 is described, when the input voltage Vin is a positive voltage, the capacitor Cint is charged and discharged, and the output voltage of the operational amplifier OP1 is as shown in FIG. 6A. The output voltage of the operational amplifier OP1 is converted into a signal having a waveform as shown in FIG. 6B as compared in the comparator CP12, and then a waveform as shown in FIG. 6D. It is formatted and output.

When the input voltage Vin is negative, as the capacitor Cint is charged, the positive voltage, which is the output voltage of the operational amplifier OP1, is increased, and therefore, the comparator CP11, the diode D1, the NAND1, NAND3 and field effect transistor FET1 perform the same operations as comparator CP12, diode D2, NAND gate NAND2, NAND4, and field effect transistor FET2 at a positive voltage input. The frequency corresponding to the negative voltage is output.

Therefore, referring to FIG. 7, which is a waveform diagram at the time of negative voltage input, the output voltage of the operational amplifier OP1 is changed to the frequency corresponding to the input voltage Vin as shown in FIG. 7A by the charging and discharging of the capacitor Cint. The output voltage of the operational amplifier OP1 is compared in the comparator CP11 and converted into a signal having a waveform as shown in FIG. 6B, and then waveform-formed and output as shown in FIG. 6D.

As described above, the present invention has the convenience of converting a positive voltage and a negative voltage into a frequency corresponding to the voltage to measure a voltage value.

Claims (1)

A capacitor Cint is connected between the inverting input terminal and the output terminal, and the output terminal of the operational amplifier OP1 to which the input voltage Vin is applied to the inverting input terminal side is a negative and positive input voltage comparator (CP11), Commonly connected to the inverting input terminal and the non-inverting input terminal of CP12, and the output terminals thereof are the input terminals of the pull-up power supply (+ Vs) side, the diodes of the diodes D1 and D2, and the flip-flop FF1. The output terminals of the monostable multivibrator MM11, which are commonly connected to each other and whose power supply (+ Vs) is input to the trigger terminal Tr through the resistor R3 and the diodes D1 and D2, are connected to the NAND gate NAND3, In common connection to one input terminal of NAND4, the output terminals Q1 and (1) of the flip-flop FF1 are connected to their other input terminals. ) Are connected to each other so that frequencies for the negative and positive input voltage Vin are output from the NAND gates NAND3 and NAND4, and at this frequency, the field effect transistors FET1 and FET2 are turned on. The off-controlled voltage / frequency converter, characterized in that configured to discharge the capacitor (Cint).