JPH0572768B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a retriggerable monostable multivibrator which is formed by combining logic circuits whose basic configuration is that of a differential amplifier.

[Background technology and its problems]

For example, as shown in US Pat. No. 3,259,761, a logic circuit is known that has a basic configuration of a differential amplifier in which the emitters of transistors are connected in common. This logic circuit is an ECL (Emitter Coupled
Logic). As shown in FIG. 6, a retriggerable monostable multivibrator can be constructed from an R-S flip-flop using this ECL.

In Fig. 6, 60 is R-S using ECL.
Flip-flop 61 is a time constant generating circuit. A reference voltage Vr is applied to the R-S flip-flop 60 and the time constant generating circuit 61 from a DC power supply 65.

A differential pulse for triggering this monostable multivibrator is supplied from the input terminal 62 to the set input S of the R-S flip-flop 60, and
The signal is supplied to the time constant generation circuit 61. The output Q and output of the R-S flip-flop 60 are taken out from output terminals 63 and 64, and the output of the R-S flip-flop 60 is supplied to a time constant generating circuit 61. The output of the time constant generation circuit 61 is R-S
It is applied to the reset input R of flip-flop 60.

The time constant generating circuit 61 is composed of a combination of a capacitor and a resistor, and supplies a reset signal to the reset input R of the R-S flip-flop 60 when a certain period of time has elapsed since the output of the R-S flip-flop was supplied. be. This reset signal causes the output Q of the R-S flip-flop to
The levels of and are inverted, and pulses of constant width are taken out from output terminals 63 and 64.

When the first differential pulse is supplied from the input terminal 62 and the next differential pulse is supplied before the R-S flip-flop is reset, this pulse is supplied to the time constant generating circuit 61, and this monostable multivibrator is Re-triggered.

FIG. 7 shows a specific configuration of a retriggerable monostable multivibrator using ECL. This retriggerable monostable multivibrator consists of transistors 70, 71, 72, 79 and transistors 81, 82, 83, 87.
S flip-flop and transistors 91,9
2, 93, 97, and a time constant generating circuit consisting of a resistor 98 and a capacitor 99.

Emitter of transistor 70 and transistor 7
The emitters 1 and 72 are commonly connected, and a constant current source 74 is inserted between this common connection point and the ground terminal 73. The base of transistor 70 is the reference voltage
It is connected to a terminal 75 to which Vr is applied. The base of transistor 71 is connected to input terminal 77 . The collector of the transistor 70 is the power supply terminal 76
connected to. The collectors of transistors 71 and 72 are connected to each other, to a power supply terminal 76 via a resistor 78, and to the base of a transistor 79.

A collector of transistor 79 is connected to power supply terminal 76 . A constant current source 80 is inserted between the emitter of transistor 79 and ground terminal 73, and the emitter of transistor 79 is connected to the base of transistor 81, from which an output terminal 90 is led out. The emitter of transistor 83 and the emitters of transistors 81 and 82 are commonly connected, and a constant current source 84 is inserted between this common connection point and ground terminal 73. The base of transistor 83 is connected to terminal 85 to which reference voltage Vr is applied. A collector of transistor 83 is connected to power supply terminal 76 . The collectors of the transistors 81 and 82 are connected to each other and to the power supply terminal 76 via the resistor 86.
Connected to the base of 7.

A collector of transistor 87 is connected to power supply terminal 76 . A constant current source 88 is inserted between the emitter of transistor 87 and ground terminal 73, and the emitter of transistor 87 is connected to the base of transistor 72, and an output terminal 89 is led out from this connection point.

These transistors 70, 71, 72, 79
and transistors 81, 82, 83, 87 and R
-S flip-flop is constructed, the set input S and reset input R of this flip-flop are:
Base of transistor 71 and transistor 82
supplied to the base of The output Q and the connection point between the emitter of the transistor 87 and the constant current source 88 and the connection point between the emitter of the transistor 79 and the constant current source 80
is taken from the connection point.

The reference voltage Vr has a relationship that matches the middle level of the logic amplitude between the low level (denoted as L in the following explanation) and the row level (denoted as H in the following explanation) of the set input S and reset input R. ing. For example, in a reset state, if the set input S rises to H while the output is H, transistor 7
1 is turned on and the level L is supplied to the base of the transistor 81. Therefore, transistor 8
3 is turned on, and transistors 81 and 82 are turned off. Therefore, even if the output Q rises to H and the set input S subsequently becomes L, the set state is maintained.

The emitters of transistors 91 and 92 and the emitter of transistor 93 are commonly connected, and a constant current source 96 is inserted between this common connection point and ground terminal 95. Reference voltage at the base of transistor 93
A terminal 94 to which Vr is applied is connected. A collector of transistor 93 is connected to power supply terminal 100. The collectors of transistors 92 and 91 are connected to each other, this connection point is connected to the base of transistor 97, and a resistor 98 and a capacitor 99 are inserted between this connection point and power supply terminal 100. The base of transistor 91 is connected to the base of transistor 71. transistor 9
The base of transistor 2 is connected to the connection point between transistor 79 and constant current source 80 .

The collector of the transistor 97 is the power supply terminal 100
connected to. A constant current source 101 is inserted between the emitter of transistor 97 and ground terminal 95, and a connection point between the emitter of transistor 97 and constant current source 101 is connected to the base of transistor 82.

A differential pulse is sent from the input terminal 77 to the transistor 7.
1 base (set input S), the 8th
As shown in the figure, the rising edge of this pulse R-S flip-flop is set and transistor 87
The level at the connection point between the emitter and constant current source 88 is H.
Therefore, the output at the connection point between the transistor 79 and the constant current source 80 becomes L. For this reason, transistor 9
The potential of the base of 2 becomes L. Further, at this time, the transistor 91 is turned on, and the capacitor 99 is charged with electric charge.

When the level of the differential pulse returns to L, transistors 91 and 92 are turned off and transistor 93 is turned on. Therefore, the charge stored in the capacitor 99 is discharged, and the voltage reset input R at the emitter of the transistor 97 rises.

The voltage at the emitter of transistor 97 is the reference voltage.
When the differential pulse is supplied again from the input terminal 75 before reaching Vr, the transistor 91 is turned on by this pulse, and the electric charge stored in the capacitor 99 is charged.

When the level of the differential pulse returns to L, the potential at the collector of transistor 92 rises again, the charge stored in capacitor 99 is discharged, and the voltage reset input R at the emitter of transistor 97 rises.

When the voltage reset input R at the emitter of transistor 97 rises above the reference voltage Vr, transistor 82 turns on, the R-S flip-flop is reset, and a pulse of constant width is applied to output terminals 89 and 9.
taken from 0.

The retriggerable monostable multivibrator shown in Figure 7 always outputs pulses of a constant width regardless of temperature changes or element variations, so the resistor
It is necessary to make the temperature characteristics of Vr and the reference voltage Vr similar. Since this reference voltage Vr is the reference voltage of the logic circuits in the board, it is set to be similar to the temperature characteristics of these logic circuits. However,
Since the resistor 98 determines the pulse width, it is not placed on the same substrate but is attached externally. For this reason, it is not possible to provide the same temperature characteristics as the circuit inside the board. Therefore, this retriggerable monostable multivibrator has the drawback that the output pulse width changes due to temperature changes.

Further, in order to achieve a completely retriggerable operation, it is necessary to lower the reset output R to the L level while the set input S is at the H level in the time constant generating circuit.
For this purpose, it is necessary to make the pulse width of the differential pulse input to the set input S sufficiently wide, or to increase the value of the constant current source. Increasing the differential pulse width leads to an increase in the number of elements for forming the differential pulse. Furthermore, increasing the value of the constant current increases the power consumption of the circuit.

Further, this retriggerable monostable multivibrator requires a reference voltage Vr, has a large number of elements, and has the disadvantage of increasing power consumption.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a retriggerable monostable multivibrator that is capable of outputting pulses of a constant width with little change in pulse width due to temperature changes or variations. Another object of the present invention is to provide a retriggerable monostable multivibrator with a small number of elements and low power consumption.

[Summary of the invention]

This invention provides a first differential amplifier in which the emitters of a first transistor and a second transistor are connected to a constant current source, and the emitters of a third transistor and a fourth transistor are connected to a constant current source. a second differential amplifier configured to supply a set input signal to the base of the first transistor, supply the collector output of the second transistor to the base of the fourth transistor, and supply a set input signal to the base of the first transistor; A reset input signal is supplied to the base of the fourth transistor, a collector output of the fourth transistor is supplied to the base of the second transistor, the set input signal and the reset input signal are binary signals having the same level relationship, and The signal supplied to the base of the transistor and the base of the fourth transistor has a logic amplitude equal to the logic amplitude of the binary signal and is larger than a level of approximately 1/2 of the logic amplitude of the binary signal. a third differential amplifier in which the emitters of the fifth and sixth transistors are connected to a constant current source; and an emitter follower type transistor in which the collector of the fifth transistor and its base are connected. 7 transistor, and a discharging resistor connected in parallel with a capacitor connected between the emitter of the seventh transistor and a reference potential point, supplies a set input signal to the base of the fifth transistor, and supplies the set input signal to the base of the fifth transistor. A retriggerable monostable circuit consisting of a time constant circuit that supplies the collector output of the second transistor to the base of the sixth transistor, and supplies the emitter output of the seventh transistor as a reset input signal to the base of the third transistor. It is a multi-vibrator.

〔Example〕

An embodiment of the invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention.

A retriggerable monostable multivibrator according to an embodiment of the present invention includes an R-S flip-flop consisting of transistors 1, 2, 3 and transistors 6, 7, 8, transistors 21, 22, 27, a capacitor 29, and a resistor 31. It is composed of a time constant generating circuit.

The emitters of transistors 1 and 2 are commonly connected, and this common connection point is connected to the collector of transistor 11 as a constant current source. The base of transistor 11 is connected to power supply terminal 20 . The emitter of transistor 11 is connected to ground terminal 13 via resistor 12.

An input terminal 4 is led out from the base of the transistor 1. The collector of transistor 1 is power supply terminal 5
connected to. The collector of the transistor 2 is connected to a power supply terminal 5 via a resistor 9, and is also connected to the base of an emitter follower type transistor 3. The collector of transistor 3 is power supply terminal 5
connected to. The emitter of transistor 3 is connected to the collector of transistor 14 as a constant current source. The base of transistor 14 is power supply terminal 2
Connected to 0. The emitter of transistor 14 is connected to ground terminal 13 via resistor 15.

The emitters of transistors 6 and 7 are commonly connected, and this common connection point is connected to the collector of transistor 16 as a constant current source. The base of transistor 16 is connected to power supply terminal 20. The emitter of transistor 16 is connected to ground terminal 13 via resistor 17.

A collector of transistor 6 is connected to power supply terminal 5. The collector of the transistor 7 is connected to the power supply terminal 5 via a resistor 10, and is also connected to the base of an emitter follower type transistor 8. The emitter of transistor 8 is connected to the collector of transistor 18 as a constant current source. The base of transistor 18 is connected to power supply terminal 20 . The emitter of transistor 18 is connected to ground terminal 13 via resistor 19.

The set input of the R-S flip-flop, consisting of transistors 1, 2, 3 and transistors 6, 7, 8, as described above, is applied to the base of transistor 1, and the reset input is applied to the base of transistor 6. The output Q is taken out from the connection point between the emitter of the transistor 8 and the collector of the transistor 18, and is led out from the output terminal 33. The output is taken out from the connection point between the emitter of transistor 3 and the collector of transistor 14, and is led out from output terminal 32.

FIG. 2 shows the relationship between the input level and output level of this R-S flip-flop.
The outputs Q and have a high level (H) and a low level (L), and have a logic amplitude VL. The set and reset inputs marked with a - sign have the same logic amplitude of VL, and have the H- level shifted to (1/2) lower VL level than the output Q.
and L- level. Regarding the analog level, if Vcc is the power supply voltage and the voltage drop between the base and emitter of the transistor is VBE, then H = Vcc - VBE L = Vcc - VBE - VL H - = Vcc - VBE - (1/2) VL L −=Vcc−VBE−VL−(1/2)VL is chosen. The constant current of the differential amplifier defined by the transistors 11 and 16 is I, and the resistors 9 and 1
If the value of 0 is R, then (IR=VL).

transistors 1, 2, 3 and transistor 6,
The R-S flip-flop constituted by 7 and 8 is in the reset state (Q=L,=H), and when the set input supplied to the base of transistor 1 falls from the H-level to the L-level, the transistor Since L- is lower than the base potential L of transistor 2, transistor 1 is turned off and transistor 2 is turned on. . Therefore, the output falls from H to L, transistor 7 of the differential amplifier turns off, and transistor 6 turns on, causing the output Q to rise from L to H and the output to fall from H to L.
This set state is maintained even if the set input becomes H-.

Furthermore, in the set state, when the reset input supplied to the base of transistor 6 falls from H-level to L-level, transistor 6 is turned off because L- is lower than the base potential L of transistor 7. Transistor 7 turns on. Therefore, the output Q falls from H to L, transistor 2 of the differential amplifier turns off, transistor 1 turns on, and the output rises from L to H.
This reset state is maintained even if the reset input becomes H-.

The emitters of transistors 21 and 22 are commonly connected, and this common connection point is connected to the collector of transistor 23 as a constant current source. The base of transistor 23 is connected to power supply terminal 20.
The emitter of transistor 23 is connected to ground terminal 13 via resistor 24 .

The collector of transistor 21 is resistor 25, 26
It is connected to the power supply terminal 5 via the power source terminal 5, and also to the base of the emitter follower type transistor 27. The collector of the transistor 22 has a low resistance 26
It is connected to the power supply terminal 5 via.

A collector of transistor 27 is connected to power supply terminal 5. The emitter of transistor 27 is connected to the collector of transistor 28, and a capacitor 29 is inserted between the emitter of transistor 27 and ground terminal 13. transistor 28
The base of is connected to the power supply terminal 20. The emitter of transistor 28 is connected to terminal 30. One end of a resistor 31 is attached to the terminal 30 externally from the board, and the other end of the resistor 31 is grounded.

In one embodiment of the present invention, the output of the emitter of transistor 27 is supplied as the reset input supplied to the base of transistor 6.
The logic amplitude of this reset input is H- and L-
It is necessary to do so. Therefore, a resistor 26 is provided in order to shift the output level of the emitter of the transistor 27 to a level lower by approximately 1/2 of the logic amplitude. The resistance value of this resistor 26 is R1/2, where the resistance of the resistor 25 is R1.

FIG. 3 is a time chart showing the operation of the above-mentioned retriggerable monostable multivibrator.
When a differential pulse falling from the level H- to L- is supplied to the input terminal 4, the R-S flip-flop is set at the falling edge of the pulse as shown in FIG. 3A, and the emitter of the transistor 8 and the transistor 18 are The output level of the output Q at the connection point between the collector of transistor 3 becomes H, and the output level of the output at the connection point between the emitter of transistor 3 and the collector of transistor 14 becomes L.

When the level of the differential pulse returns to H-, the transistor 22
Since the base potential of transistor 21 becomes low,
is turned on and transistor 22 is turned off. Therefore, the potential of the collector of transistor 21 decreases, the charge stored in capacitor 29 is discharged, and the level of the reset input supplied to the base of transistor 6 decreases as shown in FIG. 3B.

Before the level of the reset input supplied to the base of transistor 6 falls to L, input terminal 4
When the differential pulse is supplied again from , the level L- of this pulse is lower than the output level L, so the transistor 21 is turned off and the transistor 2
2 turns on. As a result, the output level of the transistor 21 increases, and the capacitor 29 is charged with electric charge.

When the level of the differential pulse returns to H-, the collector potential of the transistor 21 decreases again, the charge stored in the capacitor 29 is discharged, and the voltage supplied to the base of the transistor 6 decreases.

When the level of the voltage supplied to the base of transistor 6 falls below L, the flip-flop is reset, and the output level of the output Q at the connection point between the emitter of transistor 8 and the collector of transistor 18 becomes L, and the output level of the output Q at the connection point between the emitter of transistor 8 and the collector of transistor 18 becomes L. The output level of the output at the connection point of the 18 collectors becomes H, and a pulse with a constant width is output to the output terminal 3.
2 and 33.

The pulse width output from the above-mentioned retriggerable monostable multivibrator is determined as follows.

If the potential difference between the low level output level L of the flip-flop output and the high level output level H- of the reset input is ΔV, the potential difference ΔV is as follows.
The base voltage of the transistor for constant current source is VB,
The resistance values of resistors 9, 10, and 25 are R1, the resistance value of resistor 26 is R1/2, the resistance value of resistor 31 is R3,
Letting the capacitance of the capacitor 29 be CL, ΔV=(VB-VBE)R1/R2-(VB-VBE)(R1/2)/R2=(VB-VBE)(R1/2)/R2. When VB-VBE=VB', ΔV is expressed as ΔV=VB'×(R1/2)/R2... On the other hand, the potential of the reset input R supplied to the base of the transistor 6 is
The pulse width τ is determined by the current IL flowing through 9, and the pulse width τ is τ=(CL/IL)ΔV... The current IL is a resistor 3 connected externally from the board.
It is set as 1, and IL=(VB′/R3)... Substituting the equation into the equation, it is shown as τ=CL・R3×(R1/2)/R2... The formula is where the pulse width τ is the base voltage
This shows that it does not depend on VB, but is determined by the ratio of resistance values on the same board, the capacitance of the capacitor 29, and the resistance value R3 of the externally attached resistor 31. The resistance values within the same substrate have little variation, and since the resistance values of the respective resistors change in the same way, the ratio of the resistance values remains approximately constant even if there is a temperature change. Therefore, the pulse width τ changes depending on the capacitance of the capacitor 29 and the resistance value of the resistor 31. Since the resistance value of the externally attached resistor 31 changes little with temperature, the pulse width τ always remains constant even if the temperature changes.

Incidentally, the capacitor 29 may be inserted between the power supply terminal 5 and the emitter of the transistor 27.

(1/2) VL to a binary signal with H and L levels
In order to cause a level shift, the configuration shown in FIG. 4 or 5 may be used.

In FIG. 4, the emitters of transistors 41 and 42 are connected to a ground terminal 50 via a constant current source resistor 43, and input terminals 44 and 45 are derived from the base of transistor 41 and the base of transistor 42, respectively. has been done. The collector of the transistor 41 is connected to one end of a resistor 48 via a resistor 46, the collector of the transistor 42 is connected to one end of a resistor 48 via a resistor 47, and the other end of this resistor 48 is connected to a power supply terminal 49. .

The collector of the transistor 42 is connected to the base of an emitter follower type transistor 51, and the emitter of the transistor 51 is grounded via a resistor 52 and led out as an output terminal 53. Assuming that the values of resistors 46 and 47 are equal to R,
The value of the resistor 48 is (1/2)R. Therefore,
2 of H and L supplied to input terminals 44 and 45
The value signal is converted into a binary signal having H- and L- levels and output to the output terminal 53.

FIG. 5 shows another example of a circuit configuration for performing level conversion similar to that described above. Transistors 41 and 42
A differential amplifier is configured, and transistor 4
The collector output of 2 is supplied to the base of an emitter follower transistor 51. Resistors 52 and 54 are connected between the emitter of this transistor 51 and ground.
A series connection of the resistors 52 and 54 is inserted, and an output terminal 53 is led out from the connection point of the resistors 52 and 54. The resistor 54 is
This is for a constant current source, and if the resistance values of resistors 46, 47, and 52 are made equal, level conversion can be performed by reducing the constant current generated by this resistor 54 to 1/2 of the constant current of the differential amplifier.

〔Effect of the invention〕

According to this invention, the output pulse width is determined by the ratio of the resistance value of the externally attached resistor to the resistance value within the substrate and the capacitance of the capacitor. Since resistors within the same substrate have similar characteristics, the ratio of resistance values remains constant even if temperature changes occur.

Further, when the base voltage VB of the constant current source transistor increases due to temperature fluctuation, the current flowing through the resistor 9 increases, and the L level of the output from the emitter of the transistor 3 decreases. At this time, the discharge current of the capacitor 29 flowing through the resistor 31 also increases, and the slope of the discharge of the capacitor 29 becomes steeper. This causes the reset input to go low quickly to compensate for this output level change.

Therefore, according to the present invention, it is possible to realize a retriggerable monostable multivibrator that is not affected by temperature changes and always outputs pulses of a constant width.

Further, according to the present invention, the reset input is set to H- level by charging the capacitor 29 with the emitter follower transistor 27, so that the charging speed of the capacitor 29 is fast and a differential pulse with a narrow pulse width is used. Retriggerable operation can be performed reliably.

Furthermore, according to the present invention, since the configuration does not require a reference voltage, the same voltage source can be used, the number of elements is small, and power consumption is low.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of an embodiment of this invention, Fig. 2 is a schematic diagram used to explain signal level relationships in an embodiment of this invention, and Fig. 3 is a diagram used to explain the operation of an embodiment of this invention. The waveform diagrams used, FIGS. 4 and 5 are connection diagrams showing one example and another example of the circuit configuration for level shifting applicable to the present invention, and FIG. 6 shows the configuration of a conventional retriggerable monostable multivibrator. 7 is a connection diagram of a conventional retriggerable monostable multivibrator, and FIG. 8 is a waveform diagram used to explain the operation of the conventional retriggerable monostable multivibrator. 1, 6, 22: Differential amplifier transistor,
2, 7, 21: the other transistor of the differential amplifier, 11, 14, 16, 18, 23, 28: constant current transistor, 4: input terminal, 5: power supply terminal, 29: capacitor, 31: resistor, 32,3
3: Output terminal.

Claims (1)

[Claims] 1. A flip-flop circuit comprising a flip-flop circuit and a time constant generation circuit, the flip-flop circuit comprising a first differential transistor in which the emitters of a first transistor and a second transistor are connected to a constant current source. a second differential circuit in which the emitters of the third transistor and the fourth transistor are connected to a constant current source; and the collector of the second transistor and its base are connected, and an emitter follower type fifth transistor in which the base of the transistor and its emitter are connected; and an emitter follower type transistor in which the collector of the fourth transistor is connected to its base and its emitter is connected to the base of the second transistor. a sixth transistor, a set input signal is supplied to the base of the first transistor, and a reset input signal is supplied to the base of the third transistor; The reset input signal is a binary signal at a first level, the signal supplied to the base of the second transistor and the base of the fourth transistor is a binary signal at a second level, and the reset input signal is a binary signal at a first level. The binary signal at the level of and the binary signal at the second level have the same logical amplitude, and the binary signal at the first level has a logical amplitude which is equal to that of the binary signal at the second level. Roughly 1/
The time constant generating circuit includes a third differential circuit in which the emitters of the seventh and eighth transistors are connected to a constant current source, and the seventh transistor's emitters are connected to a constant current source. a ninth emitter-follower transistor whose collector and base are connected; a level shift circuit that shifts the amplitude of the output of the emitter-follower ninth transistor in accordance with the first level binary signal; a capacitor connected between the emitter of the ninth transistor and a reference potential point; and a discharging resistor connected in parallel to the capacitor;
A binary signal with a level of is supplied to the base of the eighth transistor.
A binary signal with a level of An input terminal is derived from the emitters of the fifth transistor and the sixth transistor, an output terminal is derived from the emitters of the fifth transistor and the sixth transistor, a pulse signal of a binary signal of a first level is supplied to the input terminal, and the pulse signal is The flip-flop circuit is set, a delayed output from a connection point between the emitter of the ninth transistor and the capacitor is supplied to the base of the third transistor, and the emitter of the ninth transistor is connected to the capacitor. A retriggerable monostable multivibrator in which the flip-flop circuit is reset by a delayed output from a point.