JP3012407B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal level conversion circuit, and more particularly to a level conversion circuit capable of outputting an ECL level from a MOS level input.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional level conversion circuit includes an input terminal 2 for inputting a MOS level and a CMOS inverter (hereinafter referred to as INV) 11, and an INV11.
Connect the output of the base of the NPN transistor to Q ₁ differential amplifier emitter composed of NPN transistors Q _1, Q ₂ connected to the constant current source 4 to GND from the emitter is common to the base of NPN transistor Q ₂ is INV11 output amplitude 1/2 to become a reference voltage source (hereinafter, V _REF) connected to 6, the collector of the NPN transistor Q ₂ is connected to the power supply terminal 1, the collector and a power supply terminal 1 of the NPN transistor Q ₁ is the resistance R ₄ , the intersection of the collector of the NPN transistor Q ₁ and the resistor R ₄ is connected to the base of the NPN transistor Q ₃ , the collector is connected to the power supply terminal 1, and the constant current source 5 is connected between the emitter and GND. , Said N
Has been a structure in which the emitter of the PN transistor Q ₃ and the output terminal.

[0003]

The operation of the conventional level conversion circuit will be described with reference to FIGS. When the input voltage shown in FIG. 3 is applied to the input terminal 2 in FIG. 2, the output of INV11 outputs the inverted input as shown in FIG.

[0004] The output is the NPN transistors Q ₁ , Q ₂
Of the transistor Q ₂
Since the base is V _{R EF} 6, which is set to 1/2 of INV11 logical amplitude is connected, NPN transistor Q ₁ is when the output amplitude of INV11 and V _OUT 1, V _OUT
1> V _REF 6 turns on transistor Q ₁ , V _OUT 1 <V _REF
Transistor Q ₁ is turned OFF at 6.

Accordingly, when the current of the constant current source 4 and I _0, the collector current I _C1 of the transistor Q ₁ is, transistor to Q ₁ ON at I _C1 = I _0, the transistor Q ₁ OF
Since I _{C 1} = 0 at the time of F, both ends of the resistor R ₄ are connected as shown in FIG.
The output of the input voltage and the phase, as shown in the collector voltage of the transistor Q ₁ is obtained. Moreover, the high level V _H of the collector voltage of the transistor Q _1, when a low level and V _L, respectively represented by the following formula.

V _H = V _CC (1) _{V L = V CC -R 4 ×} I C1 (2) equation However, V _CC = supply voltage

Further, when the amplitude of the collector voltage of the transistor Q ₁ and _{V C1, V C1 = V H} -V L (3) the formula.

Since V _C1 is output through the transistor Q _{3 of the} emitter follower, the output voltage also has the same phase as the input voltage as shown in FIG.

Further, assuming that the output voltage is V _{OUT (H)} on the high side and V _{OUT ( L)} on the low side, V _{OUT (H)} = V _H −V _BE Q ₃ (4) Equation V _{OUT (L)} = V _L -V _BE Q ₃ Equation (5) V _BE Q ₃ = KT / q ln I ₅ / I _S Equation (6) is obtained. Where K = Boltzmann's constant, q = load of electrons,
T = absolute temperature, I _S = transistor Q ₃ base-emitter saturation current, I ₅ = current value of constant current source 5.

Assuming that the amplitude of the output voltage is V _OUT , V _OUT = V _{OUT (H)} −V _{OUT (L)} · V _H −V _L Equation (7) is obtained, and the amplitude of the output terminal becomes equal to V _C1 .

[0011] When the input voltage is Hairebereru, since the transistor Q ₁ is in the ON state, the transistor Q ₁ at that time
Since the collector voltage V _C1 is expressed by equation (2), I ₀
Assuming that = 1 mA and R ₄ = 300Ω, V _C1 = 4.7 V.

Meanwhile, the base voltage at this time the transistor Q ₁ (V _B1), the amplitude of INV11 is for swing from V _{C C} until GND, a V _B1 = V _CC.

Therefore, V _B1 and V _{B1 of the} transistor Q _1
C1 is V _B1 > V _C1 and the base potential is lower than the collector voltage. That is, it is saturated.

The common emitter DC current gain of a transistor is usually referred to as hFE. However, when the transistor is saturated, the hFE is reduced to 1/10 or less of the saturated state. In the output voltage waveform of FIG.
It rises to 0%. Rise time (hereinafter tr),
The time during which the amplitude falls from 90% to 10% is called fall time (hereinafter referred to as tf) and is represented by the following equation.

[0015]

(Equation 1)

[0016]

(Equation 2)

[0017]

(Equation 3)

Here, hFR in the active state is 50, hFE in the saturated state is hFE ′ = hFR × 0.10, f _T = 10
Assuming 0 MHz, T _B = 40 ns from equation (10). Now, assuming that I ₀ = 1 mA, (8),
From equation (9), tr = 88 ns and tf = 88 ns.

One cycle T _IN of the input signal is represented by T _IN = 1 / f _IN f _IN : input frequency. As shown in FIG. 4, f _IN is low and T _IN ≧
Under the conditions of tr and tf, the output voltage is normally output.
f _IN increases. When T _IN ≦ 2tr, tf, the output voltage waveform becomes a triangular wave, and the output is not performed normally.

Assuming that tr and tf = 88 ns, in the case of the conventional circuit, the input frequency f _IN becomes f _IN = 1 / (2 × tr) = 5.6 MHz (10 ′). However, there was a drawback that the waveform became a triangular wave.

An object of the present invention is to provide a level conversion circuit in which the upper limit of the input frequency is increased.

[0022]

In order to achieve the above object, a level conversion circuit according to the present invention comprises an inverted signal of an input signal.
A first CMOS inverter for outputting a signal;
CMOS inverter outputting non-inverted signal of signal
And a differential amplifier, and converts the MOS level signal into an ECL signal.
A level conversion circuit for converting the first C
An output terminal of a MOS inverter and the second CMOS input terminal;
The first, second, and third resistances are sequentially connected to the output terminal of the inverter.
Is next serially connected, an inverting input terminal and noninverting of the differential amplifier
Input terminals are connected to one end and the other end of the second resistor, respectively.
It is connected and outputs an ECL level signal.

[0023]

An ECL level signal is output using an inverted signal and a non-inverted signal output from two CMOS inverters connected in series. As a result, the output waveform is output as a square wave, and the limit input frequency can be increased.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, a CMOS inverter (hereinafter referred to as INV) 11 and a CMOS inverter (hereinafter referred to as INV) are shown.
INV) is connected in series, and INV11 is
The input terminal 2 of the S level signal, and the output of INV11 and I
Resistors R ₁ , R ₂ , and R ₃ are connected in series between the intersection of the inputs of the NV 12 and the output of the INV 12.

Furthermore, both ends of the resistor R ₂ to the emitter of NPN transistor Q _1, Q ₂ and the common, the common emitter and G
Connected to the respective bases of the differential amplifier connected to the constant current source 4 between the ND, the collector of the transistor Q ₂ is the power supply terminal 1, the collector of the transistor Q ₁ is connected to the power supply terminal 1 via a resistor R _1, resistor R ₁ and NPN transistor Q
The base of the NPN transistor Q ₃ is connected to one of the intersection,
The collector is connected to the power supply terminal 1 and the emitter is connected to GND via the constant current source 5. The emitter of the NPN transistor Q ₃ is used as the output terminal 3.

When the input voltage shown in FIG. 5 is applied to the input terminal 2 of FIG. 1, the output of the INV 11 outputs the inverted input to the inverted input terminal 6 as shown in FIG. Its output is INV
As shown in FIG. 3, the output of INV 12 is output in the same phase as the input and is output to the non-inverting input terminal 7.

Next, because it is connected in series at the output of INV11 and INV12 resistance R _1, R _2, R _3, resistors R _1,
Voltage across R ₃ is equal to the output amplitude level of INV11, INV12. Since the amplitude of the CMOS INV swings from the power supply terminal voltage (hereinafter, V _CC ) to GND, the resistance of the resistor R ₁
And the potential difference of R ₃ is the V _CC.

[0029] The voltage generated across the resistor R ₂ and V _R2, the high level V _R2H, when a low level and V _R2L,
Each is represented by the following equation.

[0030] _{V R2H = V CC × (R} 2 + R 3) / (R 1 + R 2 + R 3) (11) formula _{V R2L = V CC × R 3} / (R 1 + R 2 + R 3) (12) formula V _{R2 = V R2H -V R2L = R} 2 / (R 1 + R 2 + R 3) (13) equation

From the equations (11) to (13), V _CC = 5.0
_{V, R 1 = 20K, R} 2 = 10K, When R ₃ = 20K, a _{V R2H = 3V, V R2L =} 2V, V R2 = 1V.

On the other hand, the differential amplifier comprising NPN transistors Q ₁ and Q ₂ , constant current source 4 and resistor R ₄ has the transistor Q ₁ turned on at VR _2H and VI when the constant current source 4 is I _0.
C1 = I ₀ V transistor Q ₁ is OFF at _R2L, V I _C1
As a result, a signal having the same phase as the input voltage is output from the collector voltage V _C1 of the transistor Q ₁ as shown in FIG.

Assuming that the high level of the collector voltage of the transistor Q ₁ is V _H and the low level is V _L , the following equations are respectively given. V _H = V _CC (14) _{V L = V CC -R 4 ×} I 0 (15) In addition, when the amplitude of the collector voltage for Q ₁ and V _C1, represented by _{V C1 = V H -V L (} 16) equation. V _C1 is an emitter follower transistor Q
₃ , the output voltage is also in phase with the input voltage as shown in FIG.

Further, the output voltage, the high-side V _{OUT (H),} when a row side is _{V OUT (L), V OUT} (H) = V H -V BE Q 3 (17) formula V _{OUT (L )} = V _L -V _BE Q ₃ (18) V _BE Q ₃ = KT / q ln I ₅ / I _S Equation (19) is obtained. Where K = Boltzmann's constant, q = load of electrons,
T = absolute temperature, I _s = Q ₃ base-emitter saturation current, I
₅ = current value of constant current source 5

The amplitude of the output voltage is V_OUTThen, V_OUT= V_{OUT (H)}-V_{OUT (L)}= V_H-V_L  (20) where the amplitude of the output terminal is V_C1Is equal to

[0036] When the V _R2H, NPN transistor Q ₁ is ON
However, the voltage at that time is _VR2H = 3.0 V according to the equation (1).
Next, this is of the NPN transistor Q ₁ base voltage V
_B1 .

On the other hand, since the collector voltage V _C1 of the NPN transistor Q ₁ is Q ₁ is in the ON state, V _C1 is (15)
Where I ₀ = 1 mA, R ₄ = 30, as in the prior art.
When 0 .OMEGA, the _{V C1 = V CC -R 4 ×} I 0 = 5V-300Ω × 1mA = 4.7V. V _B1 and V _C1 of the transistor Q ₁ are V _B1 <V _C1
Next, the transistor Q ₁ is not to become saturated in a V _B1> V _C1 as in the conventional example. Therefore, hFE does not become 1/10 or less unlike the conventional example.

Next, using equations (8) to (10), t
When r and tf are the same as those in the conventional example, hFE = 50, f _T =
Assuming that the calculation is performed at 100 MHz and I ₀ = 1 mA, tr = 32 ps from the equation (8) and tf = 7 ps from the equation (9).
2 ps.

Next, when the limit input frequency f _{IN MAX at} which the output waveform in the case of the present invention becomes a square wave and the normal output is performed is calculated, f _{IN MAX} = 1 / (2 × tr) = 7 GHz.

[0040]

As described above, the use of the circuit of the present invention has an effect that the limit input frequency f _{IN MAX} can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a diagram showing operation waveforms of a conventional circuit.

FIG. 4 is a diagram showing operation waveforms of a conventional circuit.

FIG. 5 is a diagram showing operation waveforms of the present invention.

[Explanation of symbols]

First power supply terminal 2 input terminals 3 output terminal 4 the constant current source 5 constant-current source 6 inverting input terminal 7 a non-inverting input terminal 11, 12 CMOS inverter (INV) Q ₁ ~Q ₃ NPN transistor R ₁ to R ₄ the resistance

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (1)

(57) [Claims] 1. A first C for outputting an inverted signal of an input signal.
Outputs a MOS inverter and a non-inverted signal of the input signal
A second CMOS inverter and a differential amplifier.
To convert the MOS level signal to the ECL level.
A conversion circuit, comprising: an output terminal of the first CMOS inverter;
A first, a second, and a second
3 are serially connected in series, and the inverting input terminal and the non-inverting input terminal of the differential amplifier
ECL connected to one end and the other end of the second resistor, respectively.
A level conversion circuit for outputting a level signal.