JP2789911B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit,
In particular, it relates to a circuit for converting a logic level of an emitter-coupled logic (ECL) circuit to another logic level.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of an example of a level conversion circuit used for level conversion of a signal voltage from an ECL circuit to a transistor / transistor / logic (TTL) circuit. Inputting the input voltage V1 and the inverted input voltage V2,
This level conversion circuit for supplying the level conversion output voltage V3 to the inverter input terminal 7 of the L inverter 6 has a base connected to the input terminal 1 and an inverting input terminal 2 respectively, a collector connected to the VC power supply terminal 4 and an emitter connected respectively. Input and inverting input transistors Q1 and Q2 connected to the resistor R1 and one end of the resistor R of the resistor section 9a;
A diode resistor 11 connected in series with the anode end connected to the other end, an anode of the current input diode D1 is connected to the cathode of the diode resistor 11, and a collector of the current output transistor Q3 is connected to the cathode of the diode D2 of the resistor 9a. It has a current mirror circuit 10 in which the cathode of the diode D1 and the emitter of the output transistor Q3 are both connected to the ground terminal 5.

The TTL inverter 6 of the next stage inputs the level conversion output voltage V3 to the inverter input terminal 7, performs logical processing on the Schottky transistor Q4 and the like, and outputs the inverter output voltage V8 from the inverter output terminal 8.

Next, the operation of the circuit shown in FIG. 3 will be described with reference to FIG. Here, the potentials of the terminals 4 and 5 are
C and GND, the high level of the voltages V1 and V2 input to the input terminal 1 and the inverting input terminal 2 is VC, and the low level is (VC-W), that is, the ECL of the circuit preceding the level conversion circuit.
The logical amplitude of the output voltage is W.

When the input voltage V1 up to time t1 is a high level VC, a high level current input to the diode D1 of the current mirror circuit 10 through the input transistor Q1, the resistor R1 and the diode resistor 11 is set to IH. ,
IH is (VC-4VF) / R1. Here, it is assumed that the base-emitter voltage of the transistor Q1 and the forward voltage drop voltage of each diode are all the same value VF. At this time, the inverting input transistor Q2 and the resistor 9a
Has the same value as the input current IH.

Therefore, the voltage V3 of the level conversion output terminal 3
Becomes the low level conversion output voltage VOL, and the voltage VOL
Since the inverted input voltage V2 is a low level (VC-W), the voltage VOL is (VC-W) -VF-
R.IH-VF = [1- (R / R1)] VC-W +
[(4R / R1) -2] VF.

Next, at time t2, the input voltages V1, V
2 is inverted from the state described above, and when the input voltage V1 is as low as (VC-W) and the inverted input voltage V2 is at VC, the low-level input current IL of the current mirror circuit 10 becomes [(VC-W)- 4VF] / R1. Similarly to the above, the voltage V3 of the level conversion output terminal 3 at this time becomes the high level conversion output voltage VOH, and the voltage VOH is (V
C-VF-R.IL-VF) = [1- (R / R1)] V
C + (R / R1) W + [(4R / R1) -2] VF.

Normally, the diode voltage VF is 0.8
[V], a typical logic amplitude W of ECL is 0.8 [V],
The power supply voltage VC is 5.0 [V], and when the resistors R and R1 are set to the same value, the above-mentioned low-level conversion output voltage VOL becomes 0.8 [V] and the high-level conversion output voltage V
OH becomes 2.4 [V], and these values conform to the input standard of the TTL signal voltage, and are suitable for driving the TTL inverter 6 in the next stage.

[0009]

In the above-described conventional level conversion circuit, if the frequency of the input voltage is high and the voltage changes steeply, the operation of the current mirror circuit cannot be followed. Since the low-level converted output voltage rises above the design logical value, the duty ratio of the level-converted output voltage fluctuates, and the next-stage TTL circuit may malfunction.

When a general circuit constant is used, the high-level conversion output voltage is only about 2.4 [V], so that the high-level threshold voltage other than the TTL circuit is higher, for example, a CMOS inverter. The circuit can no longer be driven.

[0011]

A level conversion circuit according to the present invention has a base connected to an input terminal and an inverting input terminal, a collector connected to a higher power supply terminal, and an emulator connected to one end of a resistor and one end of a resistor, respectively. Input and inverting input transistors, a voltage dividing resistor connected between the other end of the resistor and a ground terminal via a voltage dividing point N, a base connected to the voltage dividing point, and an emitter connected to the ground terminal. And a collector including an output transistor connected to the other end of the resistor section via a level conversion output terminal.

[0012]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. The level conversion circuit of the present embodiment eliminates the diode resistor 11 and the diode D2 of the resistor 9a of the conventional level conversion circuit shown in FIG. 3, and replaces the input diode D1 of the current mirror circuit 10 with a voltage dividing resistor R2. Output transistor Q
3 is supplied with the voltage at the voltage dividing point N. The TTL inverter 6 is the same as the conventional one.

Next, the operation of the circuit of FIG. 1 will be described with reference to the voltage waveform diagram of FIG. As described in the conventional example shown in FIG. 3, the voltages of the power supply terminals 4 and 5 are changed to VC and G, respectively.
Suppose that the high level of the input voltage V1 and the inverted input voltage V2 is VC, and the low level thereof is (VC-W), that is, the logic amplitude of the ECL of the preceding circuit is W.

First, before the time point t1, when the input voltage V1 is at the high level and at the level VC, the high input current IH of the current I1 flowing to the input transistor Q1 side is (VC-VF) / (R1 +
R2). In this case, the inverting input transistor Q2
The current I2 flowing through the base of the output transistor Q3
The voltage VB3 is determined by the emitter voltage VB3, and the voltage VB3 is a product of the high input current IH and the voltage dividing resistor R2.

When the current I2 flows through the resistor R, the inverted input voltage (VC-W), the base-emitter voltage VF of the inverting input transistor Q2, the voltage drop VR of the resistor R, and the PN junction current formula are used to obtain a level conversion output. The low-level conversion output voltage VL of the voltage V3 is obtained by Expression (2). Also,
When the above-described input / inverted input voltages V1 and V2 are inverted at the time point t2, the high-level converted output voltage VH is obtained by Expression (3).

[0016]

(Equation 1)

As described above, in the level conversion circuit of the present embodiment, the ECL voltage level whose high level is VC and the low level is (VC-W) is expressed by the equation (3).
The conversion voltage VL is a value represented by the following expression and the low level is expressed by the equation (2)
Is converted to the level for the TTL voltage of the value indicated by.

Next, as an example, as described in the aforementioned conventional example, all the diode forward voltages VF are set to 0.8.
[V], assuming that the typical logic amplitude W of ECL is 0.8 [V] and the power supply voltage VC is 5.0 [V], the saturation current IS of the PN junction is a general value obtained on an integrated circuit. And is assumed to be 3. [10 minus the 18th power] amperes. The values of the resistors R, R1 and R2 are set to 4 [KΩ] and 1
When 5 [KΩ] and 15 [KΩ] are set, Equation (2),
From (3), VL is -23.1 [V] and VH is 4.2.
[V] is calculated.

Here, the calculated value of VL is a negative value, but does not actually fall below GND. Therefore, in the case of this example, a level converted output voltage V3 having a high level converted output voltage VH of 4.2 [V] and a low level converted output voltage VL of 0 [V] is obtained. Therefore, T
It is possible to drive at a high frequency by connecting not only a TL circuit but also a CMOS circuit.

Here, if the resistor 9 of the first embodiment shown in FIG. 1 is replaced by the same resistor 9a as in the prior art, only VF can be suppressed so that the high level voltage does not become too high. If a capacitor is connected in parallel with the resistor R of the resistor section 9, the rising and falling edges of the converted output voltage V3 can be accelerated.

[0021]

As described above, according to the present invention, in the level conversion circuit for adjusting the level between logic circuits of different levels, the high and low levels of the level conversion output voltage are respectively reduced to the lower power supply voltage and the ground potential. , Which has the effect of improving the high-frequency response.

Also, there is an effect that a circuit such as a CMOS circuit having a higher high-level threshold voltage other than the TTL circuit can be driven.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform chart of each voltage for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of an example of a conventional level conversion circuit.

FIG. 4 is a waveform chart of each signal for explaining the operation of the circuit of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Inverting input terminal 3 Level conversion output terminal 4 VC power supply terminal 5 Grounding terminal 6 TTL inverter 7 Inverter input terminal 8 Inverter output terminal 9 Resistor part N Voltage dividing point Q1 Input transistor Q2 Inverting input transistor Q3 Output transistor R1, R Resistance R2 Voltage dividing resistor V1 Input voltage V2 Inverting input voltage V3 Level conversion output voltage VC Power supply voltage GND Ground potential

Claims (2)

(57) [Claims] An input and inverting input transistor having a base connected to an input terminal and an inverting input terminal, a collector connected to a higher power supply terminal, and an emitter connected to one end of a resistor and one end of a resistor, respectively; A voltage dividing resistor connected between the other end of the resistor and a ground terminal via N; a base connected to the voltage dividing point; an emitter connected to the ground terminal; and a collector connected via a level conversion output terminal. An output transistor connected to the other end of the unit. 2. The level conversion circuit according to claim 1, wherein the resistor section is a resistor, a series circuit of a resistor and a diode, or a parallel circuit of a resistor and a capacitor.