JP2936906B2 - Voltage comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage comparison circuit, and more particularly to a voltage comparison circuit having a hysteresis function requiring low power consumption.

[0002]

2. Description of the Related Art A conventional voltage comparison circuit of this type is shown in FIG.
As shown in PNP transistors 1 and 8 to 1
0 and NPN transistors 2, 11 to 13, 16, 1
7, 19, 20 and 22 and resistors 3, 5, 6, 14,
15, 18 and 23, constant current sources 4 and 24, and a reference voltage source 7.

In FIG. 3, a constant current source 1 having one connected to a power source, resistors 5 and 6 and a reference voltage source 7 connected in series between the constant current source 1 and a ground point, 6
Transistor 1 whose collector is connected to the connection point of
3, a resistor 15 connected between the emitter of the NPN transistor 13 and the ground point, a PNP transistor 8 having an emitter connected to the power supply and a collector connected to the emitter of the NPN transistor 13, The PNP transistor 9 constituting the current mirror circuit constitutes a reference voltage generating circuit having a circuit for generating hysteresis. The collector is connected to the power supply, and the base is connected to the connection point between the resistors 4 and 5. NPN transistor 11 and base is NPN
An NPN transistor 12 connected to the emitter of the transistor 11, an NPN transistor 16 having an emitter connected to the emitter of the NPN transistor 12, a collector connected to the power supply, and an emitter connected to the NPN transistor 16
And a NPN transistor 19 whose base is connected to the input terminal 51, constitutes a comparison circuit for comparing the level of the input pulse signal with the reference voltage generated in the reference voltage generation circuit. .

The collector of NPN transistor 16 is connected to the input of a current mirror circuit composed of PNP transistors 1 and 10.
The current mirror circuit constituted by the PNP transistors 1 and 10 forms an output circuit for outputting the result of comparison by the comparison circuit. An NPN transistor 17 having a collector connected to the common emitter of the NPN transistors 12 and 16 and a resistor 18 connected between the emitter of the NPN transistor 17 and the ground.
NPN transistors 2 and 22 and resistors 3 and 23, which constitute a current mirror circuit with NPN transistor 17 and resistor 18, and collectors are connected to the power supply and emitters are NPN transistors 17 and 22.
An NPN transistor 20 connected to the common base of
Power supply and base of NPN transistor 20 and NPN
A constant current supply circuit that supplies an operating current is configured by a constant current source 24 connected between the transistor 22 and the collector of the transistor 22. FIG. 2 is an operation signal waveform diagram in the conventional example and an embodiment of the present invention described later.

Next, the operation of the conventional example shown in FIG. 3 will be described.

Now, the voltage of the pulse signal input to the input terminal 51 is V _A (see FIG. 4), the output voltage of the reference voltage generation circuit is V _D , the output voltage of the output terminal 52 is V _B , _Assuming that the output voltage of the voltage source 7 is V _REF , the output voltage V _D of the reference voltage generation circuit is represented by the following equation.

V _D = V _REF + R ₅ × I ₁ + R ₆ (I ₁ −I ₁₃ ) (1) In the above formula, R ₅ and R ₆ are resistance values of resistors 5 and 6, respectively, and current I ₁₃ is a collector current flowing through the NPN transistor 13, and current I ₁ is a current value of the constant current source 4.

In FIG. 2, between times T _{1 and} T ₂ , V _A <V _D , and the collector current I ₁₇ of the NPN transistor 17, which is the operating current of the comparison circuit, is all the NPN transistor 12. Is supplied to the resistor 15 connected to the emitter of the NPN transistor 13 via the current mirror circuit PNP transistors 8 and 9. Now, _assuming that the current mirror ratio of the current mirror circuit is K, the forward voltage of the NPN transistor 13 is V _BE13 , N
The collector current of the PN transistor 17 is set to I ₁₇ ,
When the resistance value is R _15, the value of K × I ₁₇ × R ₁₅ is equal to or sufficiently large level value than the forward voltage V _BE13 of the NPN transistor 13, NPN transistor 13 becomes non-conductive. That is, in the equation (1), I ₁₃ = 0, and the output voltage V _D of the reference voltage generation circuit during the time T _{1 to} T ₂ is V _D = V _REF + (R ₅ + R ₆ ) × I ₁ .

Further, no current is supplied to the NPN transistor 16, and therefore, a PN which forms a current mirror circuit is not provided.
Since no current is supplied to the output terminal 52 via the P transistors 1 and 10, the potential V _B of the output terminal 52 becomes
Assuming that the saturation voltage between the collector and the emitter of the NPN transistor 2 is V _CE2 , the voltage value is represented by the following equation, and is as shown in FIG.

[0010] _{V B = V CE2 ......................................................... (2} ) Next, in the time axis shown in FIG. 2, time T ₂ through T ₃
, V _A > V _D , and the collector current I of the NPN transistor 17, which is the operating current of the comparison circuit.
_C17 is not supplied to the NPN transistor 12, so that no current is supplied to the resistor 15 from the PNP transistors 8 and 9 forming the current mirror circuit. Thus, the NPN transistor 13 and the resistor 15 and the NP
A current is supplied from a current mirror circuit formed by the N transistor 22 and the resistor 23. That is, FIG.
As shown, the output voltage V _D between the time T ₂ through T _{3 is, V D = V REF + R} 5 × I 1 + R 6 (I 1 -I
_C13 ). The NPN transistor 16 has I
_C17 is all supplied and forms a current mirror circuit.
Current is supplied to the NP transistor 1 and the output terminal 52 via a 10, the output voltage V _B is as shown in the following equation.

V _B = V _CC −V _CE1 (3) However, as a condition for _satisfying the above expression, the value of K ₁ × I _C17 is
It is required to take a value sufficiently larger than the current value of I _C2 . Here, K ₁ is the current mirror ratio of the current mirror circuit formed by PNP transistors 1 and 10, and I _C17 and I _C2 are the collector current of NPN transistor 17 and the collector current of NPN transistor 2, respectively.

[0012] Incidentally, as shown in FIG. 2, time T ₁ ~
The output voltage V _D between T _2, the value of the difference voltage [Delta] V _D between the output voltage V _D between the time T ₂ ~T _3, NPN
The collector current of the transistor 13 is given by the following equation as I _C13 , and represents the hysteresis voltage in the conventional example.

ΔV _D = R ₆ × I _C13 …………………………… (4)

In [0008] Conventional comparator circuit described above, in FIG. 1, with respect to the difference voltage [Delta] V _i at the input pulse signal at the input terminal 51,
The potential V _p that propagates and appears at the node P set at the base input of the NPN transistor 11 is represented by the following equation.

[0014]

The symbols in the above equation are as follows.

Z _REF : impedance of the reference voltage generation circuit Z _C1 : AC equivalent impedance of NPN transistors 16 and 19 Z _C2 : AC equivalent impedance of NPN transistors 11 and 12 Z _C3 : AC equivalent impedance of NPN transistor 17 _R : Equivalent impedance viewed from the base of the NPN transistor 17 In response to the application of the input pulse signal (voltage V _A ), the input pulse signal becomes NPN transistors 19, 16, 12 and in order to be AC-propagate via 11, as shown in FIG. 4, whiskers 101 and 102 are generated in the switching despite th output voltage V _D of the reference voltage generating circuit, that is a factor of noise There are drawbacks.

[0017]

A voltage comparison circuit according to the present invention comprises: a reference voltage generation circuit having hysteresis characteristics; and a comparison circuit for comparing a reference voltage output from the reference voltage generation circuit with a voltage level of an input pulse signal. And a constant current supply circuit that supplies an operation current to the reference voltage generation circuit, the comparison circuit, and the output circuit. The current supply circuit includes a resistor connected between a common base of a transistor pair forming a current mirror circuit and a ground point.

[0018]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, the present embodiment has an input terminal 51.
And the PNP transistor 1 corresponding to the output terminal 52
And 8 to 10 and NPN transistors 2, 11 to 1
3, 16, 17, 19, 20 and 22 and resistance 3,
5, 6, 14, 15, 18, 21 and 23, constant current sources 4 and 24, and a reference voltage source 7.

As shown in FIG. 1, the configuration of the present embodiment is basically similar to that of the above-described conventional example, except that a resistor 21 is newly added. That is, a constant current source 1 having one connected to a power supply, resistors 5, 6 and a reference voltage source 7 connected in series between the constant current source 1 and a ground point, and a connection point between the resistors 5 and 6 NPN transistor 13 to which a collector is connected, NPN transistor 13
And a PNP transistor 8 having an emitter connected to the power supply and a collector connected to the emitter of the NPN transistor 13.
The PNP transistor 8 and a PNP transistor 9 forming a current mirror circuit constitute a reference voltage generating circuit having a circuit for generating hysteresis. The collector is connected to a power supply, and the base is connected to a resistor 4. , An NPN transistor 12 having a base connected to the emitter of the NPN transistor 11, and an emitter having an NP
NPN transistor 16 connected to the emitter of N transistor 12, NPN transistor 19 having the collector connected to the power supply, the emitter connected to the base of NPN transistor 16, and the base connected to input terminal 51.
Thus, a comparison circuit for comparing the level of the input pulse signal with the reference voltage generated in the reference voltage generation circuit is configured.

The collector of the NPN transistor 16 is connected to the input of a current mirror circuit composed of the PNP transistors 1 and 10.
The current mirror circuit constituted by the PNP transistors 1 and 10 forms an output circuit for outputting the result of comparison by the comparison circuit. An NPN transistor 17 having a collector connected to the common emitter of the NPN transistors 12 and 16 and a resistor 18 connected between the emitter of the NPN transistor 17 and the ground.
NPN transistors 2 and 22 and resistors 3 and 23, which constitute a current mirror circuit with NPN transistor 17 and resistor 18, and collectors are connected to the power supply and emitters are NPN transistors 17 and 22.
An NPN transistor 20 connected to the common base of
A resistor 21 additionally connected between the common base of the NPN transistors 17 and 22 and the ground point;
A constant current supply circuit that supplies an operating current is configured by a constant current source 24 connected between the base of the PN transistor 20 and the collector of the NPN transistor 22. FIG. 2 shows operation signal waveform diagrams in the above-described conventional example and this embodiment.

The operation of the present embodiment is basically the same as that of the above-described conventional example, and the output voltage V of the reference voltage generation circuit corresponding to the voltage V _{A of the} pulse signal input to the input terminal 51. _D is given by the above equation (1), and the potential V _B of the output terminal 52 is similarly given by the above equation (2), where the saturation voltage between the collector and the emitter of the NPN transistor 2 is V _CE2. Can be Further, in a period of time T ₂ through T _3, the output voltage V _B is given by the equation (3), the output voltage V _D between the time T ₁ through T _2, during the time T ₂ through T ₃ difference voltage [Delta] V _D between the output voltage V _D in
Is also shown in the above equation (4).
Accordingly, the description of the operation of the present embodiment is the same as that of the conventional example, and thus the description thereof is omitted. However, in the present embodiment, the NPN transistors 13 and 17 included in the current mirror circuit of the constant current supply circuit and The resistor 21 is inserted and connected between the common base 22 and the ground point, thereby suppressing noise caused by "whisker" generated in the conventional example.

That is, the resistor 21 is inserted and connected between the common base of the NPN transistors 13, 17 and 22 included in the constant current supply circuit and the ground point, so that
The equation is expressed as the following equation (6). In the equation (5), by setting the resistance value of the resistor 21 to about several tens kΩ, the reference voltage generating circuit at the time of applying the input pulse signal is set. The level of "whisker" at the switching point of the output voltage is greatly suppressed.

[0024]

The symbols in the above equation are as follows.

Z _REF : Impedance of the reference voltage generating circuit Z _C1 : AC equivalent impedance of NPN transistors 16 and 19 Z _C2 : AC equivalent impedance of NPN transistors 11 and 12 Z _C3 : AC equivalent impedance of NPN transistor 17 _R : equivalent impedance as viewed from the base of the NPN transistor 17 R ₂₁ : resistance value of the resistor 21

As described above, according to the present invention, the input is realized by inserting the resistor 21 between the common base of the NPN transistors 13, 17 and 22 included in the constant current supply circuit and the ground point. There is an effect that noise caused by "whisker" generated at a switching point of the output voltage of the reference voltage generating circuit when a pulse signal is applied can be largely suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing operation signal waveforms in the present embodiment and a conventional example.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing operation signal waveforms in a conventional example.

[Explanation of symbols]

1, 8 to 10 PNP transistors 2, 11 to 13, 16, 17, 19, 20, 22N
PN transistor 3, 5, 6, 14, 15, 18, 21, 23 Resistance 4, 24 Constant current source 7 Reference voltage source

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) G01R 19/00-19/32 H03K 5/08-5/12 H03K 3/023

Claims (1)

(57) [Claims] A reference voltage generating circuit having hysteresis characteristics; a comparing circuit comparing a reference voltage output from the reference voltage generating circuit with a voltage level of an input pulse signal;
A voltage comparison circuit comprising: an output circuit that outputs a comparison result by the comparison circuit to the outside; and a constant current supply circuit that supplies an operation current to the reference voltage generation circuit, the comparison circuit, and the output circuit. A voltage comparison circuit comprising a resistor connected between a common base of a pair of transistors forming a current mirror circuit included in the circuit and a ground point.