JPH06230149A - Timer circuit - Google Patents

Abstract

PURPOSE:To provide a timer circuit in which a PNP transistor and an NPN transistor are turned ON by providing a trigger pulse when the output terminal of the timer is High and the output can be reset by providing the trigger pulse again when erroneous operation is found. CONSTITUTION:When a power supply 10 is turned ON, a timer IC 9 is actuated and when a user provides a trigger signal to a trigger input terminal 2, the IC 9 begins to measure the time. When a user notices erroneous operation and provides a trigger pulse again during High interval at an output terminal 3, a PNP transistor 20 is turned ON and an NPN transistor 22 is also turned ON. When a capacitor 15 is discharged and the potential thereof drops below the reset potential of the IC 9, signal at the terminal 3 goes Low. When the trigger pulse disappears, the transistors 20, 22 are turned OFF. Consequently, the capacitor 15 is recharged to elevate the potential at a reset input terminal 4 thus bringing about the initial state for receiving the trigger pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer circuit using a timer IC.

[0002]

2. Description of the Related Art A conventional timer circuit has a timer IC 9 called a 555 type having terminals 1 to 8 as shown in FIG.
It is equipped with. The above-mentioned terminals monitor the added signal, the ground terminal 1, the trigger input terminal 2, the positive logic output terminal 3, the reset input terminal 4, the comparison signal terminal 5 for outputting the comparison reference voltage generated inside the timer IC 9. A threshold input terminal 6 that outputs a signal when the comparison reference voltage is reached, a discharge terminal 7 that discharges the electric charge of the capacitor, and an input terminal 8 that inputs the circuit power supply. And 10 is a power supply. Reference numerals 11 and 12 are capacitors and resistors that form a CR time constant circuit, and those corresponding to the set time are used. Reference numeral 13 is a capacitor that prevents noise from being superimposed on the comparison signal terminal 5. Reference numerals 14 and 15 are resistors and capacitors connected to the reset input terminal 4 and are connected to the power source 1
No erroneous output is output when 0 is input.

The operation of this structure will be described below with reference to FIG. Reference characters a, b, and c represent voltage waveforms of the trigger input terminal 2, the threshold input terminal 6, and the output terminal 3, respectively. When a pulse signal of negative logic as shown in a is applied to the trigger input terminal 2, the threshold input terminal 6 becomes b
The change in the voltage of the capacitor 11 is monitored as shown in FIG. That is, until the voltage of the capacitor 11 that changes according to the time constant of the capacitor 11 and the resistor 12 reaches the comparison reference voltage that is ⅔ of the voltage V _CC of the power supply 10, the output terminal 3 as shown in c Is outputting a positive logic pulse.

[0004]

However, in the conventional structure described above, once the trigger pulse is input, the pulse shown in FIG. 4c is output for the specified time. In other words, there is a problem in that even if it is started by an erroneous operation, it cannot be canceled.

SUMMARY OF THE INVENTION The present invention is intended to solve the problems of such a conventional structure, and an object thereof is to provide a timer circuit capable of resetting the output.

[0006]

In order to achieve the above object, the present invention provides a negative logic trigger input terminal, a positive logic output terminal, and a low output when the input signal is low.
Timer IC with reset input terminal
A resistor connected to the output terminal of the timer IC, a capacitor charged and discharged through the resistor, a diode having an anode connected to the capacitor, a cathode of the diode as an emitter, and a trigger input of the timer IC. A timer including a PNP transistor having a terminal connected to a base via a resistor, an NPN transistor having a collector connected to the base of the PNP transistor via a resistor, a collector connected to a reset input terminal of the timer IC, and an emitter grounded. It is a circuit.

[0007]

The combination of the PNP transistor and the NPN transistor is such that when the trigger pulse is input when the output terminal of the timer IC is High, the two transistors are turned on to reset the timer IC.

[0008]

Embodiments of the present invention will be described below with reference to FIGS. In the present embodiment, the same parts as those of the conventional structure will be designated by the same reference numerals, and the description thereof will be omitted. That is, a reset circuit is added, 16 is a resistor connected to the output terminal 3 of the timer IC 9, 17 is a capacitor charged and discharged through the resistor 16, and 18 is a diode having an anode connected to the capacitor 17. Reference numeral 20 designates the cathode of the diode 18 as the emitter and the trigger input terminal 2 of the timer IC 9 as the resistor 1
9 is a PNP transistor connected to the base via 9. Reference numeral 22 is an NPN transistor in which the collector of the PNP transistor 20 is connected to the base via a resistor 21, the emitter is grounded, and the collector is connected to the reset input terminal 4. Note that 23 and 24 are resistors for preventing malfunction of the transistor due to leakage current.

The operation of this embodiment will be described below with reference to FIG. When the power supply 10 is turned on, the timer IC 9 starts operating. When the user inputs a trigger signal to the trigger input terminal 2 in this state, the timer IC 9 starts measuring a predetermined time and outputs the output terminal 3 as described in the conventional example.
Outputs a pulse signal as described with reference to FIG. That is, the voltage waveforms a and b in the period P of FIG. 2 correspond to the operation of the timer IC 9 described in a and c of FIG. The waveforms c, d, and e of FIG. 2 at this time show the voltages at the collector / reset input terminal 4 of the capacitor 17 and the transistor 20. Here, in the case of the present embodiment, if the trigger pulse is input to the trigger input terminal 2 again after noticing an erroneous operation, the reset is activated.

That is, it is assumed that the user inputs the trigger pulse again at time Q ₁ , that is, while the output terminal 3 is High. When the trigger pulse is input, the PNP transistor 20 turns ON, and therefore the NPN transistor 22 also turns ON. When the NPN transistor 22 is turned on,
The capacitor 15 is discharged, and the potential of the capacitor 15 decreases as shown by e in FIG. At time Q ₂ ,
When the potential of the capacitor 15 falls below the reset potential V _reset of the timer IC 9, the signal at the output terminal 3 becomes Low as shown in b of FIG. Therefore, the electric charge of the capacitor 17 is discharged through the resistor 16 and gradually decreases as shown in FIG. At this time, the voltage of the emitter of the PNP transistor 20 is lower than the potential of the capacitor 17 by the forward voltage V _{F of the} diode 18,
Therefore, the NPN transistor 22 continues to be turned on. That is, the reset input terminal 4 holds the ground potential. When the trigger pulse disappears at time Q ₃ as shown in FIG. 2A, the PNP transistor 20 and the NPN transistor 22 are turned off. Therefore, the capacitor 15 is charged again through the resistor 14, and the potential of the reset input terminal 4 rises. That is, it returns to the initial state in which the next trigger pulse is accepted.

[0011]

As described above, according to the present invention, the negative logic trigger input terminal, the positive logic output terminal, and the inputted signal are L.
When it is ow, a timer IC having a reset input terminal for fixing the output to Low, a resistor connected to the output terminal of the timer IC, a capacitor charged and discharged through the resistor, and an anode for the capacitor. The diode connected, the PNP transistor in which the cathode of the diode is connected to the emitter and the trigger input terminal of the timer IC is connected to the base via the resistor, and the collector of the PNP transistor is connected to the base via the resistor to connect the timer IC to the base. An NPN transistor having a collector connected to a reset input terminal and an emitter grounded is provided to provide a timer circuit in which an output can be reset when a trigger pulse is input again upon noticing an erroneous operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a timer circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing a voltage waveform of each part.

FIG. 3 is a circuit diagram showing a conventional timer circuit.

FIG. 4 is a diagram showing voltage waveforms of respective parts.

[Explanation of symbols]

 9 Timer IC 16 ・ 19 ・ 21 ・ 23 Resistor 17 Capacitor 18 Diode 20 PNP transistor 22 NPN transistor

Claims (1)

[Claims] 1. A negative logic trigger input terminal, a positive logic output terminal, and an output Lo when the input signal is Low.
Timer IC with reset input terminal fixed to w
A resistor connected to the output terminal of the timer IC, a capacitor charged and discharged through the resistor, a diode having an anode connected to the capacitor, a cathode of the diode as an emitter, and a trigger input of the timer IC. A timer including a PNP transistor having a terminal connected to a base via a resistor, an NPN transistor having a collector connected to the base of the PNP transistor via a resistor, a collector connected to a reset input terminal of the timer IC, and an emitter grounded. circuit.