JPS5838435Y2 - Reset signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset signal generation circuit for an electrical device having a power-on switch, such as an electronic desktop calculator.

A conventional example is shown in FIG.

In FIG. 1, when the switch 9 is turned on, the power supply voltage 1
0 typically rises with a certain time constant due to the capacitive load 8.

At this time, the reference voltage terminal of the comparator 10 rises with the same time constant as the rise of the power supply voltage 10 due to the voltage dividing ratio of the voltage dividing resistors 2 and 3.

Here, when the power supply voltage 10 is below the Zener voltage of the Zener diode 7, a reset signal is generated from the output terminal of the comparator 1.

Next, when the power supply voltage 10 becomes equal to or higher than the Zener voltage of the Zener diode T, charging of the capacitor 4 via the resistor 5 is started from the resistor 5 and the capacitor 4 by a time constant at the center.

When the terminal voltage on the capacitor 4, that is, the comparison voltage becomes larger than the divided voltage between the resistors 2 and 3, the reset signal is released.

Next, when the switch 9 is opened, the charge charged in the capacitive load 8 starts discharging through various resistors.

Furthermore, when the cathode side voltage of the Zener diode γ becomes equal to or less than the Zener voltage, the charge stored in the capacitor 4 is discharged via the resistors 5 and 6.

However, the resistor 5 has a large value in order to obtain a large delay time when the switch 9 is turned on.

Therefore, even if the cathode voltage of the Zener diode γ becomes less than the Zener voltage, the comparison voltage on the capacitor 4 does not immediately become smaller than the divided voltage of the resistors 2 and 3.

Therefore, the comparator 1 does not generate a reset signal immediately when the power supply voltage 10 is opened by the switch 9.

Generally, electronic devices are often equipped with a large number of power supplies, but a small amount of one power supply remaining may destroy an element.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to prevent element destruction caused by instability of power supply voltage when power is cut off.

This invention focuses on the fact that the voltage detection delay time can be changed when the power is turned on and when the power is turned off, and is devised so that the time constant of the famous constant circuit that sets the delay time becomes smaller when the power is turned off. .

An embodiment of the present invention is shown in FIG.

The operation when the switch 9 is turned on in FIG. 2 is the same as the operation in FIG. 1.

When the switch 9 is opened, the charge stored in the capacitive load 8 starts discharging through various resistive loads.

On the other hand, the charge in the capacitor 4 is discharged via the diode 12 and the resistor 6.

Since the resistor 6 is generally much smaller than the delay resistor 5, the discharge time of the capacitor 4 can be made much smaller than the discharge time of the capacitive load 8.

Therefore, after the switch 9 is opened, almost at the same time when the cathode voltage of the Zener diode 7 becomes lower than the Raney voltage of the Zener diode 7, (the anode voltage of the diode 12) becomes <(the divided voltage of the resistors 2 and 3). , comparator 1 can generate a reset signal.

According to the present invention, by making the time constant of the delay circuit required for the reset signal generation circuit large when the power is turned on and small when the power is turned off, it is possible to generate a reset signal immediately even when the power is turned off. Because it is possible to
Even if a small amount of this power remains, destruction of the element can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional reset signal generating circuit, and FIG. 2 is a circuit diagram showing an embodiment of the reset signal generating circuit of the present invention. In the figure, 1 is a comparator, 2 and 3 are power supply voltage dividing resistors, 4 is a delay time setting capacitor, 5 is a delay time setting resistor (second resistor), and 6 is a voltage detection resistor (first resistor).
, γ is a Zener diode, 8 is a capacitive load, 9 is a switch, 1a is a power supply voltage, 11 is a load of the comparator 1, and 12 is a diode.

Claims (1)

[Claims for Utility Model Registration] A Zener diode whose cathode is connected to the positive side of the power supply and whose anode is connected to the negative side of the power supply through a first resistor, and a capacitor connected to both ends of the first resistor through a second resistor. and a voltage dividing resistor connected to both ends of the power supply, and a comparator that compares a reference voltage generated by the voltage dividing resistor with a comparison voltage on the capacitor and generates a reset signal while the reference voltage is higher than the comparison voltage. In particular, a reset signal generating circuit comprising a diode whose cathode is connected to a midpoint between the anode of the Zener diode and the first resistor, and an anode of a diode connected to a midpoint between the second resistor and the capacitor. .