JPS5846584Y2 - timed circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time circuit suitable for electronic equipment using battery power.

In electronic equipment, a time-limited circuit as shown in Figure 1, which uses a time constant circuit, is used to generate output for a predetermined period of time because it is easy to construct and is not easily affected by variations in components. Traditionally used.

That is, by setting the flip-flop 1 with the generation of the trigger signal S and resetting it with the output of the time limit circuit 2,
The flip-flop is generated for a predetermined period T from the generation of the trigger signal S, and the timer circuit 2 includes a differentiating circuit 3 to which the set output Q of the flip-flop 1 is derived, and the output of the differentiating circuit 3 reaches a threshold level. A first inverter 4 whose output is inverted when the output drops, an integrating circuit 5 which integrates the output of the first inverter 4, and a second inverter whose output is inverted when the output of the integrating circuit 5 rises to a threshold level. Everter 6
and a diode 8 that discharges the charge of a capacitor 7 that constitutes an integrating circuit 5, and the output of the timer circuit 2 is
It is connected to the reset terminal R of the flip-flop 1 via an inverter 9.

Therefore, before time T1 when the trigger signal S is generated, the potential of each part is in the state shown in FIG. ) occurs at the first inverter 4
is inverted, and this state continues until time T2 when the output of the differentiating circuit 3 drops to the threshold level of the first inverter 4.

This time is determined by the time constant of the differentiating circuit 3.

The output of the differentiating circuit 3 drops to the threshold level,
When the output of the first inverter 4 is again inverted to the H level, the diode 8 is non-conductive and the capacitor 7 of the integrating circuit 5 is charged.

Then, the charging potential of the capacitor 7 is changed to the second inverter 6.
When the threshold level of is reached (at time T3),
The second inverter 6 is inverted and becomes L level, and this potential change is led to the reset I/terminal R of the flip-flop 1 via the third inverter 9.
Reset.

The time until the second inverter 6 is inverted is determined by the integration circuit 5.
determined by the time constant of

Therefore, an output is generated at the output terminal (OUT) for a period of time determined by the time constants of the differentiating circuit 3 and the integrating circuit 5 (FIG. 2A).

At this time, diode 8 is reset by reset I of flip-flop 1.
conducts, the charge in the capacitor 7 of the integrating circuit 5 is discharged, and the circuit enters a standby state for the next trigger signal.

In this case, the output generation period can be changed arbitrarily by changing the time constants of the differentiating circuit 3 and the integrating circuit 5.

Furthermore, by converting the inverters 4 and 6 into ICs and forming them on the same chip, the threshold levels become approximately the same.
This has the advantage that the output period is not affected by variations in the threshold level.

However, in this case, since the diode 8 is provided to discharge the charge of the capacitor 7 of the integrating circuit 5 when the flip-flop 1 is reset, the resistor 10 is connected to the output of the first inverter 4. Current flows through the diode 8, which consumes power, which has the drawback of shortening battery life in electronic devices that use batteries as a power source.

Therefore, the present invention has been devised in view of this point, and is an object of the present invention to provide a timer circuit with improved power consumption in the noset state.

The time limit circuit improved according to the present invention will be explained below with reference to FIG.

Components that are the same as those in Figure 1 are indicated by the same figure numbers.
Only the improved parts will be explained.

Reference numeral 11 denotes a transistor whose collector and emitter are connected between the output of the first inverter 4 and the integrating circuit 5, and is applied to the base electrode via a flip-flop resistor 12.

Therefore, upon generation of the trigger signal S, the flip-flop 1
When is set, the transistor 11 is set to a conductive state, thereby performing the same operation as described above.

When the flip-flop 1 is reset after a predetermined period of time, the output of the first inverter 4 is at H level, but the output of the flip-flop 1 changes to the low level, causing the transistor 11 to become non-conductive. .

Therefore, after the charge in the capacitor 7 is discharged, the diode 8 becomes non-conductive, and wasteful power consumption is prevented.

The present invention, which prevents wasteful power consumption in the reset state, can be applied to, for example, a portable clock radio, etc., and generates a trigger signal at a set time, and uses the flip-flop output to power the radio. If configured to control the radio, it would be convenient to have the radio sound for a predetermined period of time starting from a set time.

As mentioned above, the time limit circuit of the present invention improves wasteful power consumption in standby state, and has an extremely practical effect when applied to electronic equipment using batteries as a power source.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example of a time limit circuit, FIG. 2 is an operational waveform diagram of the main part of FIG. 1, and FIG. 3 is a diagram showing a time limit circuit according to the present invention.

Claims (1)

[Claims for Utility Model Registration] A flip-flop that is set by the generation of an l-rigger signal, a differentiating circuit that differentiates the output of the flip-flop,
a first inverter that inverts at the output level of the differentiating circuit;
an integrating circuit that integrates the output of the first inverter; a discharging circuit that discharges the output of the integrating circuit when resetting the flip-flop; a second inverter that inverts the output level of the integrating circuit at the output level of the flip-flop; What is claimed is: 1. A time-limiting circuit comprising a reset circuit configured to reset the circuit, wherein a flip-flop element is provided between the first inverter and the integrating circuit in the foot-flop.