JPS54140854A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS54140854A
JPS54140854A JP4895878A JP4895878A JPS54140854A JP S54140854 A JPS54140854 A JP S54140854A JP 4895878 A JP4895878 A JP 4895878A JP 4895878 A JP4895878 A JP 4895878A JP S54140854 A JPS54140854 A JP S54140854A
Authority
JP
Japan
Prior art keywords
time
input
level
power supply
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4895878A
Other languages
Japanese (ja)
Inventor
Masaaki Kanda
Yoshitaka Umeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4895878A priority Critical patent/JPS54140854A/en
Publication of JPS54140854A publication Critical patent/JPS54140854A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Abstract

PURPOSE:To obtain an output lagging as expected even when a power supply is turned ON-OFF in a short time. CONSTITUTION:The emitter of PNP transistor 8 is connected to input 6 of buffer circuit 5, its base is connected to power supply 1 via resistance 7, and its collector is connected to GND. As for the operation of this circuit, the base potential of transistor 8 decreases as the level of power supply 1 changes into ''L'' at time (Tc), so that transistor 8 will turn ON. In consequence, the charge of capacitor 4 connected to input 6 of circuit 5 charged at level ''H'' is discharged to GND via transistor 8 in a conductive state so that the level will decrease suddenly. This shows that the rise in the potential of input 6 is sudden and at time (tD), the potential of input 6 has reached the lowest level yet. Therefore, the change in the level of power supply 1 into ''H'' at time (tD) causes the charging of input 6 of circuit 5 as well as that at time (tA) and output 2 has the delay time of ''tE-tD''(=''tB-tA) and becomes ''H'' at time (tE)
JP4895878A 1978-04-24 1978-04-24 Delay circuit Pending JPS54140854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4895878A JPS54140854A (en) 1978-04-24 1978-04-24 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4895878A JPS54140854A (en) 1978-04-24 1978-04-24 Delay circuit

Publications (1)

Publication Number Publication Date
JPS54140854A true JPS54140854A (en) 1979-11-01

Family

ID=12817777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4895878A Pending JPS54140854A (en) 1978-04-24 1978-04-24 Delay circuit

Country Status (1)

Country Link
JP (1) JPS54140854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62294325A (en) * 1987-05-13 1987-12-21 Makoto Aso Timer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62294325A (en) * 1987-05-13 1987-12-21 Makoto Aso Timer circuit

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