JPS56111315A - Oscillating circuit - Google Patents

Oscillating circuit

Info

Publication number
JPS56111315A
JPS56111315A JP1380980A JP1380980A JPS56111315A JP S56111315 A JPS56111315 A JP S56111315A JP 1380980 A JP1380980 A JP 1380980A JP 1380980 A JP1380980 A JP 1380980A JP S56111315 A JPS56111315 A JP S56111315A
Authority
JP
Japan
Prior art keywords
output
capacitor
flop
flip
threshold level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1380980A
Other languages
Japanese (ja)
Inventor
Takao Kaneko
Hiroyuki Kikuchi
Kuniharu Uchimura
Minoru Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1380980A priority Critical patent/JPS56111315A/en
Publication of JPS56111315A publication Critical patent/JPS56111315A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape

Abstract

PURPOSE:To suppress a latch-up phenomenon by inputting the output voltage of a capacitor to a circuit with a different threshold level, by setting and resetting a flip- flop with its output and by charging and discharging the capacitor according to the output of the flip-flop. CONSTITUTION:When output Q of flip-flop FF19 is at a low level, switch element 12 is on and element 13 is off, so that capacitor 18 is charged by constant current source 11. As the charging voltage exceeds the threshold level of inverter 22, FF19 is set and output Q is at a high level. Consequently, the states of switch elements 12 and 13 are inverted and the capacitor is discharged via switch element 13. As the discharging voltage drops below the threshold level of inverter 23, FF19 is reset to its initial state and this operation is repeated.
JP1380980A 1980-02-06 1980-02-06 Oscillating circuit Pending JPS56111315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1380980A JPS56111315A (en) 1980-02-06 1980-02-06 Oscillating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1380980A JPS56111315A (en) 1980-02-06 1980-02-06 Oscillating circuit

Publications (1)

Publication Number Publication Date
JPS56111315A true JPS56111315A (en) 1981-09-03

Family

ID=11843594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1380980A Pending JPS56111315A (en) 1980-02-06 1980-02-06 Oscillating circuit

Country Status (1)

Country Link
JP (1) JPS56111315A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209153A (en) * 1982-05-31 1983-12-06 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209153A (en) * 1982-05-31 1983-12-06 Nec Corp Semiconductor integrated circuit device

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