JPS5639620A - Flip-flop circuit - Google Patents
Flip-flop circuitInfo
- Publication number
- JPS5639620A JPS5639620A JP11562679A JP11562679A JPS5639620A JP S5639620 A JPS5639620 A JP S5639620A JP 11562679 A JP11562679 A JP 11562679A JP 11562679 A JP11562679 A JP 11562679A JP S5639620 A JPS5639620 A JP S5639620A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- inputted
- capacitor
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
Abstract
PURPOSE:To reduce malfunctions due to electromagnetic coupling by attaining operation with low electric power and at a low voltage, by forming an FF circuit that sets at the rise of a set signal and then resets with a reset signal preferentially. CONSTITUTION:When neither a set signal nor a reset signal is inputted by capacitor 2 and switch circuit 1, FF circuit 3 charges capacitor 2 via FETs 11 and 12 and when the reset signal is inputted, capacitor 2 is discharged via FET13. Then, circuit 3 is set when the set signal is inputted with capacitor 2 charged and rset when the reset signal is inputted. Consequently, circuit 3 is set at the rise of the set signal and preferentially reset with the reset signal. Thus, low-power and low-voltage operations are attained to reduce malfunctions due to electromagnetic coupling, etc.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54115626A JPS5948568B2 (en) | 1979-09-07 | 1979-09-07 | flip-flop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54115626A JPS5948568B2 (en) | 1979-09-07 | 1979-09-07 | flip-flop circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5639620A true JPS5639620A (en) | 1981-04-15 |
JPS5948568B2 JPS5948568B2 (en) | 1984-11-27 |
Family
ID=14667299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54115626A Expired JPS5948568B2 (en) | 1979-09-07 | 1979-09-07 | flip-flop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5948568B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS648714A (en) * | 1987-07-01 | 1989-01-12 | Matsushita Electric Ind Co Ltd | Initial value setting circuit |
JPH04187058A (en) * | 1990-11-21 | 1992-07-03 | Nippon Shiyotsuken Kk | Dusting powder composition for fried food |
-
1979
- 1979-09-07 JP JP54115626A patent/JPS5948568B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS648714A (en) * | 1987-07-01 | 1989-01-12 | Matsushita Electric Ind Co Ltd | Initial value setting circuit |
JPH04187058A (en) * | 1990-11-21 | 1992-07-03 | Nippon Shiyotsuken Kk | Dusting powder composition for fried food |
Also Published As
Publication number | Publication date |
---|---|
JPS5948568B2 (en) | 1984-11-27 |
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