JP2710349B2 - Power-on reset circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit for preventing a digital circuit from malfunctioning when power is turned on or off.

[Conventional technology]

Conventionally, a power-on reset circuit of this kind, as exemplified that in Figure 5, to connect the series circuit of a resistor to the power supply terminal of the power supply V _CC R ₁₁ and capacitor C _11, a diode D to the resistance R _{11 21} is a circuit connected in parallel. And output from the charging voltage output terminal 1 of the capacitor C _11, are wired to be supplied to the integrated circuit element 2 to be a power-on reset signal V _O.

The power supply for operation is supplied to the integrated circuit element 2 by turning on the power supply V _CC . The integrated circuit device 2 keeps the state in which the reset release voltage V _B or more power-on reset signal V _O is up to given has been reset, the reset release voltage V _B
The reset is released by the above power-on reset signal V _O , and the circuit performs a normal operation. Resistor R ₁₁ is sometimes built in an integrated circuit device 2.

After the power supply V _CC is applied to such a circuit, the capacitor C ₁₁ is charged via the resistor R _11, and when the charged voltage of the capacitor C ₁₁ reaches the reset release voltage V _B , the integrated circuit element 2
Is reset. Accordingly, as shown in FIG. 6, when the increase of the power supply V _CC at power-on is stepped as shown in FIG. 6 is, after power, resistor R ₁₁ and a fixed time determined by the time constant of the capacitor C ₁₁ after t elapses, the power-on reset signal V _O is higher than a predetermined level of the reset release voltage V _B, it can be reset release of the integrated circuit device 2.

On the other hand, a voltage equal to or higher than the predetermined allowable operating voltage _VA is supplied to the integrated circuit element 2 immediately after the power is turned on. Therefore,
The reset of the integrated circuit element 2 is released after a lapse of a predetermined time t from the application of the allowable operating voltage _VA . or,
When power-off, the charge of the capacitor C ₁₁ is diode D ₂₁
, The integrated circuit element 2 is immediately reset.

[Problems to be solved by the invention]

The conventional power-on reset circuit described above uses the power supply V _CC
When the voltage rises and falls has a slope as shown in FIG. 7, or when a short-time instantaneous interruption occurs, there are the following problems.

First, when the voltage rise at power-on has a slope, the power-on reset signal V _O is _output from the power supply V _CC as shown in FIG.
It would reach the reset release voltage V _B before the voltage reaches the allowable operating voltage V _A. Further, if the instantaneous interruption occurs, the power-on reset signal V _O may not fall below the reset release voltage V _B. In these cases, during the period X or Y shown in FIG. 7, the reset is released while the power supply voltage equal to or lower than the allowable operating voltage _VA is supplied to the integrated circuit element 2, so that a malfunction may occur. The same applies to the case of power-off.

That is, the conventional power-on reset circuit shown in FIG. 5 has a drawback that it cannot fulfill its purpose in these cases.

An object of the present invention is to release the reset after a certain time from the point when the power supply voltage reaches the allowable operating voltage of the integrated circuit element, and to immediately reset when the power supply voltage falls below the allowable operating voltage. Another object of the present invention is to provide a power-on reset circuit that can surely secure resetting for a certain period of time again even when the power supply voltage is restored after a short interruption.

[Means for solving the problem]

In the power-on reset circuit according to the present invention, a first constant-voltage diode and a first resistor are connected in series and one end thereof is connected to a power supply terminal, and a base is connected to the other end of the constant-voltage circuit. A first emitter connected to a ground terminal;
A first switching circuit including an NPN transistor; a capacitor having one end connected to the power supply terminal; and a second resistor connected between the other end of the capacitor and a collector of the first NPN transistor. A charging circuit whose charging operation is controlled by the first switching circuit; and a collector follower-connected PNP transistor and a cathode whose base current is controlled by the charging circuit.
A second switching circuit having an anode connected to the base of the NP transistor and a second constant voltage diode connected to a connection point between the first capacitor and the second resistor; An output circuit including a third resistor connected to the collector and the other end connected to the ground terminal, and an output terminal connected to the collector of the PNP transistor; and an emitter connected to the first capacitor and the second resistor. A second NPN transistor connected to the connection point, a fourth resistor having one end connected to the collector of the second NPN transistor and the other end connected to the power supply terminal, and a fourth resistance connected to the power supply terminal at one end. A discharge circuit having an end connected to the base of the second NPN transistor and a collector of the first NPN transistor;

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of a first embodiment of the present invention.

As shown in FIG. 1, the charging circuit comprising the capacitor C ₁ and the second resistor R ₂ from the circuit connected in series is provided. Then, the charging circuit and the series connection circuit of the collector and the emitter of the _first NPN transistor Q1 are connected between the power supply terminal of the power supply V _CC and the ground terminal. The base of transistor Q ₁ is connected to the power supply terminal of the power supply V _CC through a first resistor R ₁ and a first constant voltage circuit comprising a constant voltage diode D _1.

The sum of the first base-emitter voltage V _BE1 of the Zener voltage V _Z1 and the transistor to Q ₁ constant voltage diode D ₁ is to be equal to the allowable operating voltage V _A which is described in the fifth to seventh earlier figures Is set to Thus, the transistor Q ₁ is the power supply V
_When the voltage of _CC becomes equal to or higher than a certain allowable operating voltage _VA , the conduction state is established. In this embodiment, the transistor Q ₁ and the resistor R ₁
And constituting the first switching circuit at a constant voltage diode D _1.

The power supply terminal of the power supply V _CC is connected to the emitter of a PNP transistor Q ₃ , and the base of the transistor Q ₃ is connected via a _second constant voltage diode D ₂ to a connection point between the capacitor C ₁ and the resistor R _2. It is connected to the. Further, the collector of the transistor Q ₃ are together connected to the output terminal 1 is connected to the ground terminal via the output resistor R _3. Circuit including a transistor Q ₃ are in this embodiment, constitutes a second switching circuit. Transistor Q ₃ are Zener voltage V _Z2 and transistor Q ₃ of the charging voltage V _C of the capacitor C ₁ is a constant voltage diode D ₂
Is non-conductive until the sum with the base-emitter voltage V _{BE3 of} FIG.

Further, the second switching circuit and the output resistor R ₃ are connected in series, and the power-on reset signal V _O is output from one end of the output resistor R ₃ through the output terminal 1. The power-on reset signal V _O goes high when the second switching circuit (ie, transistor Q ₃ ) is conducting.

Further, the second emitter of the NPN transistor Q ₂ is connected to a connection point between the capacitor C ₁ and a resistor R _2, connecting a collector resistor R ₄ and the base resistor R ₅ of the transistor Q ₂ to the power supply terminal of the power supply V _CC together, to connect the base of the transistor Q ₂ to the collector of the transistor Q _1. This circuit, when transistor Q ₁ is turned off, charge stored in the capacitor C ₁ flows to the base of the transistor Q ₂ through a resistor R _5, therefore, the charge of capacitor C ₁ and transistor Q ₂ is rendered conductive It is rapidly discharged through the resistor R _4.

FIG. 2 is a time chart showing waveforms of respective parts and transistor operation for explaining the operation of the first embodiment of FIG.

The operation of the first embodiment of FIG. 1 will be described below with reference to FIG. In FIG. 2, V _CC is the power supply, V _C
The charging voltage, V _O of the capacitor C ₁ is a power-on reset signal, Q ₁ to Q ₃ shows an operation state of each of the transistors Q ₁ to Q _3.

First, when the power is turned on, the voltage of the power supply V _CC rises. Until the power supply V _CC reaches a certain allowable operating voltage V _A , the transistor Q ₁ is in a non-conductive state, so that the transistor Q ₂ is in a conductive state, but no charge is stored in the capacitor C _1. because they are not, not supplied base current of the transistor Q ₂ is, therefore, the transistor Q ₂ is in the non-conductive state.

Next, when the power supply V _CC reaches the allowable operating voltage V _A , a current flows through the constant voltage diode D ₁ and the transistor Q ₁ is turned on, that is, the first switching circuit is turned on. Along with this, the base-emitter of the transistor Q ₂ is reverse biased, the charge in the capacitor C ₁ in time constant tau ₁ = C ₁ R ₂ together with the transistor Q ₂ is nonconducting begins, the capacitor C ₁ charging voltage V _C is increased in. When the charging voltage V _C reaches the sum of the base-emitter voltage V _BE3 of the Zener voltage V _Z2 and transistor Q ₃ of the constant voltage diode D _2, a current flows through the constant voltage diode D _2, the transistor Q ₃ through a resistor R ₂ the base current flows, the transistor Q ₃ is turned, i.e., the second switching circuit is operational. In this way, the power supply V _CC is
₃ , and a high-level power-on reset signal V _O is output from the output terminal 1.

Delay time t ₀ until the voltage of the capacitor C ₁ is in the conductive state of the transistor Q ₃ are, depending on the voltage rise rate of the power supply V _CC, almost capacitance of the capacitor C ₁ and the resistance value of the resistor R _2, and constant determined by the voltage diodes Zener voltage V _Z2 etc. D _2. The delay time t ₀ is minimum when the power supply V _CC is applied in a step-like manner. Therefore, if each circuit constant is set so that the delay time t ₀ becomes the predetermined value T, the delay time t ₀ must be longer than the predetermined value T. You can get time.

Therefore, if the first embodiment is connected to the power supply input terminal of the integrated circuit device 2 as shown in FIG. 5 described above, even after a voltage higher than the allowable operating voltage _VA starts to be supplied to the power supply input terminal. During the fixed delay time t ₀ , the reset is continued without fail and there is no possibility of malfunction.

Next, an instantaneous interruption occurs, and as shown in FIG.
_{After CC} falls below the allowable operating voltage V _A, illustrating the operation when a re-allowable operating voltage V _A or recovered immediately.

When the power V _CC falls below the allowable operating voltage V _A, the transistor Q ₁ is rendered non-conductive, the charge of capacitor C ₁ flows through the base of the transistor Q _2. Thus, it starts the discharge by a constant tau ₂ = C ₁ R ₄ when the charge of the capacitor C ₁ since the transistor Q ₂ is turned, the transistor Q ₃
Becomes non-conductive. At this time, the power-on reset signal
V _O immediately goes low, as shown in FIG. 2, resetting the integrated circuit device (not shown). here,
Τ ₂ is selected to be as small as possible (specifically, R ₄ is selected to be small) so that the electric charge of the capacitor C ₁ can be completely discharged even after a short interruption.

After a short interruption, the power supply V _{CC returns} to the allowable operating voltage V
Exceeds _A, the transistor Q ₁ is turned on, and thereafter, the same operation as when the power is turned as described above is performed, the reset is released after a predetermined delay time t _0, a malfunction of the integrated circuit element is completely prevented You. Note that when the power is turned off, the same operation as when the instantaneous interruption occurs is performed, and the power supply V _CC is set to the allowable operating voltage V _A
Reset occurs when the value falls below.

 FIG. 3 is a circuit diagram of a second embodiment of the present invention.

As shown in FIG. 3, in the second embodiment, a resistor R ₆ and a resistor R ₆ are provided between the base and the emitter of the transistors Q ₁ and Q _{3 in} FIG.
A circuit connected to R _7.

In the second embodiment, the constant voltage diode D ₁ and D ₂ or leakage current of the transistor Q _1, the transistors Q ₁ and
Prevents Q ₃ is turned, it can be advantageously a switching operation more reliably.

 FIG. 4 is a circuit diagram of a third embodiment of the present invention.

As shown in FIG. 4, the third embodiment is the transistor Q ₃ and the resistor R ₃ of the second embodiment of FIG. 3 described above, and a resistor R ₈ to the series.

In a third embodiment, the level of the output terminal 1 after the release of reset, by selecting the resistor R ₈ to be a level that ensures the reset release voltage level of the integrated circuit elements (not shown) after reset release it can be advantageously a power consumption of the transistor Q ₃ and the small.

〔The invention's effect〕

As described above, according to the present invention, the charging of the charging circuit in which the capacitor and the resistor are connected in series is started by the first switching circuit in which the power supply is turned on at the allowable operating voltage or more,
When the capacitor is charged to a certain voltage or higher, the second switching circuit is turned on, and a series connection circuit of the second switching circuit and the output resistor is connected between a power supply terminal and a ground terminal to form an output circuit. Further, when the power supply falls below the allowable operating voltage, the discharge circuit that rapidly discharges the charged capacitor is operated when the power supply reaches the allowable operating voltage when the power is turned on. There is an effect that the reset can be continuously performed for a certain period of time or more, and at the time of power-off, the voltage can be reset immediately after dropping to the allowable operating voltage. Further, there is an effect that the reset can be continued for a certain time or more even when the power is turned on after recovery from a short interruption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG.
FIGS. 3 and 4 are time charts showing voltage waveforms and transistor operations of respective parts for explaining the operation of the first embodiment of FIG.
The figures are circuit diagrams of the second and third embodiments of the present invention, respectively.
FIG. 5 is a circuit diagram of an example of a conventional power-on reset circuit, and FIGS. 6 and 7 are time charts for explaining the operation of the power-on reset circuit of FIG. 1 output terminal, 2 integrated circuit element, C ₁ , C ₁₁ … capacitor, D ₁ , D ₂ … constant voltage diode, D ₂₁ … diode, Q ₁ , Q ₂ … NPN transistor, Q ₃ …… PNP transistor, R _{1 to} R ₈ , R ₁₁ …… Resistance, V _A …… Permissible operating voltage, V
₈ … Reset release voltage, V _CC … Power supply, V _C … Charge voltage, V _O … Power-on reset signal, V _BE1 , V _BE3 … Base-emitter voltage.

Claims (1)

(57) [Claims] 1. A constant voltage circuit in which a first constant voltage diode and a first resistor are connected in series and one end thereof is connected to a power supply terminal, a base is connected to the other end of the constant voltage circuit, and an emitter is a ground terminal. A first switching circuit comprising: a first NPN transistor connected to the power supply terminal; a capacitor having one end connected to the power supply terminal; the other end of the capacitor;
Connected to the collector of the NPN transistor of
A charging circuit, the charging operation of which is controlled by the first switching circuit; and a collector follower-connected PNP transistor and a cathode, the base current of which is controlled by the charging circuit. A second switching circuit having an anode connected to a connection point between the first capacitor and the second resistor, a second switching circuit having one end connected to the collector of the PNP transistor and the other end grounded; An output circuit having a third resistor connected to the terminal and an output terminal connected to the collector of the PNP transistor; and a second circuit having an emitter connected to a connection point between the first capacitor and the second resistor. NPN transistor and one end are connected to the collector of the second NPN transistor, and the other end is connected to the power supply terminal. Source-based connection to the other end to the terminal the second NPN transistor and the first NPN
And a fifth resistor connected to the collector of the transistor.