JPH077911B2 - Power-on reset circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a power-on reset circuit for preventing malfunction of a digital circuit at power-on and power-off.

[Conventional technology]

An example of a conventional power-on reset circuit is shown in FIG.

This circuit is a circuit in which a resistor R ₁₁ and a capacitor C ₁₁ are connected in series to the power supply Vcc, and a diode D ₂₁ is connected in parallel to the resistor R ₁₁ . The charging voltage of this capacitor C ₁₁ is terminal 1
Is connected to the target integrated circuit element 2 as a power-on reset signal Vo.

The integrated circuit element 2 is supplied with power for operation when the power Vcc is turned on. The integrated circuit 2 until the reset release voltage V _B or more power-on reset signal Vo is applied maintaining a state of being reset by a reset release voltage V _B or more power-on reset signal Vo, the reset is released Is a circuit that performs normal operation. Resistor R ₁₁ is
It may be incorporated in the integrated circuit element 2.

After the power supply Vcc is applied to such a circuit, the capacitor C ₁₁ is charged through the resistor R _11, and when the charging voltage of the capacitor C ₁₁ reaches the reset release voltage V _B , the reset of the integrated circuit element 2 is released. To be done. Therefore, as shown in FIG. 6 (a), when the voltage Vcc rises stepwise when the power is turned on, as shown in FIG.
₁₁ and constant time t determined by the time constant of capacitor C ₁₁
After that, the power-on reset signal Vo exceeds the reset release voltage V _B of a predetermined level, and the reset release can be performed.

On the other hand, the integrated circuit element 2 is supplied with a voltage equal to or higher than a predetermined allowable operating voltage V _A immediately after the power is turned on. Therefore, the integrated circuit element 2 is released from reset after a fixed time t after the application of the allowable operating voltage V _A. Further, when the power is turned off, the electric charge of the capacitor C ₁₁ is immediately discharged through the diode D ₂₁ , so that the integrated circuit element 2 is immediately reset and no malfunction occurs.

However, when the voltage rise and fall of the power supply Vcc has a slope as shown in FIG. 7 (a), the power-on reset signal Vo is the power supply Vc as shown in FIG. 7 (b).
The reset release voltage V _B may be reached before the voltage of c reaches the allowable operating voltage V _A. In this case, during the period X shown in the figure, the integrated circuit element 2 is released from the reset state while being supplied with the power supply voltage equal to or lower than the allowable operating voltage V _A, which may cause a malfunction. The same applies to the case of power off.

That is, the conventional power-on reset circuit shown in FIG. 5 has a drawback that it cannot fulfill its purpose if the rise and fall of the power supply voltage are slow.

[Problems to be solved by the invention]

An object of the present invention is to solve the above-mentioned conventional drawbacks, to enable reset to be released after a certain period of time from when the power supply voltage reaches the allowable operating voltage of the integrated circuit, and when the power supply voltage falls below the allowable operating voltage. The present invention provides a power-on reset circuit which can be reset immediately, which is advantageous in terms of mounting or cost, and which can have a large fan-out.

[Means for solving problems]

The power-on / reset circuit of the present invention is characterized by including the following circuits.

A constant voltage circuit in which a first constant voltage diode D ₁ and a resistor R ₁ are connected in series and one end of which is connected to a power source, and the other end of which is connected to the base and whose emitter is connected to ground A first switching circuit consisting of _one NPN transistor Q ₁ .

A capacitor C ₁ with one end connected to the power supply and this capacitor
A _first diode D ₃ having an anode connected to the other end of C ₁ and a resistor R having one end connected to the cathode of the first diode D ₃ and the other end connected to the collector of the _first NPN transistor Q _{1. A} charging circuit comprising 2 and a second diode D ₄ whose cathode is connected to the anode of the first diode D _{3 and} whose anode is connected to the ground, and whose charging operation is controlled by the first switching circuit.

The PNP transistor Q ₂ supplied with switching current by this charging circuit, the cathode is connected to the base of the PNP transistor Q ₂ , and the anode is connected to the first diode.
A second switching circuit consisting of a _second voltage regulator diode D ₂ connected to the cathode of D ₃ .

An output circuit having a resistor R ₅ having one end connected to the collector of the PNP transistor Q ₂ and the other end connected to ground, and an output terminal 1 connected to the collector of the PNP transistor Q ₂ .

A second NPN transistor Q ₃ whose emitter is connected to the collector of the first NPN transistor Q ₁ , and one end of which is connected to the collector of this second NPN transistor Q ₃ , and the other end of which is the base of the PNP transistor Q ₂ . And a resistor R ₃ connected to the collector of the PNP transistor Q ₂ and the other end connected to the base of the second NPN transistor Q ₃
Positive feedback circuit consisting of ₄ and.

〔Example〕

 FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The circuit is first provided with a charging circuit including a circuit in which a capacitor C ₁ , a first diode D _3, and a third resistor R ₂ are connected in series. Then, the charging circuit and the collector-emitter series connection circuit of the first NPN transistor Q ₁ are connected between the power supply Vcc and the ground. Transistor
The base of Q ₁ is connected to the power supply Vcc through a constant voltage circuit composed of a second resistor R ₁ and a first constant voltage diode D ₁ .

The sum of the Zener voltage V _{Z1 of} the first constant voltage diode D ₁ and the base-emitter voltage V _BE1 of the transistor Q ₁ should be equal to the allowable operating voltage V _A described in FIGS. 5 and 6. Is set to. Therefore, the transistor Q ₁ is connected to the power source Vcc.
When the voltage of exceeds a certain allowable operating voltage V _A , it is turned on. In this embodiment, the transistor Q ₁ , the resistor R ₁ , and the constant voltage diode D ₁ constitute the first switching circuit I.

Further, the voltage Vcc is further connected to the emitter of the PNP transistor Q ₂ , and the base of the transistor Q ₂ is connected to the connection point between the diode D ₃ and the resistor R ₂ via the _second constant voltage diode D _2. It is connected. Then, the collector of the transistor Q ₂ is connected to the ground via the output resistor R ₅ . The output terminal 1 is connected to both connection parts. The anode of the second diode D ₄ is grounded and the cathode is connected between the capacitor C ₁ and the first diode D ₃ .

In the present embodiment, the circuit including the transistor Q ₂ is the _second circuit.
Of the switching circuit II. This transistor Q ₂
Is that the charging voltage Vc of the capacitor C ₁ is the Zener voltage V _{Z2 of the second} constant voltage diode D ₂ and the base voltage of the transistor Q ₂ .
It is in the OFF state until the value obtained by subtracting the forward voltage V _D3 of the first diode D ₃ from the sum of the emitter-to-emitter voltage V _BE2 ,
It will be in the ON state when the voltage is higher than the above value. The diode D ₃ has a polarity that prevents the charge of the capacitor C _{1 from} flowing as a base current of the transistor Q ₂ when the power supply is cut off.

Further, the second switching circuit II and the output resistance R ₅ are connected in series, and the power-on reset signal Vo is output from one end of the output resistance R ₅ through the terminal 1. An output circuit is configured by these. The power-on reset signal Vo has a high level when the second switching circuit II is in the ON state.

Further, the collector of the transistor Q ₂ is connected to the base of the second NPN transistor Q ₃ through the base resistance R ₄ , and the collector resistance R ₃ of this transistor Q ₃ is connected to the base of the transistor Q ₂ and the positive feedback is provided. Make up the circuit. Transistor Q ₃ is turned ON by the present circuit, the base current of the transistor Q ₂ flows through the resistor R _3, so that the transistor Q ₂ can be sufficiently drive.

Next, the operation of the circuit of this embodiment will be described with reference to FIGS.
It will be described with reference to the drawings.

2 (a) is the voltage of the power source Vcc, FIG. 2 (b) is the charging voltage Vc of the capacitor C ₁ , FIG. 2 (c) is the power-on reset signal Vo, and FIG. 2 (d) is each transistor Q ₁ ... It is a time chart which shows the state of Q ₃ .

First, when the power source is turned on, the voltage of the power source Vcc rises as shown in FIG. 2 (a) and reaches a certain allowable operating voltage V _A ,
The first voltage regulator diode D ₁ conducts and the transistor Q ₁
Turn on. That is, the first switching circuit I is turned on. As a result, charging of the capacitor C ₁ is started, and the charging voltage Vc of the capacitor C ₁ rises as shown in FIG. 2 (b). This voltage is calculated from the sum of the Zener voltage V _{Z2 of the second} constant voltage diode D ₂ and the base-emitter voltage V _BE2 of the transistor Q ₂ and the forward voltage V 1 of the first diode D _3.
It reaches a certain value minus the _D3, Zener diode D ₂ conducts. This allows the transistor to pass through resistor R _2.
The base current flows Q _2, turns ON the transistor Q ₂ or second switching circuit II slightly. With this, terminal 1
The potential rises and the base current starts to be supplied to the transistor Q ₃ through the resistor R ₄ . This turns ON the slightly transistor Q ₃ by the base current, the base current of the transistor Q _2, to further drive through collector resistor R _3, the transistor Q ₂ is further turned ON, even further increases the potential of the terminal 1. The same process is repeated thereafter, positive feedback is applied, the transistors Q ₂ and Q ₃ are rapidly turned on, the power source Vcc is applied to the output resistor R _5, and the high voltage from the terminal 1 as shown in FIG. The level power-on reset signal Vo is output.

Delay time t for the voltage of the capacitor C ₁ causes the ON the second switching circuit II, depending on the rate of rise of the voltage of the power source Vcc, almost the resistance value of the capacitance and resistance R ₂ of the capacitor C ₁ and, the Zener voltage V of constant voltage diode D ₂ of _2
Determined by _Z2 etc. And this delay time t is
The minimum is when Vcc is applied stepwise. Therefore, if each circuit constant is set so that this minimum delay time to becomes a predetermined value, a delay time of to or more can be obtained without fail.

That is, if such a circuit is connected to the power input terminal of the integrated circuit element as shown in FIG. 5, the allowable operating voltage V _A
Even after the above voltage starts to be supplied to the input terminal, the reset is surely continued for a certain delay time to, and there is no possibility of causing a malfunction.

Here, increasing the size of the capacitor C ₁ as a method of obtaining the delay time to is disadvantageous in terms of mounting structure and cost. Therefore, it is general to make the capacitor C ₁ as small as possible and instead make the resistor R ₂ a large value. In this circuit,
Immediately after the start of charging the capacitor C ₁ , the transistor Q ₃ turns off.
Therefore, the resistor R ₂ can be selected large, and the capacitor C ₁ can be made sufficiently small. On the other hand, in this circuit, after this delay time to elapses, the transistor Q ₃ turns on.
Then, the resistor R ₃ will be inserted in the base circuit of the transistor Q ₂ , but this R ₃ can be chosen to be a small value so as to allow sufficient base current to drive the transistor Q ₂ . Therefore, the power-on reset circuit of the present invention can have a large fan-out.

Further, when the power supply voltage Vcc drops to the allowable operating voltage V _A as shown in FIG. 2 (a) when the power supply is cut off, the transistor Q ₁ is turned off and the base current of the transistor Q ₂ is cut off. To turn it off immediately. At this time, the transistor Q ₃ also turns off at the same time. Therefore, the power-on reset signal Vo immediately becomes low level as shown in FIG. 7C, and resets the integrated circuit element (not shown). As a result, malfunction of the integrated circuit element is completely prevented even when the power is turned off. On the other hand, the charging voltage Vc of the capacitor C ₁ is until the power supply Vcc drops to V _Z2 + V _BE2 −V _D3 −V _D4 (V _D4 is the forward voltage of the second diode D ₄ )
Since there is no discharge loop, the charge voltage is maintained, and then the charge of the capacitor C ₁ is discharged through the diode D ₄ and becomes 0 as shown in FIG.

FIG. 3 is a modified example of the above embodiment, which is a circuit in which resistors R ₆ , R ₇ , and R ₈ are connected between the base and emitter of the transistors Q ₁ , Q ₂ , and Q ₃ of FIG. ₁ , respectively. .

In the case of this circuit, the leakage current of the first constant voltage diode D ₁ , the second constant voltage diode D ₂ or the transistor Q ₁ prevents the transistors Q ₁ , Q ₂ and Q ₃ from turning on. There is an advantage that the switching operation can be performed more reliably.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

This circuit is a circuit in which a resistor R ₉ is inserted in series with the transistor Q ₂ and the resistor R ₅ of the circuit shown in FIG. In this case, by selecting the resistor R ₉ so that the level of the terminal 1 after the reset is released is a level that guarantees the reset release voltage level of the integrated circuit element (not shown), the consumption of the transistor Q ₂ after the reset is released. The power can be small.

〔The invention's effect〕

As described above, in the present invention, the operation of the charging circuit in which the capacitor and the resistor are connected in series is started by the first switching circuit in which the power source is turned on at the allowable operating voltage or more, and the capacitor is charged to a certain voltage or more. At this time, the second switching circuit is rapidly turned on by using the positive feedback circuit, and the series circuit of the second switching circuit and the output resistor is connected between the power supply and the ground to form the output circuit. When the power is turned on, it is possible to reliably continue the reset for a certain time or more after the power reaches the allowable operating voltage. Further, when the power is turned off, the reset can be performed immediately when the operating voltage drops to the allowable operating voltage. Further, it is possible to provide a circuit that simultaneously satisfies the contradictory conditions of reducing the capacitance of the capacitor and increasing the fan-out. That is, it is possible to reliably prevent malfunction of the integrated circuit when the power is turned on and off,
It is advantageous in terms of mounting or cost, and has the effect of achieving a large fan-out.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a power-on reset circuit of the present invention, FIG. 2 is a time chart showing voltage waveforms and operations of each part of this embodiment, and FIG. 3 is a modification thereof. Circuit diagram, FIG. 4 is a circuit diagram showing another embodiment of the present invention,
FIG. 5 is a circuit diagram showing the configuration of a conventional power-on reset circuit, and FIGS. 6 and 7 are time charts showing its operation. 1 ...... output terminal, 2 ...... integrated circuit element, C ₁ ...... capacitor, D ₁ ...... first constant voltage diode, D ₂ ...... second constant voltage diode, D ₃ ...... first diode, D ₄ …… Second diode, Q ₁ …… First NPN transistor, Q ₂ …… PNP transistor, Q ₃ …… Second NPN transistor, R _{1 to} R ₉ , R ₁₁ …… Resistance, V _A ... Allowable operating voltage, V _B ... Reset release voltage, Vcc ... Power supply, Vc ... Capacitor charging voltage, Vo ... Power-on reset signal, V _D3 , V _D4 ... Diodes D ₃ and D ₄ in this order Directional voltage. V _BE1 , V _BE2 …… Base-emitter voltage of transistors Q ₁ and Q ₂ ,

Claims (1)

[Claims] 1. A power-on reset circuit comprising the following circuits. A constant voltage circuit in which a first constant voltage diode and a resistor are connected in series and one end of which is connected to a power supply, and a first NPN transistor in which the other end of this constant voltage circuit is connected to the base and the emitter is connected to ground A first switching circuit comprising: A capacitor having one end connected to a power supply, a first diode having an anode connected to the other end of the capacitor, one end connected to the cathode of the first diode, and the other end connected to the collector of the first NPN transistor Resistance,
Connecting the cathode to the anode of the first diode,
A charging circuit comprising a second diode for discharging whose anode is connected to ground and whose charging operation is controlled by the first switching circuit. A second PNP transistor supplied with a switching current by the charging circuit, and a second constant voltage diode having a cathode connected to the base of the PNP transistor and an anode connected to the cathode of the first diode. Switching circuit. An output circuit having a resistor having one end connected to the collector of the PNP transistor and the other end connected to ground, and an output terminal connected to the collector of the PNP transistor. A second NPN transistor having an emitter connected to the collector of the first NPN transistor and one end of the second NPN transistor.
A resistor connected to the collector of the PN transistor and the other end to the base of the PNP transistor, and one end connected to the PNP transistor.
Connect to the collector of the transistor and connect the other end to the second NPN
Positive feedback circuit consisting of a resistor connected to the base of a transistor.