JPS62269415A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To ensure the reset continuity for a prescribed time or longer after a power supply reaches a permissible voltage by turning on rapidly the 2nd switching circuit by a positive feedback circuit when a capacitor is charged over a prescribed voltage. CONSTITUTION:The titled circuit consists of the 1st switching circuit I including the 1st constant voltage diode D1 and the 1st NPN transistor (TR) Q1, of a charging circuit including the 1st and 2nd diodes D3, D4, of the 2nd switching circuit including the 2nd constant voltage diode D2, of an output circuit having an output terminal 1, and of a positive feedback circuit including the 2nd NPN TR Q3. One terminal of a resistor R3 of the positive feedback circuit is espe cially connected to the collector of the 2nd NPN TR Q3 and the other terminal is connected to the base of a PNP TR Q2. Thus, the resetting is released at a prescribed time after the power voltage reaches the permissible operating voltage of an integrated circuit and if the power voltage is lower than the permissbile operating voltage, the resetting is immediately applied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit for preventing malfunctions when power is turned on or turned off in a digital circuit.

[Conventional technology]

An example of a conventional power-on reset circuit is shown in FIG.

This circuit connects a series circuit of a resistor R1+ and a capacitor C1 to the power supply Vcc, and a diode D to the resistor R11.
This is a circuit in which 21 are connected in parallel. This capacitor CI
The wiring is such that a + charging voltage is output from the terminal l and supplied to the target integrated circuit element 2 as a power-on reset signal Vo.

The integrated circuit element 2 is supplied with power for operation by turning on the power supply Vcc. This integrated circuit 2 remains in a reset state until a power-on reset signal ■0 with a reset release voltage ■6 or higher is applied, and is reset by a power-on reset signal ■0 with a reset release voltage ■8 or higher. This is a circuit that operates normally after being released.

Resistor R11 may be built into integrated circuit element 2 in some cases.

After the power supply Vcc is applied to such a circuit, the resistor R1
1, capacitor C11 is charged through capacitor C
When the charging voltage 11 reaches the reset release voltage 8, the reset of the integrated circuit element 2 is released. Therefore, as shown in FIG. 6(a), when the voltage CC rises stepwise when the power is turned on, as shown in FIG. 6(b), after the power is turned on, the resistance R11 and the capacitor CI + After a certain period of time determined by the time constant of V, the power-on reset signal V.

exceeds a predetermined level of reset release voltage (2), the reset can be released.

On the other hand, the integrated circuit element 2 is supplied with a voltage equal to or higher than the predetermined allowable operating voltage immediately after the power is turned on. Therefore,
The integrated circuit element 2 will be released from reset after a certain period of time has elapsed since the allowable operating voltage (2) was applied. Furthermore, when the power is turned off, the charge in the capacitor C11 is immediately discharged through the diode D2+, so the integrated circuit element 2 is immediately reset and does not malfunction.

However, the rise and fall of the voltage of the power supply Vcc, as shown in Fig. 7 (
If the power-on reset signal ■0 has a slope as shown in a), the power-on reset signal
The voltage of cc may reach the reset release voltage ■ before reaching the allowable operating voltage ■. In this case, during the period X shown in the figure, the integrated circuit element 2 is released from reset while being supplied with a power supply voltage that is less than the allowable operating voltage (2), so there is a risk of malfunction. The same applies to the case of power-off.

That is, the conventional power-on reset circuit shown in FIG. 5 has the disadvantage that it cannot fulfill its purpose if the power supply voltage rises and falls slowly.

[Problem that the invention seeks to solve]

An object of the present invention is to solve the above-mentioned conventional drawbacks, to be able to release the reset after a certain period of time from the point when the power supply voltage reaches the permissible operating voltage of the integrated circuit, and when the power supply voltage drops below the permissible operating voltage. An object of the present invention is to provide a power-on reset circuit that can be reset immediately, is advantageous in terms of implementation and cost, and can have a large fan-out.

Means for Solving Problem C] The power-on reset circuit of the present invention is characterized by comprising the following circuits 1 to 5.

■ A constant voltage circuit in which a first constant voltage diode D1 and a resistor R1 are connected in series, one end of which is connected to a power supply; the other end of this constant voltage circuit is connected to a base, and an emitter is connected to ground. A first switching circuit comprising an NPN transistor Q1.

■A capacitor C1 whose one end is connected to the power supply and a first diode D whose anode is connected to the other end of this capacitor C1.
, . One end is connected to the cathode of the first diode D3, and the other end is connected to the first NPN transistor Q1.
and a second diode D whose cathode is connected to the anode of the first diode D3 and whose anode is connected to ground, and the charging operation is performed by the first switching circuit. Controlled charging circuit.

■PNP supplied with current for switching by this charging circuit Ranjisk Q2 and the cathode of the above PN
P. A second switching circuit comprising a second constant voltage diode D2 connected to the base of the transistor Q2 and having its anode connected to the cathode of the first diode D3.

■One end is connected to the collector of this PNP transistor Q2, and the other end is connected to ground, and its PN
P an output circuit having an output terminal l connected to the collector of transistor Q2.

■A second NPN transistor Q3 whose emitter was connected to the collector of the first NPN transistor Q1, one end of which was connected to the collector of the second NPN transistor Q3, and the other end connected to the base of the PNP transistor Q2. A resistor R3 has one end connected to the collector of the PNP transistor Q2 and the other end connected to the second NP transistor Q2.
A positive feedback circuit consisting of a resistor R2 connected to the base of N transistor Q3.

〔Example〕

FIG. 1 is a diagram showing one embodiment of the present invention.

This circuit is first provided with a charging circuit consisting of a circuit in which a capacitor C1, a first diode D3, and a third resistor R2 are connected in series.

The charging circuit and a series connection circuit of the collector and emitter of the first NPN transistor Q1 are connected between the power supply Vcc and the ground. The base of transistor Q is
It is connected to the power supply Vcc through a constant voltage circuit consisting of a second resistor R1 and a first constant voltage diode D1.

Zener voltage VZI of the first constant voltage diode D1 and base-emitter voltage VBE of the transistor Q1
The sum of I and I is set to be equal to the allowable operating voltage {circle around (2)} explained in FIG. 5 and FIG.

Therefore, the transistor Q1 is turned on when the voltage of the power supply Vcc exceeds a certain allowable operating voltage 5. In this embodiment, a transistor Q1, a resistor R1, and a constant voltage diode D constitute a first switching circuit l.

Further, the emitter of a PNP transistor Q2 is connected to the power supply Vcc, and the base of this transistor Q2 is connected to the connection point between the diode D3 and the resistor R2 via the second voltage regulator diode D2. . The collector of transistor Q2 is then connected to ground via output resistor R5. An output terminal l is connected to the connection portion between the two. Further, the anode of the second diode D is grounded, and its cathode is connected between the capacitor C1 and the first diode D3.

In this embodiment, the circuit including the transistor Q2 constitutes the second switching circuit (2). In this transistor Q2, the charging voltage Vc of the capacitor C1 is the sum of the Zener voltage V Z 2 of the second constant voltage diode D2 and the base-emitter voltage VllE2 of the transistor Q2, and the forward voltage V of the first diode D3 is determined by the charging voltage Vc of the capacitor C1. I+3
It is in the OFF state until the value obtained by subtracting the above voltage is reached, and it is in the ON state when the voltage exceeds the above voltage. The diode D3 has a polarity that prevents the charge in the capacitor CI from flowing as the base current of the transistor Q2 when the power is turned off.

Further, the second switching circuit (2) and an output resistor R5 are connected in series, and a power-on reset signal (2)0 is outputted from one end of the output resistor R6 through a terminal l. These constitute an output circuit. This power-on
Reset signal■.

is high when the second switching circuit ■ is in the ON state.
level.

Furthermore, the collector and base resistances R of transistor Q2
1 is connected to the base of a second NPN transistor Q3, and this transistor Q.

The collector resistor R3 is connected to the base of the transistor Q2 and forms a positive feedback circuit. When the transistor Q is turned on by this circuit, the base current of the transistor Q2 flows through the resistor R3, and the transistor Q2 can be sufficiently driven.

Next, the operation of the circuit of this example will be explained in FIGS. 1 and 2.
This will be explained with reference to the figures.

Figure 2 (a) shows the voltage of the power supply Vcc, Figure 2 (b) shows the charging voltage Vc of the capacitor C1, Figure 2 (C) shows the power-on reset signal Vo, and Figure 2 (d) shows each transistor Q1 to Q.
3 is a time chart showing state No. 3.

First, when the power is turned on, the voltage of the power supply Vcc increases as shown in Fig. 2 (a).
When the voltage increases as shown in FIG. 1 and reaches a certain allowable operating voltage, the first constant voltage diode D1 becomes conductive and the transistor Q1 turns on. Zunawaji, the first switching circuit ■ turns on. As a result, charging of the capacitor C1 starts, and the charging voltage Vc of the capacitor C1 increases as shown in FIG.
It rises as shown in b). This voltage reaches a constant value obtained by subtracting the forward voltage VD3 of the first diode D3 from the sum of the Zener voltage VZ2 of the second constant voltage diode D2 and the base-emitter voltage 8,2 of the transistor Q2. Then, Zener diode D2 becomes conductive.

As a result, the base current of the transistor Q2 flows through the resistor R2, and the transistor Q2, that is, the second switching circuit (2) is slightly turned on. This causes the potential of terminal 1 to rise, and base current begins to be supplied to transistor Q3 through resistor R1. This base current also turns on transistor Q3 slightly, causing transistor Q
In order to further drive the base current of 2 through collector resistor R3, transistor Q2 further drives ONL,
The potential at terminal 1 also increases further. After that, the same process is repeated and positive feedback is applied, transistors Q2 and Q3 are turned on rapidly, power supply Vcc is applied to output resistor R5, and high level power is turned on from terminal 1 as shown in Figure 2 (C). - Reset signal Vo is output.

The voltage of capacitor C1 is O
The delay time t until the
Although it depends on the rising speed, the capacitance of the capacitor C1, the resistance value of the resistor R2, and the second voltage regulator diode D2
It is determined by the Zener voltage V z 2, etc. and,
This delay time t is minimum when the power supply Vcc is applied in a stepwise manner. Therefore, if each circuit constant is set so that the minimum delay time to becomes a predetermined value, a delay time greater than or equal to to can always be obtained.

That is, if such a circuit is connected to the power input terminal of an integrated circuit device as shown in FIG.
Even after a voltage equal to or higher than A starts to be supplied to the input terminal, it continues to be reliably reset for a certain delay time to, and there is no risk of malfunction.

Here, as a method to obtain the delay time to, the capacitor C
Increasing I is disadvantageous in terms of mounting structure and cost. Therefore, it is common to make the capacitor C1 as small as possible and instead set the resistor R2 to a large value. In this circuit, the transistor Q3 is turned off immediately after the start of charging the capacitor C1, and the resistor R2 can be made large, so that the capacitor CI can be made sufficiently small. - In the power tree circuit, after this delay time to has elapsed, transistor Q3 is ONI, and resistor R3 is inserted into the base circuit of transistor Q2, but this R
3 can be chosen to be small enough to provide enough base current to drive transistor 2.

Therefore, this power-on reset circuit
It becomes possible to take a large out.

Furthermore, when the power is turned off, the voltage of the power supply Vcc is
As shown in Figure (a), when the allowable operating voltage drops to 4, the transistor Q1 goes to OFFL and the transistor Q2 immediately turns off because its base current is cut off.

At this time, transistor Q3 is also turned off at the same time. Therefore, the power-on reset signal 0 immediately becomes a low level as shown in FIG.
(not shown). This completely prevents the integrated circuit element from malfunctioning even when the power is turned off.

On the other hand, the charging voltage Vc of the capacitor C1 is determined when the power supply Vcc is VZ2 + VBE2 VH2 - VO2 (V114
Since there is no discharging loop, the charging voltage is maintained until the voltage drops to the forward voltage of the second diode D4.Then, the charge of the capacitor C1 is discharged through the diode D, and the voltage shown in FIG. It becomes 0 as shown.

FIG. 3 shows a modification of the above embodiment, in which between the base and emitter of the transistors Q1, Q2, and Q3 in FIG.
This is a circuit in which resistors R6, R7, and R8 are connected to each other.

In the case of this circuit, the first constant voltage diode D1, the second
constant voltage diode D2, or transistor Q1
Due to the leakage current, transistors Ql, Q2, Q
3 is prevented from turning on, which has the advantage of making the switching operation more reliable.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

This circuit consists of transistor Q2 and resistor R of the circuit of FIG.
This is a circuit in which a resistor R9 is inserted in series with R5. In this case, the level of terminal 1 after the reset is released is the integrated circuit element (
By selecting the resistor R8 at a level that guarantees the reset release voltage level of (not shown), the power consumption of the transistor Q2 after the reset is released can be reduced.

〔Effect of the invention〕

As described above, in the present invention, the operation of the charging circuit in which a capacitor and a resistor are connected in series is started by the first switching circuit in which the power supply is turned ON when the power supply is above the allowable operating voltage, and the above-mentioned capacitor is charged above a certain voltage. , the second switching circuit is rapidly turned on using a positive feedback circuit.
Since the output circuit is configured by connecting the second switching circuit and the series connection circuit of the output resistor between the power supply and the ground, when the power is turned on, after the power supply reaches the allowable operating voltage, can be reliably continued. Furthermore, when the power is turned off, it can be reset immediately when the voltage drops to the allowable operating voltage.

Furthermore, it is possible to provide a circuit that simultaneously satisfies the contradictory conditions of reducing the capacitance of the capacitor and increasing the fan-out. That is, it is possible to reliably prevent malfunctions of the integrated circuit when the power is turned on and off, and it is also advantageous in terms of implementation and cost, and has the effect of allowing a large fan-out.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the power-on reset circuit of the present invention, Fig. 2 is a time chart showing voltage waveforms and operations of various parts of this embodiment, and Fig. 3 shows a modification thereof. A circuit diagram, FIG. 4 is a circuit diagram showing another embodiment of the present invention,
FIG. 5 is a circuit diagram showing the configuration of a conventional power-on reset circuit, and FIGS. 6 and 7 are time charts showing its operation. l...Output terminal, 2...Integrated circuit element, C1...Capacitor, Dl...First voltage regulator diode, D2...
...Second voltage regulator diode, D3...First diode, D,...Second diode, Ql...First NPN transistor, Q2
・・・・・・PNP) Ranjisk, Q3・・・・・・
Second NPN transistor, R3-”9, R11...
...Resistance, ■, ...Allowable operating voltage, ■8 ...Reset release voltage, Vcc...
...Power supply, Vc...Capacitor charging voltage, ■0...
・Power-on reset signal, VO2, VO4...
...Forward voltage of diodes D3 and D4. VBEI, VBE2...Transistor Q
Base-emitter voltage of 1 and Q2, applicant NEC Corporation agent

Claims (1)

[Scope of Claims] A power-on reset circuit comprising the following circuits 1 to 5. 1 A constant voltage circuit in which a first constant voltage diode and a resistor are connected in series with one end connected to a power supply, and a first NPN in which the other end of this constant voltage circuit is connected to a base and the emitter is connected to ground. A first switching circuit consisting of a transistor. 2 A capacitor having one end connected to a power supply, a first diode having an anode connected to the other end of the capacitor, one end connected to the cathode of the first diode, and the other end connected to the collector of the first NPN transistor. and a second diode for discharging whose cathode is connected to the anode of the first diode and whose anode is connected to ground, and the charging circuit has a charging operation controlled by the first switching circuit. 3. A second voltage regulator diode comprising a PNP transistor to which a switching current is supplied by the charging circuit, and a second voltage regulator diode whose cathode is connected to the base of the PNP transistor and whose anode is connected to the cathode of the first diode. switching circuit. 4. An output circuit having a resistor having one end connected to the collector of the PNP transistor and the other end connected to ground, and an output terminal connected to the collector of the PNP transistor. 5 a second NPN transistor having an emitter connected to the collector of the first NPN transistor; a resistor having one end connected to the collector of the second NPN transistor and the other end connected to the base of the PNP transistor; and a resistor connected to the collector of the PNP transistor and the other end connected to the base of the second NPN transistor.