JPH0473326B2 - - Google Patents
Info
- Publication number
- JPH0473326B2 JPH0473326B2 JP58127275A JP12727583A JPH0473326B2 JP H0473326 B2 JPH0473326 B2 JP H0473326B2 JP 58127275 A JP58127275 A JP 58127275A JP 12727583 A JP12727583 A JP 12727583A JP H0473326 B2 JPH0473326 B2 JP H0473326B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- output transistor
- current
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 16
- 238000007599 discharging Methods 0.000 claims description 4
- 238000011084 recovery Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0826—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in bipolar transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
Landscapes
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、高出力用のバイポーラトランジスタ
を内蔵した高出力用集積回路に係り、特に出力ト
ランジスタの負荷の短絡時にこのトランジスタを
保護するための出力トランジスタ保護回路に関す
る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a high-output integrated circuit incorporating a high-output bipolar transistor, and particularly to an output transistor for protecting the output transistor when the load of the output transistor is short-circuited. Regarding transistor protection circuits.
この種の従来の出力トランジスタ保護回路は、
出力トランジスタの出力電流を監視することによ
つて負荷短絡時を検出し、この検出と同時に出力
トランジスタの動作を遮断し、こののちタイマ回
路による設定時間後に出力トランジスタの動作を
復帰させるように制御を行なつている。したがつ
て、この復帰動作時に依然として負荷短絡状態が
続いていれば、上述したように遮断、復帰動作を
繰り返すようになり、出力トランジスタは出力電
流のオン、オフを繰り返すことによつて破壊から
保護される。
This kind of conventional output transistor protection circuit is
By monitoring the output current of the output transistor, a load short-circuit is detected, and at the same time as this detection, the operation of the output transistor is cut off, and the control is then performed so that the operation of the output transistor is restored after a set time by a timer circuit. is being carried out. Therefore, if the load short-circuit condition continues during this recovery operation, the cutoff and recovery operations will be repeated as described above, and the output transistor will be protected from destruction by repeatedly turning the output current on and off. be done.
ところで、上記出力電流のオン、オフ期間は、
各対応して負荷短絡検出から出力トランジスタの
オフ制御までのフイードバツクループの信号遅れ
時間およびタイマ回路の設定時間に依存するが、
このタイマ回路の設定時間はばらつきが大きいの
で、上記オン、オフ期間のデユーテイ比がばらつ
く。これによつて、出力トランジスタに対する保
護能力にばらつきが生じ、出力トランジスタを確
実に保護することが困難であつた。また、負荷が
ランプ等の容量性負荷の場合には、上記出力電流
のオン期間を大きくする必要があるが、これに伴
つて一定のデユーテイ比を得るためにオフ期間を
大きくすべくタイマ回路の設定時間を長くする必
要があり、そうするとタイマ回路の設定時間がま
すますばらつくのでデユーテイ比のばらつきが大
きくなる。
By the way, the on/off period of the above output current is
It depends on the signal delay time of the feedback loop and the setting time of the timer circuit from load short circuit detection to output transistor OFF control, respectively.
Since the set time of this timer circuit varies widely, the duty ratio of the on-off period mentioned above also varies. This causes variations in the ability to protect the output transistors, making it difficult to reliably protect the output transistors. In addition, when the load is a capacitive load such as a lamp, it is necessary to increase the on-period of the above output current, but in conjunction with this, the timer circuit is required to increase the off-period in order to obtain a constant duty ratio. It is necessary to lengthen the setting time, and this causes further variation in the setting time of the timer circuit, resulting in greater variation in the duty ratio.
本発明は上記の事情に鑑みてなされたもので、
出力トランジスタの負荷短絡時における遮断、復
帰制御に際して出力トランジスタの出力電流のオ
ン、オフ期間のデユーテイ比をほぼ一定に設定す
ることができ、出力電流のオン期間を大きくする
必要がある場合でも上記デユーテイ比をほぼ一定
に設定し得る高出力用集積回路の出力トランジス
タ保護回路を提供するものである。
The present invention was made in view of the above circumstances, and
The duty ratio of the on/off period of the output current of the output transistor can be set almost constant when the output transistor is cut off and restored when the load is short-circuited. An object of the present invention is to provide an output transistor protection circuit for a high-output integrated circuit that can set the ratio substantially constant.
即ち、本発明は、出力トランジスタの負荷短絡
時を検出して出力トランジスタをオフ状態に制御
したのち、再び自動的に出力トランジスタをオン
状態に復帰させるための高出力用集積回路の出力
トランジスタ保護回路において、負荷に電流を供
給する出力トランジスタと、この出力トランジス
タを駆動制御する駆動制御回路と、前記出力トラ
ンジスタの出力電流を監視してその負荷短絡時を
検出する短絡電流検出回路と、この短絡電流検出
回路の検出出力によつて所定の定電流を出力する
ように制御される第１の定電流源と、この第１の
定電流源の出力端に接続される充放電用コンデン
サと、このコンデンサ並列接続され、前記第１の
定電流源からの出力電流の一部または上記コンデ
ンサからの放電電流が流れる第２の定電流源と、
前記コンデンサの端子電圧が第１の基準電圧より
高い場合、前記出力トランジスタをオフさせるた
めの信号を前記駆動制御回路に供給し、前記コン
デンサの端子電圧が前記第１の基準電圧より低い
第２の基準電圧に比べて低い場合、前記出力トラ
ンジスタをオンさせるための信号を前記駆動制御
回路に供給する比較回路とを具備することを特徴
とするものである。
That is, the present invention provides an output transistor protection circuit for a high output integrated circuit, which detects a load short circuit of an output transistor, controls the output transistor to an OFF state, and then automatically returns the output transistor to an ON state. , an output transistor that supplies current to a load, a drive control circuit that drives and controls the output transistor, a short-circuit current detection circuit that monitors the output current of the output transistor and detects when the load is short-circuited, and the short-circuit current A first constant current source controlled to output a predetermined constant current by the detection output of the detection circuit, a charging/discharging capacitor connected to the output terminal of the first constant current source, and this capacitor. a second constant current source connected in parallel, through which a part of the output current from the first constant current source or a discharge current from the capacitor flows;
If the terminal voltage of the capacitor is higher than the first reference voltage, a signal for turning off the output transistor is supplied to the drive control circuit; The present invention is characterized by comprising a comparison circuit that supplies a signal for turning on the output transistor to the drive control circuit when the voltage is lower than a reference voltage.
以下、図面を参照して本発明の一実施例を詳細
に説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は高出力用集積回路の一部を示してお
り、１はVcc電源電圧が印加される電源端子、２
は接地端子、３入力端子、４は出力端子である。
５は上記入力端子３からの入力信号に応じて後述
する出力トランジスタ６を駆動するための駆動信
号を発生すると共に、後述する比較器７からの比
較判定出力に応じて上記駆動信号のオン、オフ期
間が制御される駆動制御回路である。上記出力ト
ランジスタ６はNPN形のバイポーラトランジス
タからなり、そのコレクタは電流リミツタ回路８
を介して電源端子１に接続され、そのベースには
前記駆動信号に印加され、そのエミツタは前記出
力端子４に接続されている。９は上記出力トラン
ジスタ６のエミツタに接続されてそのエミツタ電
流（出力電流）を監視し、上記出力トランジスタ
６の負荷短絡時を検出する短絡電流検出回路であ
る。１０は上記検出回路９の検出出力がベースに
印加されてオン状態に制御されるたとえばPNP
形のスイツチ用トランジスタであり、そのエミツ
タは前記電源端子１に接続され、そのエミツタは
定電流I1を流すための第１の定電流源１１を介し
たのち、充放電用コンデンサ１２および定電流I2
（＜I1）を流すための第２の定電流源１３を並列
に介して接地端子２に接続されている。そして、
前述の比較器７は、上記コンデンサ１２の端子電
圧Vcを２個の閾値電圧VTH1，VTH2（但し、VTH1＜
VTH2）と比較し、VcがVTH2を越えて高くなつた
ときにハイレベルからロウレベルに反転し、Vc
がVTH1を越えて低くなつたときにロウレベルから
ハイレベルに反転する比較判定出力を発生する。
ここで、上記比較器７は、たとえばヒステリシス
特性を持つシユミツトトリガ回路が用いられ、
VTH1は入力電圧降下時の閾値電圧、VTH2は入力電
圧上昇時の閾値電圧である。 Figure 1 shows part of a high-power integrated circuit, where 1 is a power supply terminal to which Vcc power supply voltage is applied, 2 is a power supply terminal to which Vcc power supply voltage is applied;
is a ground terminal, 3 is an input terminal, and 4 is an output terminal.
5 generates a drive signal for driving an output transistor 6, which will be described later, in response to an input signal from the input terminal 3, and turns the drive signal on or off in accordance with a comparison judgment output from a comparator 7, which will be described later. This is a drive control circuit whose period is controlled. The output transistor 6 is an NPN type bipolar transistor whose collector has a current limiter circuit 8.
is connected to the power supply terminal 1 via the base thereof, the drive signal is applied to its base, and its emitter is connected to the output terminal 4. Reference numeral 9 denotes a short-circuit current detection circuit connected to the emitter of the output transistor 6 to monitor the emitter current (output current) and detect when the load of the output transistor 6 is short-circuited. 10 is a PNP, for example, which is controlled to be turned on by applying the detection output of the detection circuit 9 to its base.
The emitter is connected to the power supply terminal 1, and the emitter is connected to the charging/discharging capacitor 12 and the constant current source 11 through the first constant current source 11 for flowing the constant current I1. I 2
(<I 1 ) is connected to the ground terminal 2 via a second constant current source 13 in parallel. and,
The above-mentioned comparator 7 converts the terminal voltage V c of the capacitor 12 into two threshold voltages V TH1 and V TH2 (where V TH1 <
V TH2 ), when V c rises above V TH2 , it reverses from high level to low level, and V c
Generates a comparison judgment output that inverts from low level to high level when V TH1 becomes lower than V TH1.
Here, the comparator 7 uses, for example, a Schmitt trigger circuit having hysteresis characteristics,
V TH1 is the threshold voltage when the input voltage drops, and V TH2 is the threshold voltage when the input voltage increases.
次に、上記構成における動作を第３図を参照し
て説明する。正常動作状態においては、入力端子
３からの入力信号に応じて出力トランジスタ６が
負荷（出力端子４に接続される）を駆動する。こ
の状態のとき、スイツチ用トランジスタ１０はオ
フ状態であり、コンデンサ１２の端子電圧Vcは
ほぼ0Vであり、比較器７の判定出力はハイレベ
ルであり、駆動制御回路５は通常動作を行なつて
いる。これに対して、出力トランジスタ６の負荷
短絡時には、電流リミツタ回路８によつて出力電
流I0の上限値が制限されると共に、短絡電流検出
回路９による検出出力によつてスイツチ用トラン
ジスタ１０がオン状態に制御される。これによつ
て、第１の定電流源１１に電流流が流れ始め、I1
＞I2に設定されているので、（I1−I2）なる電流に
よりコンデンサ１２が充電され始め、その端子電
圧Vcが次第に上昇する。この端子電圧Vcが比較
器７の第２の閾値電圧VTH2を越えて高くなると、
比較半定出力がロウレベルに反転し、これによつ
て駆動制御回路５は駆動信号をオフにするので出
力トランジスタ６がカツトオフ状態になる。これ
によつて、出力電流I0は零になり、短絡電流検出
回路９の短絡検出は行われなくなり、スイツチ用
トランジスタ１０はオフ状態になる。これによつ
て、コンデンサ１２の電荷は第２の定電流源１３
を通じて放電を開始し、その端子電圧Vcは次第
に降下する。この端子電圧Vcが比較器７の第１
の閾値電圧VTH1を越えて低くなると、比較判定出
力がハイレベルに反転し、これによつて駆動制御
回路５は通常動作に戻る。そして、出力トランジ
スタ６に再び出力電流が流れ始め、このとき依然
として負荷短絡状態が続いていれば、前述したよ
うな短絡電流検出からロウレベルの比較判定出力
発生までの一連の動作を繰り返す。 Next, the operation of the above configuration will be explained with reference to FIG. In normal operating conditions, the output transistor 6 drives a load (connected to the output terminal 4) in response to an input signal from the input terminal 3. In this state, the switch transistor 10 is off, the terminal voltage V c of the capacitor 12 is approximately 0V, the judgment output of the comparator 7 is at a high level, and the drive control circuit 5 performs normal operation. ing. On the other hand, when the load of the output transistor 6 is short-circuited, the upper limit value of the output current I0 is limited by the current limiter circuit 8, and the switching transistor 10 is turned on by the detection output from the short-circuit current detection circuit 9. controlled by the state. As a result, a current begins to flow through the first constant current source 11, and I 1
>I 2 , the capacitor 12 begins to be charged with a current of (I 1 −I 2 ), and its terminal voltage V c gradually increases. When this terminal voltage V c becomes higher than the second threshold voltage V TH2 of the comparator 7,
The comparative semi-constant output is inverted to a low level, whereby the drive control circuit 5 turns off the drive signal, so that the output transistor 6 is in a cut-off state. As a result, the output current I 0 becomes zero, the short circuit detection circuit 9 no longer detects a short circuit, and the switching transistor 10 becomes OFF. As a result, the charge on the capacitor 12 is transferred to the second constant current source 13.
The terminal voltage Vc gradually drops. This terminal voltage V c is the first voltage of comparator 7.
When the voltage becomes lower than the threshold voltage V TH1 , the comparison judgment output is inverted to a high level, and the drive control circuit 5 returns to normal operation. Then, the output current begins to flow through the output transistor 6 again, and if the load short-circuit condition continues at this time, the series of operations from short-circuit current detection to generation of a low-level comparison judgment output as described above is repeated.
上記出力トランジスタ保護回路においては、負
荷短絡検出によつてコンデンサ１２が充電を開始
して、その端子電圧VcがVTH1からVTH2まで上昇
する所要時間T1は充電電流（I1−I2）に依存す
る。また、出力トランジスタ６がカツトオフされ
ると共にスイツチ用トランジスタ１０もカツトオ
フされることによつて、コンデンサ１２の放電を
開始してその端子電圧VcがVTH2からVTH1まで降
下する所要時間T2は放電電流I2に依存する。この
場合、（I1−I2）＞I2となるように設定されており、
上記時間T1，T2が出力電流I0のオン、オフ期間
に相当する。即ち、オン、オフ期間のデユーテイ
比は、前記電流（I1−I2），I2の比に依存し、これ
は２個の定電流源１１，１３が同一チツプ上に形
成されているので、定電流I1，I2のばらつきがあ
つても互いに比例関係を持つようになり、ほほ一
定のデユーテイ比が得られる。また、出力電流の
オン期間は定電流I1，I2の選択によつて任意（た
とえば50〜200μs）に設定可能であり、ランプ等
の容量性負荷を駆動する場合が都合が良い。 In the above output transistor protection circuit, the time T 1 required for the capacitor 12 to start charging upon detection of a load short circuit and for its terminal voltage V c to rise from V TH1 to V TH2 is equal to the charging current (I 1 − I 2 ). Further, when the output transistor 6 is cut off and the switch transistor 10 is also cut off, the time T 2 required for the capacitor 12 to start discharging and for its terminal voltage V c to drop from V TH2 to V TH1 is Depends on the discharge current I 2 . In this case, it is set so that (I 1 − I 2 ) > I 2 ,
The above times T 1 and T 2 correspond to on/off periods of the output current I 0 . That is, the duty ratio of the on and off periods depends on the ratio of the currents (I 1 - I 2 ) and I 2 , and this is because the two constant current sources 11 and 13 are formed on the same chip. Even if there are variations in the constant currents I 1 and I 2 , they will have a proportional relationship with each other, and a nearly constant duty ratio can be obtained. Further, the on-period of the output current can be arbitrarily set (for example, 50 to 200 μs) by selecting the constant currents I 1 and I 2 , and is convenient when driving a capacitive load such as a lamp.
上述したように本発明の高出力用集積回路の出
力トランジスタ保護回路によれば、出力トランジ
スタの負荷短絡時における遮断、復帰制御に際し
て出力トランジスタの出力電流のオン、オフ期間
のデユーテイ比をほぼ一定に設定することがで
き、出力電流のオン期間を大きくする必要がある
場合でも上記デユーテイ比をほぼ一定に設定する
ことができる利点がある。
As described above, according to the output transistor protection circuit of the high output integrated circuit of the present invention, the duty ratio of the output current of the output transistor during the on and off periods can be kept almost constant during cutoff and recovery control when the output transistor is short-circuited. There is an advantage that the duty ratio can be set substantially constant even when it is necessary to increase the on-period of the output current.
第１図は本発明に係る高出力用集積回路の出力
トランジスタ保護回路の一実施例を示す構成説明
図、第２図は第１図の動作説明のために示す信号
波形図である。
３…駆動制御回路、６…出力トランジスタ、７
…比較器、９…短絡電流検出回路、１１…第１の
定電流源、１２…コンデンサ、１３…第２の定電
流源。
FIG. 1 is a configuration explanatory diagram showing one embodiment of an output transistor protection circuit for a high-output integrated circuit according to the present invention, and FIG. 2 is a signal waveform diagram shown for explaining the operation of FIG. 1. 3... Drive control circuit, 6... Output transistor, 7
... Comparator, 9... Short circuit current detection circuit, 11... First constant current source, 12... Capacitor, 13... Second constant current source.
Claims (1)
回路と、 前記出力トランジスタの出力電流を監視してそ
の負荷短絡時を検出する短絡電流検出回路と、 この短絡電流検出回路の検出出力によつて所定
の定電流を出力するように制御される第１の定電
流源と、 この第１の定電流源の出力端に接続される充放
電用コンデンサと、このコンデンサに並列接続さ
れ、前記第１の定電流源からの出力電流の一部ま
たは上記コンデンサからの放電電流が流れる第２
の定電流源と、 前記コンデンサの端子電圧が第１の基準電圧よ
り高い場合、前記出力トランジスタをオフさせる
ための信号を前記駆動制御回路に供給し、前記コ
ンデンサの端子電圧が前記第１の基準電圧より低
い第２の基準電圧に比べて低い場合、前記出力ト
ランジスタをオンさせるための信号を前記駆動制
御回路に供給する比較回路と を具備することを特徴とする高出力用集積回路の
出力トランジスタ保護回路。[Scope of Claims] 1. An output transistor that supplies current to a load, a drive control circuit that drives and controls the output transistor, and a short-circuit current detection circuit that monitors the output current of the output transistor and detects when the load is short-circuited. a first constant current source that is controlled to output a predetermined constant current by the detection output of the short circuit current detection circuit; and a charging/discharging source connected to the output terminal of the first constant current source. a second capacitor connected in parallel to the capacitor, through which part of the output current from the first constant current source or the discharge current from the capacitor flows;
a constant current source that supplies a signal to the drive control circuit to turn off the output transistor when the terminal voltage of the capacitor is higher than the first reference voltage; An output transistor of a high output integrated circuit, comprising: a comparison circuit that supplies a signal for turning on the output transistor to the drive control circuit when the voltage is lower than a second reference voltage lower than the second reference voltage. protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127275A JPS6019313A (en) | 1983-07-13 | 1983-07-13 | Output transistor protection circuit of integrated circuit for high output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127275A JPS6019313A (en) | 1983-07-13 | 1983-07-13 | Output transistor protection circuit of integrated circuit for high output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6019313A JPS6019313A (en) | 1985-01-31 |
| JPH0473326B2 true JPH0473326B2 (en) | 1992-11-20 |
Family
ID=14955952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58127275A Granted JPS6019313A (en) | 1983-07-13 | 1983-07-13 | Output transistor protection circuit of integrated circuit for high output |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6019313A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL9201053A (en) * | 1992-06-15 | 1994-01-03 | Koninkl Philips Electronics Nv | SWITCHED CAPACITOR LOADING PUMP AND SAW Tooth Oscillator equipped with such a SWITCHED CAPACITOR LOADING PUMP. |
| JP2009513011A (en) * | 2005-10-19 | 2009-03-26 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Color lighting device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53144650A (en) * | 1977-05-23 | 1978-12-16 | Mitsubishi Electric Corp | Saw-tooth wave generator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5674534U (en) * | 1979-11-09 | 1981-06-18 |
-
1983
- 1983-07-13 JP JP58127275A patent/JPS6019313A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53144650A (en) * | 1977-05-23 | 1978-12-16 | Mitsubishi Electric Corp | Saw-tooth wave generator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6019313A (en) | 1985-01-31 |
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