JPS5839283A - Timer circuit for driving base of transistor inverter - Google Patents

Abstract

PURPOSE:To obtain accurate time limit of base-ON signals and applying period of reverse bias by determining the time limit of the base-ON signals and the applying time of the reverse bias while being made depend upon reference level voltage supplied to the input side of a comparator. CONSTITUTION:A time limit circuit for ON-delay is formed by a time-constant circuit 31 and a comparator 32. The input side of the time-constant circuit 31 is connected to an input terminal 34 through an AND gate 33, and the output side is connected to the non-inversion input terminal of the comparator 32. The comparator 32 compares the level of signals from the time-constant circuit 31 and a reference voltage level from a reference voltage generator 35. A time limit circuit for reverse bias has the time-constant circuit 31 and a comparator 36. The comparator 36 compares the signal level from the time-constant circuit 31 and the reference voltage level from the reference voltage generator 35. A comparators 39, 40 are formed similarly, transistors 42, 45, 48, 51 are controlled by these output, and base signals and reverse bias signals to a main transistor are outputted.

Description

[Detailed description of the invention]

The present invention relates to a timer circuit, and particularly to a timer circuit 1MK for driving the base of a transistor inverter. Conventionally, a Lange inverter is known as a device for converting DC power into AC power. FIG. 1 shows a circuit of an eyeball-shaped filter phase output transistor inverter, which is a typical inverter of this type. In FIG. 1, six switching transistors T1 to T6 of the same type are bridge-connected, and opposite transistors T and T
, T and T, and T6 and 1 4 2 5 T6, 6-phase output terminals R, S, and T are drawn out from the respective midpoints. In such a voltage type inverter (2), in order to obtain the same output voltage under any load conditions, the opposing transistors, such as the transistor T1, are turned on at one time.

[ru. And this and Sunset; 5< t, c 1l
d1 (with a delay of 120° and 240°)
and T5, and transistors T6 and T6, respectively7
17ru. Therefore, in such a transistor innovator, the switching characteristics of each transistor are important, and in particular, it is necessary to consider the carrier accumulation effect when the transistor is off. Generally, a transistor that is conducting and in a saturated state does not immediately shut off even when the base current is turned off, and a so-called accumulation time carrier current continues to flow. Even if a reverse bias is applied, the accumulation time cannot be reduced to zero. Therefore, even if the base current of transistor T1 is turned off, for example, in both transistors 'l'++T4, transistor T1 is substantially in a conductive state during the accumulation time, so that it is immediately possible to prevent a DC short circuit. (3) Normally, the base signal for transistor T4 has a time limit that takes into account the storage time. In addition to this, a reverse bias is applied between the base and emitter of the transistor T1. If this reverse bias remains applied during the OFF period of the transistor T1, the loss of the base driving timer circuit will increase, so it is generally applied for a predetermined period until slightly beyond the OFF period. FIG. 2 shows a conventional timer circuit for driving the base of a transistor inverter in consideration of the above accumulation effect. Second
In the figure, 1 and 2 are on-delay time circuits and reverse bias circuits 1j and 1j (circuits) respectively connected to the main tracker/star T1.
This is for giving a predetermined time limit to the base signal for the input signal, and is composed of AND gates 1-3 and 4, which are made up of two human operators, and a time constant circuit 5. The input side of the AND gate 6 is connected to the input terminal, and the output side is connected to the input terminal of the time constant circuit 50, and the output side of the time constant circuit 5 is connected to the input terminal of the HAND gate 40. (4) Now, when a reference pulse signal a as shown in FIG. The time constant circuit 5 has a time constant determined by R1101 to blunt the rise of the pulse signal 21. As a result, the output side TIK- of the time constant circuit 5 receives a signal 1) as shown in FIG. The AND gate 4 has threshold values 1 and 1, and when the signal 1 rises and reaches the threshold 1 T1, it generates a low level output voltage, but the signal 1]
When exceeds the threshold value ■T1, a high level output voltage is generated. As a result, a signal G as shown in FIG. 6G is obtained from the output of the AND gate 4. The rise of this signal Glri is delayed with respect to the signal a by a time t1 from when the signal starts to rise until it reaches the threshold value (1). This signal C- is a base signal having a time period t1,
Transistor 7I is supplied via pulse transformer 8 to the base of main transistor T1. The reverse bias time circuit 2 is for forming a reverse bias signal for the transistor T1 (5), and is configured as an IC monostabilized multivibrator consisting of logic games 1-9, 10, and 11 and a time constant circuit 12. has been done. Input terminal of NAND gate 9 1 AND gate 6
The output side of the NAND gate 9 is directly connected to one input terminal of the NAND gate, and is also connected to the input side of the time constant circuit 12, and the output side of the time constant circuit 12 is connected to the input terminal 6 via the NAND gate. It is connected to the input side of the gate 11 , and the output side of the NAND gate 11 is connected to the other input end of the HAND gate 10 . Now, when the base signal C of the transistor T1 is turned off, a low level base signal a is supplied to the input side of the NAND gate 9. NAND gate 9 inverts this signal a and generates a high level inverted signal d as shown in FIG. 3DK. This signal d u A is supplied to one input side of the AND gate 10 and also to the time constant circuit 12 . The time constant circuit 12 smoothes the rise of the signal d using a time constant determined by R2 and C2. As a result, a signal e as shown in FIG. 6E is obtained on the output side of the time constant circuit 12 (6).
This signal e Id N A N D G 1-11 K is supplied. NAND gate 11, threshold value
'2 is the threshold value V, r
It generates a high level output voltage when it reaches 2Vc, but
When the number of months (・ exceeds the threshold ■T2, the output type r-] of the low 1 novel occurs, r, r. Sono result, output side KH of NAND game 1-11 Figure 6 F
Obtain the signal shown in ``This signal [is AND
The other input terminal of the gate 10 is supplied with (Jt) and is ANDed with one input signal (1.
From the output 1ll of the D gate 10, a signal g as shown in FIG. This signal g breaks the pulse width 12 at 1 which reaches the threshold value V,..., 2Vc after the signal e starts to rise, and is used as a reverse bias signal to connect the base of the main transistor T1 through the transistor 1 and the pulse transformer 14. Supplied between emitters. The base signal and reverse bias signal for the main transistor T4Vc are obtained by an on-delay timer circuit 15 and a reverse bias timer circuit 16, respectively]1. reactor. (7) The time limit circuits 15 and 16 have the same structure as the above-described time limit circuits 1 and 2 connected to the transistor T1, respectively, and operate in the same manner. However, the reference pulse signal from the input terminal 6 is inverted by the NAND gate 17, and the human power
To avoid this, time limit circuits 15 and 16C are constructed with a phase shift of 180° relative to time limit circuits 1 and 2, respectively. As a result, when the base signal is supplied from the timer circuit 1 to the main transistor T1, a reverse bias signal is supplied from the timer circuit 16 to the main transistor T4, and a reverse bias signal is supplied from the timer circuit 2 to the main transistor T1. At this time, a base signal is supplied from the timer circuit 15 to the main transistor T2. In addition, in Fig. 2, the Zener diode is 18°20[
This is to block the flow of current into the forward bias pulse transformers 8 and 22 when the transistors T11 and T4 are reverse biased, and the Zener diodes 19 and 21 (IJ,
This is to prevent current from flowing into the reverse bias pulse transformers 14 and 23 during the l1ll'i bias. -1 In a series of conventional base drive timer circuits, (
8) The timing of the base signal and the pulse width of the reverse bias signal depend on the threshold of the logic gate. In other words, the time limit t1 of the base signal is the time from when the signal 1) begins to rise until it reaches the threshold value V, 1.1 of the AND gate 4, and the pulse width I2 of the reverse bias signal is This is the time from when the signal e starts rising to when it reaches the threshold value ②T2 of the NAND gate 11. However, the threshold values of individual logic gates generally have fluctuations and fluctuate with changes in ambient temperature. For this reason, in the conventional base driving timer circuit, the time limit of the base signal and the application period of the reverse bias become inaccurate or fluctuate, making it impossible to perform stable switching. Furthermore, according to the conventional base drive timer circuit, each main transistor is provided with a separate on-delay timer circuit and a reverse bias timer circuit, which not only increases the number of circuit components but also increases the cost. ,
Coupled with the above fluctuations in the threshold value, it has been difficult to provide consistency to the output waveforms of both time-limiting circuits. The present invention was made in view of the above-mentioned problems(9), and it makes the time limit of the base signal and the application period of the reverse bias accurate, provides good matching between the two, and simplifies the circuit and reduces the cost. We provide a timer circuit for driving the base of a transistor inverter that reduces the below,
The invention will now be described with reference to preferred embodiments. FIG. 4 is a circuit diagram of a timer circuit for driving the base of a transistor inverter according to an embodiment of the present invention. Fourth
In the figure, the on-delay time circuit according to the present invention is
It is composed of a time constant circuit 61 and a comparator 2. The time constant circuit 1 has an ordinary circuit configuration consisting of a resistor R6°, a capacitor C6, and a diode D6, and has a time constant determined by R5+05. The time constant circuit 31 (III) is connected to the input terminal 4 via the AND gate 3, and its output side is connected to the comparator 62.
is connected to the non-inverting input terminal of The comparator 62 is 61(
It has a circuit configuration that destroys an operational amplifier, and a constant voltage of N/i voltage is supplied from a reference voltage generator 65 to its inverting input terminal. As a result, the comparator 32 is controlled by the time constant circuit 61.
The signal level is compared with the reference voltage (10) level 1, and if the former is thicker than the latter, a high-level output voltage is generated, and in other cases, a low-level output voltage is generated. ing. Further, the reverse bias time limit circuit according to the present invention includes a time constant circuit 61 and a comparator 66. The output side of the time constant circuit 61 is connected to the inverting input terminal of the comparator 66,
A constant reference voltage IEV2 is supplied from the reference voltage generator 65 to the non-inverting input terminal of the comparator 66. The output side of the comparator 66 has an open collector configuration, and the collector of the output transistor (not shown) is connected to the input end of the time constant circuit 31 via a resistor 67 instead of being connected to a power supply. As a result, the comparator filter 6 outputs a high level when the level of the signal from the time constant circuit 61 is lower than the reference voltage LL level 2 and a high level voltage is supplied to the input terminal of the time constant circuit 61. elL, and is otherwise configured to generate a low level output voltage. The reference voltage generator 65 consists of a resistor dividing circuit, and from its resistance ratio, '14'LL1:, ■1, ■ of the connection point XIy.
2 is required. As will be described later, the reference voltage V1 determines the time limit of the base-on signal, and the reference voltage V2 determines the pulse width of the reverse bias signal. Normal Meat Standard 'Ichida■1・V and 2 should have a relationship of V1≦■2. The above is an on-delay time circuit for the transistor T1 and a reverse bias time circuit for the transistor T4Vc. The on-delay time circuit for the transistor T4 is composed of a time constant circuit 68 and a comparator 69, and the reverse bias time circuit for the transistor T1Vc is composed of a time constant circuit 8 and a comparator 40. These time constant circuits8. Comparators 69 and 40 irj: have the same configuration as the time constant circuit 31 and comparators 32 and 36 described above, respectively, and operate in the same manner. However, since the input reference pulse signal HNAND gate 1-41 is inverted and supplied, their operation a is 180° out of phase with respect to the circuit described above. As a result, when a base-on signal is supplied to the main transistor T1, a reverse bias signal is supplied to the main transistor T4, and when a reverse bias signal is supplied to the main transistor T1, a base-on signal is supplied to the main transistor T4. 't,C is done like this. Next, the operation of the base driving timer circuit configured as described above will be explained. In this case, when the reference pulse signal 11 as shown in FIG. 5 is input from the input terminal 64 at time 14, this signal h The time constant circuit 31 slows down the rising speed of the signal 11 with a time constant determined by R5*Gy.As a result, the time constant circuit 6
On the output side of the signal 1, a signal 1 with a single rising edge as shown in Figure 5 is obtained. This is true. Comparator 32Iri generates a low level output voltage when signal 1 rises and reaches reference voltage V1, but at time tB
A high level output voltage is generated after the signal i exceeds the reference voltage level V1 until it is turned off. the result,
From the output side of the comparator 32, a signal J whose rise is delayed at time t1 (from time tA to 13t) with respect to the reference pulse signal is obtained as shown in FIG. 5J(13). This signal] is applied to transistor 42. as a base-on signal with a time limit t1. Pulse transformer 46. It passes through the Zener diode 44 and is supplied to the base of the main transistor T1, turning on the transistor T1. On the other hand, in the comparator 6, its non-inverting input terminal is at a low level before the signal l is supplied, but at this time, the output side of the comparator 66 is at an off level, that is, a low level, through a resistor 7. In order to receive the reference pulse signal 11, a low level output voltage is generated. However, when the signal i is supplied at time tA, the reference pulse signal becomes on level, that is, high level. As a result, time t
Time t when signal 1 rises from A and reaches base ff/L voltage 2. Until then, comparator 66 produces a high level output voltage. Then, when the signal i becomes thicker than the reference voltage level 2 after time tc, the comparator 66 again generates a low level output voltage. As a result, the output of the comparator 36 (14
) side, as shown in FIG. 5K, a signal K having a pulse width t2 at 1° from time IA is obtained. This signal is applied to the transistor 45. as a reverse bias signal having an application period t2. Pulse transformer 46. zener diode 4
7 and is supplied to the base of the main transistor T4 to facilitate turning off the transistor T4. After that, at time tD, the pulse signal 11 and the base on signal j
When the signal becomes off level, the other time constant circuit 68 receives an on level signal t (FIG. 5L) obtained by inverting the pulse code 11 by the NAND gate 41. As a result, exactly the same operation as described above is performed by the time constant circuit 68 and both comparators 9.40. That is, from the output side of the time constant circuit 8, as shown in FIG. 5M, 1. A signal m with a distorted rising edge is obtained, and r is sent to the output side of the comparator filter 9.
[Time 11 for pulse signal t (from time '11 to 11
The signal n (N in Figure 5) with a delayed rise (at 2 inches) becomes 1 ([
7, and the output side of the comparator 40 has a pulse width of 12 (time 1
□, at tF4), the signal o (O in Figure 5) is 1
4) ") fl-ru. And the signal n, the base on signal with time period 11 run raster 48. Pulse transformer 49 through Zener diode 50 main transistor T4 (7) base); supplied, transistor 14 The output signal 0 is applied as a reverse bias signal during the application period t2, and the transistor 51, pulse transformer 52, and Zener diode 5 are turned on.
6 and is supplied to the base of the main transistor T1 to facilitate turning off the transistor T1. 1f, the time limit t1 of the base-on signal and the pulse width t2 of the reverse bias signal are based on the reference voltage 1. (2) Each can be adjusted by changing 2, and an appropriate value is selected in consideration of the storage time and the time when the main transistor is off. The configuration and operation of the base drive timer circuit according to an embodiment of the present invention have been described above, but the present invention has the following advantages compared to the conventional base drive timer circuit.
do. First, in the present invention, the time constant circuit for obtaining the base-on signal and the time constant circuit for obtaining the reverse bias signal are shared by a second time constant circuit. For this reason,
The circuit configuration is simplified, the cost can be reduced, and it is easy to provide consistency between the time period of the base-on signal and the time period of the reverse bias signal. Further, according to the present invention, the time limit of the base on signal and the application period of the reverse bias do not depend on the threshold value of the logic gate as in the conventional base driving timer circuit, but on the other manual side of the comparator. Depends on the constant reference level voltage provided. Therefore, accurate time limits and application periods can be obtained.
The adjustment time required in the past is no longer required, and stable operation can be achieved against changes in ambient temperature, etc. Note that the present invention is applicable not only to a voltage source six-phase output transistor inverter, but also to a VVVF inverter configured by bridge-connecting transistors, a CVCF inverter, a bridge-connecting transistor chopper for transistor servo, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an electric current type six-phase output transistor inverter to which the present invention is used, (17) FIG.
3 is a signal waveform diagram of each part of the circuit of FIG. 2. FIG. 4 is a circuit diagram of a timer circuit for driving the base of a transistor inverter according to an embodiment of the present invention. FIG. 5 is a signal waveform diagram of each part of the circuit of FIG. 4. 61, Ro8... Time constant circuit 32. Ro6・Ro9
, 40... Comparator, 65... Reference voltage generator Ti, T4... Main transistor. Patent applicant Fuji Electric Manufacturing Co., Ltd. (18)

Claims (1)

[Claims] A base-on signal is supplied to the base of the other transistor at a predetermined time period after the base current of one of the opposing transistors of the bridge inverter is turned off, and a base-on signal is supplied to the base of the other transistor for a predetermined period after the base current is turned off. A time constant circuit for delaying the rise of a reference pulse signal by a fixed time constant in a timer circuit for driving the base of a transistor inverter that switches the on state from the one transistor to the other transistor by supplying a reverse bias to the base of the transistor. Then, the output signal of the time constant circuit and the first reference level signal are manually adjusted so that the level of the output signal becomes the first reference level signal.
a first comparator that generates a high level output voltage only when the output voltage is thicker than a reference level; the output signal of the time constant circuit and a second reference level signal are inputted, and the reference pulse signal (1) is and a second comparator that generates a high level output voltage only when the level of the output signal is lower than the second reference level and the reference pulse signal is at a high level, A timer circuit for driving a base, characterized in that the base-on signal is obtained from the output side of a comparator, and the reverse bias signal is obtained from the output side of the second comparator.