JP2002344296A - Overheat protection circuit and power transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an overheat protective circuit, in which abrupt temperature rise of a PTr is suppressed, even if overcurrent flows due to short circuit of the load of the PTr and the PTr can be turned off completely, when the temperature thereof rises up to a limit level which can possibly cause breakdown, and a power transistor comprising the overheat protection circuit. SOLUTION: The overheat protection circuit 1 comprises a PWM control means 3, a selection control means 5, and a means 7 for detecting short- circuiting of load. The PWM control means 3 comprises an oscillation unit 31, an LPF unit 35 and a temperature-detecting section 33 provided in the vicinity of a PTr, i.e., an NMOS 10. The pulse width of an output signal from the oscillation unit 31 is controlled, depending on the temperature of the NMOS 10 detected at the temperature detecting section 33, so that LPF unit 35 outputs a signal, in response to an input signal, only when a signal having a pulse width longer than a specified time interval is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overheat protection circuit for a power transistor (hereinafter, PTr), and particularly to a PTr.
The present invention relates to an overheat protection circuit when a PTr is overheated due to a short circuit occurring in a driven load, and a PTr having the overheat protection circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional PTr protection circuit.

A conventional PTr protection circuit includes an overheat protection circuit 518 and an overcurrent protection circuit 519.

Next, the operation will be described. Overheat protection circuit 518
Is a diode 5 near an n-channel field effect transistor (hereinafter referred to as NMOS) 522 which is a PTr.
20, the potential of the node M1 is
When the temperature of the node 22 rises to a predetermined temperature T1, the potential of the node M1 falls below the potential of the node M2, which is the reference potential. Thereby, the comparison circuit 53
1 is inverted from the low level to the high level and the NMO
S521 is turned on and NMOS5 which is an output PTr is turned on.
22 is forcibly turned off. At this time, the NMOS 52
3 is turned on, the potential of the node M1 further drops, and the NMOS 5 is turned on until the PTr drops to a certain temperature T2 (<T1).
Reference numeral 22 turns off. As a result, a hysteresis characteristic with respect to the temperature of the NMOS 522 is provided.

The overcurrent protection circuit 519 includes an NMOS 522
The voltage applied between the drain terminal (D) and the source terminal (S) is divided by the resistors 524 and 525, and the NMOS 526 is driven by the divided voltage of the node M5. NM
When a load (not shown) connected to the OS 522 is short-circuited, the voltage applied between the drain terminal (D) and the source terminal (S) of the NMOS 522 increases, so that the voltage of the node M5 also increases, and the NMOS 526 is turned on. I do. By this operation, the gate voltage of the NMOS 522 is controlled, and the NMOS 5
22 is suppressed.

[0006]

In the above-described conventional overheat protection circuit 518, when the PTr is turned on by an input signal input to the input terminal (IN) in a state where the load is short-circuited, the temperature of the PTr becomes low. The temperature rises rapidly and reaches the temperature T1 at which the overheat protection is performed at a stretch. Once the temperature reaches the temperature T1, the PTr is not turned on unless it decreases to a certain temperature T2. Thus, PTr is at a certain temperature T
In a configuration that is suddenly turned off at 1 and cannot be turned on until the temperature T2 becomes sufficiently lower, for example, this PT
If r is used to drive the lamp, the lamp suddenly goes out,
Relighting cannot be performed until a certain time has elapsed, and this is a serious problem particularly in applications such as automotive lamps.

Further, only the conventional overcurrent protection circuit 519 is used for the NMOS 522 which is a PTr as shown in FIG.
In order to control the drain current of the NMOS 522, it is necessary to control the gate voltage of the NMOS 522 according to the voltage applied between the drain terminal (D) and the source terminal (S) of the NMOS 522, and the resistors R24 and R25, the transistor 526, and It was very difficult to set constants for elements such as the diode 528.

An object of the present invention is to provide a simple circuit configuration to prevent a rapid rise in temperature of a PTr even if an overcurrent flows due to a short-circuit condition of a load driven by the PTr without a delicate element constant setting. The overheating protection circuit and the overheating protection circuit which can suppress the PTr and completely increase the time until the PTr is completely turned off, and further can completely turn off the PTr when the temperature rises to a limit temperature at which the PTr may be broken. It is intended to provide a power transistor.

[0009]

According to the present invention, there is provided an overheat protection circuit comprising: a drive transistor having at least a drive input terminal, a control input terminal, and a drive control output terminal. An overheat protection circuit for the power transistor, which is connected to an electrode and outputs a drive signal input to the drive input terminal from the drive control output terminal based on a control signal input to the control input terminal and drives a predetermined load. And at least load short-circuit detection means, pulse width modulation (hereinafter, referred to as PWM) control means, and selection control means, wherein the load short-circuit detection means is provided with a predetermined load driven by the power transistor. The short-circuit detection signal is output from the short-circuit detection output terminal upon detecting that the power supply is short-circuited.
PWM of a pulse width signal corresponding to the temperature of the transistor section
Output from an output terminal, and when the temperature of the power transistor section exceeds a predetermined temperature Tc, a first temperature detection signal is output from a temperature detection output terminal. Detection result input end, 2nd
A detection result input terminal and a selection control output terminal;
A signal input to the selection input terminal is controlled to be output from the selection control output terminal in accordance with a signal input to the detection result input terminal and the second detection result input terminal, and the PWM output terminal is connected to the selection input terminal. Terminal, the short-circuit detection output terminal is connected to the first detection result input terminal, the temperature detection output terminal is connected to the second detection result input terminal, and a third selection control output terminal of the selection control means is connected. Is connected to a control input terminal of the switch means.

At this time, the PWM control means includes an oscillating unit and a low-pass filter unit (hereinafter, referred to as an LPF unit), and the oscillating unit further includes a temperature detecting unit. The pulse width of the output signal of the oscillation unit is controlled, and when the temperature of the power transistor section exceeds a predetermined temperature Tc, a first temperature detection signal is output from the temperature detection output terminal. A signal corresponding to an input signal is output only when a signal having a pulse width longer than the time is input, an oscillation output terminal of the oscillation unit is connected to an input terminal of the LPF unit, and an output terminal of the LPF unit is connected to the PWM. The control means may be configured as the PWM output terminal.

The temperature detecting section may connect m (where m is an integer of 1 or more) diodes to the cathode of the k-th diode and the anode of the k + 1-th diode (where k is 1 ≦ k ≦ (An integer that satisfies (m-1)), all are connected in series, the first diode string having the anode of the first diode as the anode end and the cathode of the m-th diode as the cathode end, and when the temperature rises, And a positive temperature coefficient thermistor having an increased resistance value.

Further, the oscillation unit includes first, second, and third comparators, three p-channel field effect transistors (hereinafter, referred to as PMOS), six resistance elements,
One capacitance element, a flip-flop with a set / reset terminal, an inverter, and m (where m is an integer of 1 or more) diodes connected to the cathode of the k-th diode and the anode of the k + 1-th diode ( However, k is an integer satisfying 1 ≦ k ≦ (m−1)), all are connected in series, and the first diode having the anode of the first diode as the anode terminal and the cathode of the m-th diode as the cathode terminal A diode string, and a positive temperature coefficient thermistor whose resistance value increases as the temperature rises. A first resistor is connected between a high-potential-side power supply terminal of a predetermined voltage and the first node, and the first node and the first node are connected to each other. A second resistor and a first PM between two nodes
An OS source / drain path is connected, the first diode row is connected between the second node and a low potential side power supply terminal with the anode end facing the second node, and the high potential side power supply terminal is connected to the first diode row. A third resistor and a fourth resistor are connected in series between the third node in this order, and a second resistor is connected in parallel with the third resistor.
A source / drain path of a PMOS is connected, a fifth resistor is connected between the third node and the low potential side power supply terminal, and a non-inverting input terminal and an inverting input terminal of the first comparator are respectively connected to the first node. And the third node. The output terminal of the first comparator is connected to each gate of the first PMOS and the second PMOS and the input terminal of the inverter. The non-inverting input terminal and the inverting input terminal of the second comparator are connected. And an output terminal connected to a fifth node, the first node, and a reset input terminal of the flip-flop, respectively, and a non-inverting input terminal, an inverting input terminal, and an output terminal of the third comparator are connected to the A sixth resistor and the capacitor connected in parallel between the fifth node and the low-potential-side power supply terminal; Side power terminal A third PMOS source / drain path is connected between one end of the positive temperature coefficient thermistor, the other end of the positive temperature coefficient thermistor is connected to the fifth node, an output end of the inverter is connected to the temperature detection output end, The flip-flop may have an inverted output terminal connected to the gate of the third PMOS and the PWM output terminal.

The selection control means includes a two-input logical sum unit and a two-input logical product unit having one inverted input terminal, and connects one input terminal of the two-input logical sum unit to the short-circuit detection output. And the other input terminal is connected to the temperature detection output terminal, the inverting input terminal of the AND unit is connected to the PWM output terminal, and the other normal input terminal is connected to the output terminal of the inverter. And said 2
The output terminal of the input AND unit may be the selection control output terminal.

Further, the load short-circuit detecting means includes one n
A channel-type field-effect transistor, two resistance elements, an inverter, and q (where q is an integer of 1 or more) diodes are connected with the cathode of the j-th diode to the anode of the j + 1-th diode (where j is 1 ≦ j ≦
(An integer that satisfies (q-1)), all are connected in series, the anode of the first diode is used as the anode end,
The second with the cathode of the q-th diode as the cathode end
A diode string; connecting a thirteenth resistor and a fourteenth resistor between the first input terminal and the second input terminal and the thirteenth node, respectively; and connecting the thirteenth resistor between the first input terminal and the fourteenth node. Connect the source / drain path of the NMOS, and
Is connected to the thirteenth node, the anode end and the cathode end of the second diode string are respectively connected to a third input terminal and the fourteenth node, and the input terminal of the inverter is connected to the fourteenth node. And the output terminal of the inverter may be a short-circuit detection output terminal from which a short-circuit detection signal is output.

The power transistor may be an n-channel field effect transistor or an NPN transistor, and the overheat protection circuit is preferably formed on the same chip as the power transistor.

[0016]

Next, the present invention will be described with reference to the drawings. It should be noted that the following description of the embodiment is based on NMOS
Is described as PTr.

FIG. 1 is a schematic block diagram showing an embodiment of the overheat protection circuit of the present invention. Referring to FIG. 1, an overheat protection circuit 1 according to the present embodiment employs pulse width modulation (hereinafter referred to as P
WM) is configured to include at least a control unit 3, a selection control unit 5, and a load short-circuit detection unit 7.

First, the PWM control means 3 includes an oscillation unit 3
1 and a low-pass filter unit (hereinafter, referred to as an LPF unit) 35, and the oscillation unit 31 further includes a temperature detection unit 33 provided near the NMOS 10, which is a PTr. The LPF unit 35 is configured to output a signal corresponding to the input signal only when a signal having a pulse width longer than a predetermined time is input, according to the temperature of the oscillation unit 31. It is. The oscillation output terminal P01 and the temperature detection output terminal P02 of the oscillation unit 31 are connected to the LPF unit 3
5 and the LPF output terminal F01 of the LPF unit 35 which is connected to the second detection result input terminal SC2 of the selection control means and serves as the PWM output terminal of the PWM control means 3, and the selection input terminal S11 of the selection control means 5. Connect with In addition, this LP
The F output terminal F01 is the PWM output terminal of the PWM control means 3.

The load short-circuit detecting means 7 is configured to output a predetermined short-circuit detection signal from the short-circuit detection output terminal D01 when a load (not shown) driven by the PTr is short-circuited or in a state equivalent to a short-circuit. Then, the first input terminal D11 and the second input terminal D12 are connected to the source terminal (S) and the drain terminal (D) of the NMOS 10, respectively, and the third input terminal D13 is connected to the drive control output terminal SW01 of the switch means 9. , The short-circuit detection output terminal D01 to the first detection result input terminal SC1 of the selection control means 5.
Connect with Further, the selection control output terminal S01 of the selection control means 5, which is the output terminal of the overheat protection circuit 1, is connected to the drive control input terminal SWC of the switch means 9.

The switch means 9 includes a drive input terminal SW11, a drive control input terminal SWC, a drive control output terminal SW01, and a reference potential connection terminal SWG, and receives a drive input based on a first control signal input to the drive control input terminal SWC. The drive signal input to the terminal SW11 is output from the drive control output terminal SW01. The drive input terminal SW11 is connected to the drive input terminal (IN) of the PTr and the drive control input terminal SWC is connected to the selection control output of the selection control means 5. End S01,
The drive control output terminal SW01 is connected to the gate of the NMOS 10, and the reference potential connection terminal SWG is connected to the source terminal (S) of the NMOS 10.

Next, a specific configuration example of the main components will be described.

FIG. 2 is a circuit diagram showing a specific configuration example of the oscillation unit 31. Referring to FIG. 2, the oscillation unit 31 of the present embodiment includes first, second, and third comparators (hereinafter, referred to as CPs) 311, 313a, and 313b, and three p-channel field-effect transistors (hereinafter, referred to as CPs). , PM1,
PM2, PM3), six resistors R1, R2, R3, R4, R5, and R6, one capacitor C1, and a flip-flop with a set / reset terminal (hereinafter, referred to as a “flip-flop”). F / F) 315, an inverter (hereinafter referred to as INV) 317, a first diode row 331, and a positive temperature coefficient thermistor 333 whose resistance increases as the temperature rises. The first diode row 331 is, for example, m (where m is an integer of 1 or more).
The pn junction diodes are connected in series by connecting the cathode of the k-th diode to the anode of the k + 1-th diode (where k is an integer satisfying 1 ≦ k ≦ (m−1)). , And the cathode of the m-th diode is a cathode end 331c.

A high potential side power supply terminal (hereinafter referred to as V
dd) and a first resistor R1 between the first node N1 and a second resistor R1 between the first node N1 and the second node N2.
2 and the source / drain path of the first PMOS PM1 are connected in parallel, and the anode terminal 3 of the first diode row 331 is connected.
The first node 31a and the cathode terminal 331c are connected to the second node N2 and a low potential side power supply terminal (hereinafter, referred to as GND), respectively. A third resistor R3 is connected between Vdd and the third node N3.
And the fourth resistor R4 are connected in series in this order, the source and drain paths of the second PMOS PM2 are connected in parallel with the third resistor R3, and the fifth resistor R5 is connected between the third node N3 and GND. I do. The non-inverting input terminal and the inverting input terminal of CP311 are connected to nodes N1 and N3, respectively,
The output terminal of CP311 is connected to the gates of PM1 and PM2 and the input terminal of INV317, and the non-inverting input terminal, inverting input terminal, and output terminal of CP313a are connected to the fifth node N5, the first node N1, and the F / F 315, respectively. And the non-inverting input terminal, the inverting input terminal, and the output terminal of the CP 313b are connected to the second node N2, the fifth node N5, and the set input terminal (S) of the F / F 315, respectively. Then, a sixth resistor R6 and a capacitor C1 are connected in parallel between the fifth node N5 and GND. Further, the source / drain path of the third PMOS PM3 is connected between Vdd and one end of the positive characteristic thermistor 333, and the other end of the positive characteristic thermistor 333 is connected to the fifth node N5. Further, the output terminal of the INV 317 is connected to the temperature detection output terminal P02, and the inverted output terminal of the F / F 315 is connected to the gate of the PM3 and the oscillation output terminal P01. The first diode row 331 and the positive temperature coefficient thermistor 3
33 is provided near the NMOS 10. Also, CP3
A window comparator (WCP) 313 is constituted by 13a and CP 313b. A CR time constant is constituted by the capacitance C1, the resistor R6, and the positive temperature coefficient thermistor 333, and WC
The oscillation frequency is determined by the potential of the first node N1 and the potential of the second node N2 input to P313. For temperature detection, a first diode row 331 and a capacitor C1
The temperature characteristics of the positive temperature coefficient thermistor 333 that varies the charging time to the battery are used. The temperature-dependent hysteresis characteristic generation unit compares the potential of the third node N3 serving as the reference voltage with the potential of the first node N1 input to the WCP 313, the PM3 that changes the reference potential, and the PM2 and the first that change the reference potential.
It is composed of PM1 used for reducing the difference between the potential of the node N1 and the potential of the second node N2.

As described above, the oscillation unit 31 of this embodiment includes the WCP 313, the F / F 315, the PM 3, and the resistor R6.
In addition, by using a WCP type CR oscillation circuit configuration including a capacitor C1 and the like, when a load short circuit occurs, PWM control depending on the temperature of PTr is performed, and control for shortening the ON time of PTr as the temperature rises is performed. It becomes possible. As a result, it is possible to delay the temperature rise of the PTr when the load is short-circuited. Specifically, the temperature of the NMOS 10 is detected by the first diode row 331 and the positive temperature coefficient thermistor 333, and NM
A PWM signal whose high level time width becomes shorter as the temperature of the OS 10 rises is output from the oscillation output terminal P01. Further, as the temperature of the NMOS 10 rises, the potential of the first node N1 and the potential of the second node N2 fall, and when the temperature exceeds a predetermined temperature Tc (normally, a temperature at which the element may be broken), the first node N1 and the second node N2 may fall. The potential of one node N1 becomes lower than the first potential V1 of the third node N3, and the output signal of CP311 is inverted from a high level to a low level. As a result, since PM1 and PM2 are turned on, the potential of the first node N1 further decreases, and the potential of the third node N3 rises to the second potential V2 (> V1). Further, the temperature detection output signal INV317 Is inverted from a low level to a high level. Thereby, the temperature of the NMOS 10 has a hysteresis characteristic. Further, when PM1 is turned on, the difference between the potential of the first node N1 and the potential of the second node N2 becomes extremely small, and the high-level time width of the oscillation signal output from the oscillation output terminal P01 becomes smaller than the time constant of the LPF unit 35. , The output of the LPF unit 35 in this state remains at a low level. Therefore, when the short circuit is detected by the load short circuit detecting means 7,
The first diode row 331 and the positive temperature coefficient thermistor 333 provide N
The temperature of the MOS 10 is detected, and as the temperature of the NMOS 10 rises, the conduction time of the NMOS 10 is controlled to be shorter regardless of the signal input to the drive input terminal (IN), and when the temperature exceeds a preset temperature Tc. , So that the NMOS 10 is completely turned off.

Next, specific examples of other main components will be described.

FIGS. 3A and 3B are diagrams for explaining specific examples of other main components, and FIGS. 3A, 3B, 3C and 3D.
3 is a circuit diagram of the selection control means 5, the LPF unit 35, the load short-circuit detection means 7, and the switch means 9, respectively.

First, referring to FIG. 3A, the selection control means 5 of the present embodiment includes, for example, a two-input OR gate (hereinafter referred to as a 2-OR) 51 and one of the two gates being an inverting input terminal. Two-input AND gate (hereinafter referred to as 2-AND)
53. In this case, the two input terminals of the 2-OR 51 and the inverting input terminal of the 2-AND 53 are a first detection result input terminal SC1, a second detection result input terminal SC2, and a selection input terminal S11, respectively. 2-A at the end
What is necessary is just to connect to the normal input terminal of ND53, and to make the output terminal of 2-AND53 the selection control output terminal S01 of the selection control means 5.

Next, referring to FIG. 3B, the LPF unit 35 of the present embodiment includes an eleventh resistor R11 and a capacitor C3.
And a buffer (hereinafter, referred to as BUF) 351. That is, the input terminal F11 of the LPF unit 35
The eleventh resistor R11 is connected between the first node N11 and the eleventh node N11, the capacitor C3 is connected between the eleventh node N11 and the GND, and the input terminal of the BUF 351 is connected to the eleventh node N11.
The output terminal of the BUF 351 may be the LPF output terminal F01 of the LPF unit 35. With this configuration, the eleventh resistor R
A signal waveform that has passed through a low-pass filter using the CR time constant of 11 and the capacitor C3 is shaped by a BUF 351 and output. Therefore, when the high-level time width of the signal input to the LPF input terminal F11 is shorter than the time constant determined by the eleventh resistor R11 and the capacitor C3, the high-level signal is not output from the LPF output terminal F01 and the low-level signal is not output. The signal remains.

Next, referring to FIG. 3C, the load short-circuit detecting means 7 of the present embodiment includes, for example, a thirteenth resistor R13, a fourteenth resistor R14, a first NMOS 71, a second diode row 73, and an INV75. And can be configured. First, a thirteenth resistor R13 is connected between the first input terminal D11 and a thirteenth node N13.
A fourteenth resistor R is provided between the second input terminal D12 and the thirteenth node N13.
Connect 14 to each. Further, the first input terminal D11 and the fourteenth
The source-drain path of the first NMOS 71 is connected between the nodes N14, the gate of the first NMOS 71 is connected to the thirteenth node N13, and the second diode row 73 is connected between the third input terminal D13 and the fourteenth node N14. , INV75 may be connected to the fourteenth node N14, and the output terminal of INV75 may be used as the short-circuit detection output terminal D01. The second diode row 7
Reference numeral 3 denotes a q number (where q is an integer of 1 or more) of diodes connected to a cathode of a j-th diode and an anode of a j + 1-th diode (where j is an integer satisfying 1 ≦ j ≦ (q−1)) In this way, the anode of the first diode is formed as the anode end 73a, the cathode of the q-th diode is formed as the cathode end 73c, and the anode end 73a and the cathode end 73c are respectively connected to the third input terminal D13. And the fourteenth node N14. Also,
The first, second and third input terminals D11, D12 and D13 are connected to the source terminal (S) and drain terminal (D) of the NMOS 10 and the drive control output terminal SW01 of the switch means 9, respectively. That is, the load short-circuit detecting means 7
The voltages applied between the source and drain of S10 are R13 and R
The voltage is divided at 14 and the divided voltage of the thirteenth node N13 is set to N
The MOS 71 is driven. Therefore, when the load connected to the NMOS 10 is short-circuited, the voltage applied between the source and the drain of the NMOS 10 becomes large, so that the thirteenth node N
The voltage of 13 also increases, and the NMOS 71 turns on. This operation lowers the potential of the fourteenth node N14 and the third input terminal D13, so that the output signal of the INV 75 is inverted to a high level, and the gate voltage of the NMOS 10 is also reduced.
The overcurrent flowing to S10 is suppressed.

Next, referring to FIG. 3D, the switch means 9 of the present embodiment comprises, for example, a sixteenth resistor R16 and a second N
MOS 91 can be included. Specifically, the sixteenth resistor R16 is connected between the drive input terminal SW11 and the sixteenth node N16.
The source / drain path of the NMOS 91 is connected to the 16th node N16
The gate of the second NMOS 91 is connected to the drive control input terminal SWC, and the sixteenth node N16 is connected to the drive control output terminal SW01 between the reference potential connection terminal SWG. With this configuration, when a high-level signal is input to the drive control input terminal SWC, the second NMOS 91 turns on, and the PTr drive input terminal (I
N) Regardless of the input signal, the potential of the sixteenth node N16 becomes substantially the same as the potential of the reference potential connection terminal SWG, and the potential of the reference potential connection terminal SWG is output from the drive control output terminal SW01. When a low-level signal is input to the terminal SWC, the second NMOS 91 is turned off, and the PTr drive input terminal (I
N) is directly output from the drive control output terminal SW01 via the sixteenth node N16.

Next, the operation of the overheat protection circuit of this embodiment will be described.

FIG. 4 is a waveform diagram schematically illustrating the temperature change of the NMOS 1 and the voltage change at the main node for explaining the operation of the overheat protection circuit 1 of the present embodiment.

First, the case where the NMOS 10 is conductive and the load short-circuit detecting means 7 has not detected a load short will be described. Referring to FIGS. 1 to 3, in this case, since the low-level signal is output from the short-circuit detection output terminal D01, the selection control output terminal of the selection control means 5 unless the temperature of the NMOS 10 exceeds the predetermined temperature Tc. Since S01 always outputs a low-level signal regardless of the signal input to the selection input terminal S11, the switch means 9 switches the signal input from the drive input terminal (IN) of the PTr connected to the drive input terminal SW1 to the first signal. Drive control output terminal SW as it is via 16 nodes N16
01, the NMOS 10 operates normally.

If the temperature of the NMOS 10 exceeds a predetermined temperature Tc for some reason despite no load short-circuit, a high-level signal is output from the temperature detection output terminal P02. From the output terminal S01, an inverted signal of the signal input to the selection input terminal S11 is output. However, at this time, the high-level time width of the oscillation output of the oscillation unit 31 is shorter than the time constant determined by the resistor R11 and the capacitor C3 constituting the LPF unit 35.
A low level signal is always output from the LPF output terminal F01 as a PWM signal which is an output of the control means 3, and the NMOS 10
Is turned off to prevent destruction.

Next, the case where the NMOS 10 is in the conductive state and the load short-circuit detecting means 7 detects the load short-circuit will be described. Referring to FIGS. 1 to 4, in this case, since a high-level signal is output from the short-circuit detection output terminal D01, the selection control output terminal S01 of the selection control means 5 is switched to the selection input terminal S11.
And outputs an inverted signal of the signal input to. N which is PTr
When the temperature of the MOS 10 is low, the resistance value of the positive temperature coefficient thermistor 333 included in the oscillation unit 31 shown in FIG.
As a PWM signal output from the WM control means 3, a PWM signal having a long high-level time width is output from the LPF output terminal F01. This operation has a waveform as shown in FIG. 4 as in the normal operation period.

Subsequently, when the temperature of the NMOS 10 rises, the forward voltage (hereinafter referred to as V) of the first diode row 331 is increased.
F voltage), the first node N1 and the second node
Each potential of the node N2 decreases. In addition, since the resistance value of the positive temperature coefficient thermistor 333 increases, the charging time to the capacitor C1 increases, and the PWM signal whose high-level time width decreases as the temperature rises is output from the LPF output terminal F01 of the LPF unit 35. That is, the NMOS 10 is PWM
It will be in a controlled state. This operation is shown in FIG.
It has a waveform like the WM control period.

When the temperature of the NMOS 10 further rises and reaches a predetermined temperature Tc, the potential of the first node N1 which is an input signal of the CP 311 becomes the third threshold when overheating occurs.
Since the output signal of the CP 311 is inverted from the high level to the low level below the first potential V1 of the node N3, PM1,
PM2 is turned on. With this operation, the potential of the third node N3 rises to the second potential V2, and as a result, a hysteresis characteristic with respect to the device temperature is provided. That is, once PM2 is turned on, the potential of the third node N3 rises to the second potential V2 (> V1).
Until the temperature of S10 decreases to a predetermined temperature Tr (<Tc), the output signal of CP 311 remains at a low level.

When the PM1 is turned on, the potential difference between the first node N1 and the second node N2 becomes small, and the oscillation unit 31 outputs a signal pulse having a very short high-level time width from the oscillation output terminal P01. I do. The resistance value of the eleventh resistor R11 and the capacitance of the capacitor 3 so that the time constant determined by the eleventh resistor R11 and the capacitance C3 of the LPF unit 35 is longer than the high-level time width of the signal pulse output from the oscillation unit 31 at this time. If a value is determined, the PWM control means 3 outputs a low-level signal at least while PM1 is on. Therefore, until the temperature of the NMOS 10 decreases to a predetermined temperature Tr (<Tc), the NMOS 10 is turned off. This operation has a waveform as shown in the PTr off period in FIG.

Next, the temperature of the NMOS 10 is set to a predetermined temperature T
r, the potential of the first node N1, which is the input signal of CP311, exceeds the second potential V2 of the third node N3, so that the output signal of CP311 becomes high level and PM
1 and PM2 are both turned off. At this time, in a state where the load short circuit is still detected, the operation such as the above-described PWM control period is repeated. In addition, after the load connected to the NMOS 10 is short-circuited in the above-described series of operations, for example, as schematically shown in FIG. When the short-circuit state is released and the normal state is reached, PTr
Is returned to the normal operation state from the point in time when the temperature has decreased to the predetermined temperature Tr. Further, the PTr temperature becomes a predetermined temperature Tc.
If the short-circuit state is released during the PWM control period in which PTr does not rise, the PTr returns to the normal operation from that point.

The overheat protection circuit of the PTr of the present invention comprises a WCP
By using the CR oscillation circuit configuration of the system, when a load short circuit occurs, PWM control depending on the PTr temperature is performed, and control to shorten the ON time of the PTr as the temperature rises becomes possible. As a result, it is possible to delay the temperature rise of the PTr when the load is short-circuited. When the PTr reaches the temperature Tc at which destruction occurs, the hysteresis generators PM1 and PM2 and the LPF unit 35 are combined with the above configuration, so that fine circuit adjustment such as setting of complicated element constants is not required, and simpler. With the circuit configuration, the PTr can be reliably turned off until the temperature falls to a predetermined temperature Tr, and destruction can be prevented.

The present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made within the scope of the invention. For example, as shown in FIG.
May be an NPN transistor 12. Also, instead of the second diode row 73 of the load short-circuit detecting means 7, FIG.
As shown in FIG.

[0042]

As described above, the overheat protection circuit of the present invention can suppress the temperature rise of the PTr without completely turning off the PTr immediately even if the load driven by the PTr is short-circuited. This has the effect. Also, P
When the temperature of the Tr exceeds a predetermined temperature Tc set in advance, the PTr is completely turned off, and after the temperature of the PTr decreases to a predetermined temperature Tr (<Tc), the PTr is operated again. There is also an effect that the destruction of the can be prevented.

Further, the overheat protection circuit of the present invention does not require fine circuit adjustment such as setting of complicated element constants, and has an effect that a stable overheat protection operation can be performed with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of an overheat protection circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of the oscillation unit of FIG.

FIG. 3 is a diagram showing an example of details of main components of FIG. 1;
(A), (b), (c), and (d) are circuit diagrams of a selection control unit, an LPF unit, a load short-circuit detection unit, and a switch unit, respectively.

FIG. 4 is a diagram for explaining the operation of the overheat protection circuit of FIG. 1;
It is an output waveform diagram in a main node.

FIG. 5 is a circuit diagram showing an example in which the overheat protection circuit of the present invention is applied to an NPN transistor.

FIG. 6 is a circuit diagram showing another example of the load short-circuit detecting means.

FIG. 7 is a circuit diagram showing an example of a conventional overheat protection circuit.

FIG. 8 is a diagram schematically showing a change in the operating state of the PTr according to the PTr temperature.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Overheat protection circuit 3 PWM control means 5 Selection control means 7 Load short circuit detection means 9 Switch means 10, 71, 91 NMOS 12 NPN transistor 31 Oscillation unit 33 Temperature detection unit 35 LPF unit 51 2-OR 53 2-AND 73 Second Diode array 75,317 INV 311, 313a, 313b CP 313 WCP 315 F / F 331 First diode array 333 Thermistor 351 BUF C1, C3 Capacitance D01 Short circuit detection output terminal D11 First input terminal D12 Second input terminal D13 Third input Terminal F01 LPF output terminal F11 LPF input terminal N1, N2, N3, N5, N11, N13, N14, N16
Node P01 Oscillation output terminal P02 Temperature detection output terminal R0, R1, R2, R3, R4, R5, R6 Resistance R11, R13, R14, R16, R20 Resistance S01 Selection control output terminal S11 Selection input terminal SC1 First detection result input terminal SC2 Second detection result input terminal SWC Drive control input terminal SW11 Drive input terminal SW01 Drive control output terminal SWG Reference potential connection terminal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J032 AA02 AA05 AA06 AB02 AC12 AC18 5J055 AX34 AX37 AX64 BX44 CX28 EX16 EY01 EY04 EY10 EY12 EY21 EZ10 EZ14 EZ23 EZ25 EZ28 EZ31 FX06 FX31 FX33 GX01X05

Claims (8)

[Claims] 1. A drive signal connected to a control electrode of a power transistor, wherein the drive control output terminal of a predetermined switch having at least a drive input terminal, a control input terminal, and a drive control output terminal is connected to the drive input terminal. Overheat protection circuit of the power transistor for driving a predetermined load by outputting from the drive control output terminal based on a control signal input to the control input terminal, wherein at least load short-circuit detection means and pulse width modulation ( Hereinafter referred to as PWM) control means and selection control means, wherein the load short-circuit detection means detects that the predetermined load driven by the power transistor has short-circuited and detects a short-circuit detection signal. Output from an output terminal, wherein the PWM control means outputs the power
PWM of a pulse width signal corresponding to the temperature of the transistor section
Output from an output terminal, and when the temperature of the power transistor section exceeds a predetermined temperature Tc, a first temperature detection signal is output from a temperature detection output terminal. Detection result input end, 2nd
A detection result input terminal and a selection control output terminal;
A signal input to the selection input terminal is controlled to be output from the selection control output terminal in accordance with a signal input to the detection result input terminal and the second detection result input terminal, and the PWM output terminal is connected to the selection input terminal. Terminal, the short-circuit detection output terminal is connected to the first detection result input terminal, the temperature detection output terminal is connected to the second detection result input terminal, and a third selection control output terminal of the selection control means is connected. Is connected to a control input terminal of the switch means. 2. The PWM control means includes an oscillation unit and a low-pass filter unit (hereinafter, referred to as an LPF unit). The oscillation unit further includes a temperature detection unit. The pulse width of the output signal of the oscillation unit is controlled, and when the temperature of the power transistor section exceeds a predetermined temperature Tc, a first temperature detection signal is output from the temperature detection output terminal. A signal corresponding to the input signal is output only when a signal having a longer pulse width is input, an oscillation output terminal of the oscillation unit is connected to an input terminal of the LPF unit, and an output terminal of the LPF unit is connected to the PW
2. The overheat protection circuit according to claim 1, wherein said PWM output terminal of said M control means has a configuration. 3. The temperature detecting section connects m (where m is an integer of 1 or more) diodes to a cathode of a k-th diode and an anode of a k + 1-th diode (where k is 1 ≦ k ≦). (An integer that satisfies (m-1)), all are connected in series, the first diode string having the anode of the first diode as the anode end and the cathode of the m-th diode as the cathode end, and when the temperature rises, 3. The overheat protection circuit according to claim 2, further comprising: a positive temperature coefficient thermistor having an increased resistance value. 4. The oscillation unit includes a first, a second, and a third comparator, three p-channel field-effect transistors (hereinafter, referred to as PMOS), six resistance elements, and one A capacitor, a flip-flop with a set / reset terminal, an inverter, and m (where m is an integer of 1 or more)
K + diodes to k +
Connected to the anode of the first diode (where k is 1 ≦
k ≦ integer satisfying (m−1)), a first diode string having the anode of the first diode as an anode end, the cathode of the m-th diode as a cathode end, and a temperature of A positive temperature coefficient thermistor having a resistance value which increases as the resistance rises, a first resistance being connected between a high potential side power supply terminal of a predetermined voltage and the first node, and a first resistance being connected between the first node and the second node. 2 resistor and 1st PMOS
The first diode row is connected between the second node and the low-potential-side power supply terminal with the anode end facing the second node, and the high-potential-side power supply terminal is connected to the second node and the low-potential-side power supply terminal. A third resistor and a fourth resistor are connected in series in this order between the three nodes, and a second PM is connected in parallel with the third resistor.
A source / drain path of an OS, a fifth resistor between the third node and the low potential side power supply terminal,
A non-inverting input terminal and an inverting input terminal of a comparator are connected to the first node and the third node, respectively, and an output terminal of the first comparator is connected to gates of the first PMOS and the second PMOS and an input terminal of the inverter. , And the non-inverting input terminal, the inverting input terminal, and the output terminal of the second comparator are connected to a fifth node, the first node, and the reset input terminal of the flip-flop, respectively. Forward input end of
An inverting input terminal and an output terminal are respectively connected to the second node, the fifth node, and a set input terminal of the flip-flop, and a sixth resistor and the low-potential-side power supply terminal are connected between the fifth node and the low-potential-side power supply terminal. A capacitor is connected in parallel, and a third capacitor is connected between the high potential side power supply terminal and one end of the positive temperature coefficient thermistor.
A PMOS source / drain path is connected, the other end of the positive temperature coefficient thermistor is connected to the fifth node, an output end of the inverter is connected to the temperature detection output end, and an inverted output end of the flip-flop is connected to the fifth output terminal. 4. The overheat protection circuit according to claim 2, wherein the overheat protection circuit has a configuration connected to a gate of a 3PMOS and the PWM output terminal. 5. The selection control means includes a two-input logical sum unit and a two-input logical product unit having one inverted input terminal, and connects one input terminal of the two-input logical sum unit to the short-circuit detection output. And the other input terminal is connected to the temperature detection output terminal, the inverting input terminal of the AND unit is connected to the PWM output terminal, and the other normal input terminal is connected to the output terminal of the inverter. 5. The overheat protection circuit according to claim 1, wherein an output terminal of the two-input AND unit is used as the selection control output terminal. 6. The load short-circuit detecting means includes one n-channel type field effect transistor (hereinafter, referred to as NMOS).
, Two resistance elements, an inverter, and q (where q is an integer of 1 or more) diodes connected to the cathode of the j-th diode and the anode of the j + 1-th diode (where j is 1 ≦ j) ≦ (integer satisfying (q-1)), a second diode string having an anode of a first diode as an anode end and a cathode of a q-th diode as a cathode end, A thirteenth resistor and a fourteenth resistor are connected between the first input terminal and the second input terminal and the thirteenth node, respectively, and a source / drain path of the NMOS is connected between the first input terminal and the fourteenth node. Connecting the gate of the NMOS to the thirteenth node; connecting the anode end and the cathode end of the second diode row to a third input end and the fourteenth node, respectively; 6. The overheat protection according to claim 1, wherein an input terminal of the inverter is connected to the fourteenth node, and an output terminal of the inverter is a short-circuit detection output terminal from which a short-circuit detection signal is output. circuit. 7. The overheat protection circuit according to claim 1, wherein the power transistor is an n-channel type field effect transistor. 8. A power transistor comprising the overheat protection circuit according to claim 1 on a same chip.