JP2693545B2 - Pulse delay circuit - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to an improvement of a pulse delay circuit used in, for example, a television video signal processing device.

(Prior Art) Conventionally, in a television image signal processing device or the like, in order to delay a pulse signal having a pulse width of several hundreds of nanoseconds (nS) to several hundreds of nanoseconds by a time shorter than the pulse width, FIG. The pulse delay circuit shown in is used.

That is, in the conventional pulse delay circuit, a time constant circuit including a resistor 2 and a capacitor 3 is connected to the pulse input terminal 1, and a buffer amplifier or the like is provided between the connection point between the resistor 2 and the capacitor 3 and the output terminal 4. A buffer circuit 5 is connected and configured.

Therefore, as shown in FIG. 4 (a), a pulse signal having a voltage level of "0"-"1" and a pulse width of T is "0" and the high voltage level is "1". It is supplied to the input terminal 1 as a pulse signal shown in FIG. 4 (b) via the buffer circuit 6, and the pulse signal of the input terminal 1 is supplied to the time constant circuit composed of the resistor 2 and the capacitor 3.

The time constant circuit starts from the leading edge of the input pulse to the capacitor 3
As shown in FIG. 4 (c), the voltage gradually rises as shown in FIG. 4 (c). However, when the voltage exceeds the threshold voltage level (h1) of the buffer circuit 4, as shown in FIG. 4 (d). The output from the buffer circuit 5 becomes the level "1" for the first time. Therefore, it is derived from the output terminal 4 as a signal in which the leading edge of the input pulse is delayed by the time t1 from when the capacitor 3 is charged to when it reaches the threshold voltage level (h1).

Next, at the trailing edge of the input pulse signal (Fig. 4 (b)),
Since the voltage level changes from "1" to "0", the capacitor 3 of the time constant circuit starts discharging and decreases to the threshold voltage level (h1) of the buffer circuit 5 after time t2. Then, as shown in FIG. 4 (d), the voltage level becomes "0", which is derived from the output terminal 4 as a pulse signal whose trailing edge is delayed by the time t2.

Generally, when the delay time t1 of the leading edge of the pulse is short, the capacitor 3 is sufficiently charged by the elapsed time until reaching the trailing edge of the pulse, so that the threshold voltage level (h1) is reached from the trailing edge of the input pulse. , The trailing edge delay time t2 is substantially equal to the leading edge delay time t1, and the pulse width T at the time of input / output remains unchanged.

However, when the delay time t1 of the leading edge of the pulse signal becomes longer and becomes closer to the pulse width T, the output pulse width T ′ becomes narrower, and it becomes impossible to obtain a delayed pulse signal with the pulse width of the input pulse signal kept as it is. Problems arise.

That is, when the delay time t1 of the input pulse signal becomes long, as shown in FIG. 5 (c), after the voltage of the capacitor 3 exceeds the threshold voltage level (h1) of the buffer circuit 5,
The time until the input voltage becomes 0 (T-t1) becomes short, and the discharge is started by the trailing edge of the pulse while the capacitor 3 is not charged to the voltage value reaching the voltage level "1". Therefore, the time t2 from when the pulse input signal becomes the voltage level "0" at the trailing edge until the input voltage of the buffer circuit 5 becomes the threshold level (h1) or less is shorter than the delay time t1 at the leading edge of the pulse. Become. Therefore, the output pulse width T'of the buffer circuit 4 becomes shorter than the input pulse width T, and there is a drawback that an output in which the pulse width T is maintained as it is cannot be obtained.

(Problems to be Solved by the Invention) As described above, in the conventional pulse delay circuit, when the pulse delay time becomes long, the pulse width of the output pulse is shortened, and the input pulse width is delayed as it is. There was a problem that it could not be done.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the above-mentioned conventional drawbacks and to provide a pulse delay circuit capable of ensuring an input pulse width and outputting even if the pulse delay time becomes long.

[Configuration of the Invention] (Means for Solving the Problems) A pulse delay circuit according to the present invention includes a resistor connected to a pulse input terminal, and a buffer circuit connected in series with the resistor to derive a pulse delay output. A capacitor connected in parallel to the buffer circuit and a DC voltage source connected via a diode to a connection point between the resistor and the buffer circuit.

(Operation) In the pulse delay circuit according to the present invention, by connecting the capacitor in parallel to the buffer circuit, feedback is applied from the output side to the capacitor forming the time constant circuit, and the input side of the buffer circuit is connected to the diode and the direct current. Since the series circuit is connected to the voltage source, the capacitor is charged and discharged so that the voltage quickly becomes "1" when the voltage exceeds the threshold value. The input / output pulse width is always constant even if it approaches the pulse width.

(Embodiment) An embodiment of a pulse delay circuit according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the circuit of the present invention. The same components as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

That is, in FIG. 1, the pulse delay circuit includes a pulse input terminal 1, a time constant circuit consisting of a resistor 2 and a capacitor 7 connected in series to the pulse output terminal 4, and a buffer amplifier in parallel with the capacitor 7. The buffer circuit 5 is connected.

A diode 8 which is a rectifying element and a DC voltage source 9 for supplying a reverse bias to the diode 8 are connected in series between the input terminal of the buffer circuit 5, that is, the connection point 7a between the resistor 2 and the capacitor 7 and the ground. To be done.

The diode 8 and the DC voltage source 9 are biased so that they are conducted only when the voltage applied to the diode 8 exceeds the level "1".

Therefore, FIG. 2 shows a voltage signal corresponding to the prior art, in particular, FIG. 5, and as shown in FIG. 2 (a), the pulse width T of the voltage level "0"-"1" The pulse signal is supplied to the input terminal 1 as an input signal through the buffer circuit 5 at the preceding stage as shown in FIG. 2 (b). Input terminal 1
The pulse signal of is charged in the capacitor 7 by the time constant circuit composed of the resistor 2 and the capacitor 7, and FIG.
The voltage waveform shown in is obtained.

Therefore, when a relatively long delay time t1 elapses and the voltage level exceeds the threshold voltage level (h1) of the buffer circuit 5 as shown in FIG. 2 (c), the output of the buffer circuit 5 is output as in the conventional case. (That is, the pulse delay circuit output) has an output level "1" as shown in FIG.

At this time, since the other end of the capacitor 7 is connected to the output side (output terminal 4) of the buffer circuit 5, the output level "1" of the buffer circuit 5 raises the charging voltage of the capacitor 7 and the voltage level of the input side. Suddenly voltage level "1"
To reach h2. However, at this moment, the voltage exceeds the reverse bias voltage level of the diode 8 and is immediately discharged by the diode 8, so that the input voltage level of the buffer circuit 5 stabilizes at "1".

Therefore, even if the trailing edge of the input pulse signal (FIG. 2 (b)) reaches after this and changes to the "0" level, the capacitor 7 starts discharging from the state of the voltage level "1", After that, the time t2 until reaching the threshold voltage level (h1) is equal to the delay time t1 of the pulse leading edge. That is, a delayed pulse output having the same input / output pulse width T can be derived.

As described above, according to the embodiment of the present invention, voltage feedback is applied to the capacitor forming the time constant circuit at the leading edge of the input pulse, and the charge voltage level rises sharply, so that the voltage level "1" is secured and maintained. To be done. Therefore, even if the time until the trailing edge of the input pulse is reached thereafter is short, discharge from the voltage level "1" is always guaranteed, and the same input / output pulse width (t1 = t2) is secured.

Although the above embodiment has been described with respect to the input pulse signal in the case where the voltage level in the steady state is “0” and the level in the pulse width section is “1”, conversely, the voltage level in the steady state is “1”. , And the level of the pulse width section is “0”, the diode 8 and the DC voltage source 9 in FIG.
The same function and the same effect can be obtained by connecting the respective polarities in reverse. Similarly, when the input pulse signal has a positive pulse and a negative pulse mixed around the voltage level "0", the polarities of the series circuits of the diode and the DC voltage power supply are made different from each other. A parallel connection configuration may be used.

It should be noted that the diode 8 may have any conducting function so as to maintain a constant voltage with respect to an applied voltage equal to or higher than a constant voltage. Therefore, the diode here is not limited to a semiconductor element, but a diode or other similar function. It also includes circuit elements having. Further, as the buffer circuit 5, not only a logic circuit such as TTL (transistor-transistor logic) or CMOS (complementary-metal-oxide-semiconductor) but also a comparator or an operational amplifier circuit can be used.

[Advantages of the Invention] In summary, the pulse delay circuit according to the present invention has a pulse delay time of a length close to the pulse width
The delayed pulse is derived while maintaining the input pulse width, and it can be widely used not only in a television signal processing circuit but also in a general pulse circuit, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a pulse delay circuit according to the present invention, FIG. 2 is an operation voltage waveform diagram of the circuit shown in FIG. 1, and FIG. 3 is a circuit configuration diagram showing a conventional pulse delay circuit. 4 and 5 are operating voltage waveform diagrams of the circuit shown in FIG. 3, respectively. 1 ... Input terminal 2 ... Resistor 4 ... Output terminal 5 ... Buffer circuit 7 ... Capacitor 8 ... Diode 9 ... DC voltage source

Claims (1)

(57) [Claims] 1. A resistor connected to a pulse input terminal, a buffer circuit connected in series to the resistor to derive a pulse delay output, a capacitor connected in parallel to the buffer circuit, and the resistor. A pulse delay circuit, comprising: a DC voltage source connected to a buffer circuit via a diode.