JPS596528B2 - Shuyutsuriyokubatshuakairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output buffer circuit, and in particular to a circuit with a high logic level such as a field effect element (FET) circuit to a TTL circuit (Transistor Transistor circuit).
It relates to output buffer circuits for low logic level circuits such as Logic or Logic.

FIG. 1 is a circuit diagram showing an example of an output buffer circuit which is the background of the present invention.

The output buffer circuit of a digital MO8IC is generally
A push-pull type inverter circuit as shown in FIG. 1 is used.

The operation of such an inverting buffer circuit is already well known, and its explanation will be omitted.

Here, the power supplies VDDt and VDD2 are, for example, 5V and 12V, respectively, since this buffer circuit is an MO8 circuit.

Moreover, the output VOUTI is at a low level (LowLe
vel: “LJ” or high level (High
Level: Depending on [HJ), it will be 0■ or 5■.

On the other hand, the input rHJ voltage of the external TTL circuit receiving the output of this MO8 circuit is approximately 2.5 mm.

Therefore, "H" from this MO8IC (buffer circuit)
An output of approximately 3.0 square meters will be sufficient (as mentioned above, 5 square meters is not necessary).

Furthermore, when the input VIN of this output buffer circuit changes from rLJ to "H", the output VOUTt changes accordingly to rHJ.
However, considering this transient characteristic (delay time), if the discharge time constant is the same, it becomes rL from 5■
If you compare going from J to going from 3■ to rLJ, the latter naturally takes less time.

This is true also in the case of charging, and is particularly noticeable in the case of an output buffer circuit with a large load capacity.

Therefore, it is conceivable to clamp the output voltage of the MO8IC (when it is "H"), which has a relatively high logic level, to about 3■ and apply it to the TTL circuit, which has a relatively low logic level.

This clamping method typically involves MO
It is conceivable to attach a clamp diode outside the 8IC.

However, this method has the disadvantage that the mounted components increase the power, which increases the number of assembly steps.

It is also conceivable to incorporate such a diode inside the IC and use this diode to clamp its output level directly to a fixed power supply.

However, this method causes a new problem in that a large amount of current flows through the diode, which increases power consumption inside the IC.

Therefore, a principal object of the present invention is to provide an output buffer circuit with improved delay time that overcomes the particular drawbacks and problems mentioned above.

In summary, the present invention is an output buffer circuit for providing a digital signal with a relatively high output logic level (when "H") to a logic circuit with a relatively low input logic level, both of which are output from FETs. Two stages of push-pull circuits are connected in cascade, and an FET circuit is added to clamp the input level of the previous push-pull circuit by the output level of the latter stage of the push-pull circuit, thereby increasing the output level of the latter push-pull circuit. This is an output buffer circuit that clamps the level to a predetermined value.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

In the configuration, the FETs Q1 to Q8 of this circuit are all N-channel enhancement type FETs, for example, the voltage vT is set to IV, and the power supply voltage DD1. ■
DD2 is set to 5V and 12V, respectively.

FETs Ql, Q2 form a front-stage push-pull circuit, FETs Q&, Q7 form a rear-stage push-pull circuit, and these FETs Ql, Q2 . Q6. Q
7 constitutes the inverting buffer shown in FIG.

The gate electrode of the FETQI is used as an input terminal VIN.

Furthermore, a clamp circuit is formed by FETs Q3, Q4, and Q5.

That is, the drain electrode of FETQ3 is connected to the source electrode of FETQ4 together with its gate electrode, and the source electrode is grounded, for example.

Further, the drain electrode of FETQ4 is connected to the power supply VDDt together with its gate electrode.

The connection point B between FETQ3 and Q4 has a drain electrode connected to the gate electrode of FETQ7 (FETQl, Q2
is connected to the source electrode of FETQ5, which is connected to the connection point A).

The gate electrode of this FETQ5 is connected to the connection point of FETQ6 and Q7.

Furthermore, the connection point C of the FETs Q6 and Q7, that is, the output terminal VOUT2, is commonly connected to the drain electrode and gate electrode of the FET Q8, and the source electrode of the FET Q8 is grounded, for example.

The operation of the above configuration will be explained below with reference to FIG.

FIG. 3 is an example of a level chart showing the operation of the present invention.

In operation, first, the signal from input 1
Consider the case of J.

At this time, FETs Ql and Q6 become conductive, and both connection points A and C (output end voUT2) are forced to the ground potential of approximately O■.

Therefore, the output terminal VOUT2 becomes "L".

Next, consider the case where the input terminal VIN is "L".

At this time, both FETQI and Q'6 are cut off, and the potential at the connection point A is changed to the power supply VDD2 via FETQ2.
increases because it is given.

Therefore, FET Ql becomes conductive, and the potential at connection point C and therefore at output terminal VOUT2 rises, as shown by line a in FIG. 3.

As described above, when the potential at the connection point C increases and reaches a value equal to or greater than , FETQ5 starts to conduct, and FETQ3 becomes conductive.

Therefore, the potential at the connection point A decreases to a value corresponding to the conduction of FETs Q3 and Q5.

Correspondingly, the gate voltage of FET Ql decreases, its conduction state becomes slightly in the cut-off direction, and the potential at the output terminal voUT2 cannot rise above the potential shown by line a in FIG. 3.

Here, the gain factor (Gai
By appropriately selecting the ratio of nFactor)β and setting the potential of connection point B to a predetermined value, the output terminal VOU
The potential of T2 is clamped to approximately 3.times. as shown in FIG.

That is, by appropriately selecting the gain factor β of each FET Q3, Q4, Q5, Q7, etc. (this selection will be easy for those skilled in the art), the output voltage voltage can be adjusted to about 3.
■ Clamp on.

If the output voltage is clamped to about 3 cm as shown by line a in FIG. 3, the delay time during charging and the delay time during discharging due to the load capacitance, for example, can be significantly shortened.

For example, when the output voltage of rHJ is 3■ as shown by line a in Figure 3, the output voltage of "H" is 5■ as shown in line a of Figure 3, compared to the conventional circuit where the output voltage of "H" is 5■ as shown in line a of Figure 3. ” (approximately OV), the delay time when the output voltage drops is significantly shortened.

That is, the delay time to rLJ when the output voltage of "H" is 5V is t2, and the delay time to "L" when the output voltage is 3V is tl, and tl<t2.

Further, FETQ8 connected to the output terminal VOUT2 is not directly involved in the above-mentioned clamping operation, but the FETQ8 is connected to the output terminal voU.
By passing a small amount of current between T2 and ground, F
I am afraid that ETQ7 will completely cut off.

As a result, FETQ5. This prevents unstable operation caused by a delay in the on-off operation of Q7.

Note that the bias power source for the connection point B described above can also be supplied individually.

Further, in the above embodiment, an inverting buffer configured with an N-channel enhancement type FET was described, but this may be a non-inverting type FET, a P-channel FET, or another type of FET. Of course, it is possible.

As described above, according to the present invention, for example, there is no need for a diode or the like to apply force outside the IC, and the number of parts can be reduced.

Furthermore, even within the IC, compared to clamping the buffer output directly to a fixed power supply with a diode (which consumes a lot of power), the power consumption of the IC circuit increases only slightly, and clamping can be performed accurately. It is possible.

With such a simple configuration, a relatively high logic level FET circuit can be connected to a relatively low logic level, e.g.
In the output buffer circuit to the TL circuit, the operation delay time due to load capacitance can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 shows an example of an output buffer circuit which is the background of the present invention. FIG. 2 is a circuit diagram of one embodiment of the present invention. FIG. 3 is a level chart showing an example of the operation of the present invention. In the figure, Ql to Q8 are FETs, A, and B. C is a connection point, VIN is an input end, and VOUT2 is an output end.

Claims (1)

[Claims] 1. An output buffer circuit for outputting a signal from a relatively high logic level logic circuit input to an input terminal to a relatively low level logic circuit, the output buffer circuit comprising: a first power source; An inverting circuit including a first field effect element driven by a DC voltage from the input terminal and for inverting the polarity of a signal input to the input terminal, and a second and third field effect element connected in series. is driven by a DC voltage from a second power source, and a signal input to the input terminal is applied to the gate electrode of the second field effect element,
a push-pull circuit in which a signal inverted by the first field-effect element is applied to a gate electrode of the third field-effect element; and a connection between an output end of the inversion circuit and an output end of the push-pull circuit. and in response to the output level of the push-pull circuit becoming equal to or higher than a predetermined value, the voltage applied to the gate electrode of the second field effect element is controlled to reduce the output level of the push-pull circuit to a predetermined value or less. an output buffer circuit comprising a clamp circuit including a fourth field effect element that forces a direct current voltage from the second power source to the fourth field effect element;