JPH08321768A - Buffer circuit and semiconductor integrated circuit using the circuit - Google Patents

Abstract

PURPOSE: To speed up the operation. CONSTITUTION: An output circuit 20 has a series connection of a pMITS transistor(TR) p1 and an nMIS TR N1, a negative pule is fed from a leading edge detection circuit 21 to a gate of the pMIS TR P1 to turn on the pMIS TR P1 and a current flows from a power supply line Vdd to a load C through the pMIS TR P1. Furthermore, a positive pulse is fed from a trailing edge detection circuit 22 to a gate of the nMIS TR N1 to turn on the nMIS TR N1 and a current flows from the load C through the nMIS TR N1 to a power supply line Vss. While one of the pMIS TR P1 and the nMIS TR N1 is conductive, the other is nonconductive and since no through-current flows through the output current 20, the operation speed is high. When the TRs P1, N1 are nonconductive, an output level is kept constant by an output of a noninverting gate 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit for amplifying load driving capability and a semiconductor integrated circuit using the buffer circuit.

[0002]

2. Description of the Related Art CMIS (including CMOS) integrated circuits have the advantage of low power consumption, but with the increasing speed of MPU operations, there is a demand for higher speed operations.
The buffer circuit shown in FIG. 5 is for amplifying the load driving capability in the semiconductor integrated circuit, and a CMIS inverter 11 having a size smaller than that of the CMIS inverter 10 is cascade-connected in front of the CMIS inverter 10. The output terminal of the CMIS inverter 10 is connected to, for example, the gates of a large number of FETs (not shown), and the total load capacitance thereof is represented by C.

When the output of the CMIS inverter 11 transits from a high level to a low level, the pMIS transistor P1
Is turned on, the nMIS transistor N1 is turned off, and a current flows from the power supply line Vdd to the load capacitance C through the pMIS transistor P1. When the output of the CMIS inverter 11 transits from the low level to the high level, the pMIS transistor P1 is turned off and the nMIS transistor N1 is turned on, and a current flows from the load capacitance C through the nMIS transistor N1 to the power supply line (ground line) Vss.

[0004]

CMIS Inverter 1
In the state of the intermediate potential when the output of 1 transits between the high level and the low level, a through current flows from the power supply line Vdd through the pMIS transistor P1 and the nMIS transistor N1 to the power supply line Vss, and the CMIS inverter. 10
Is causing the slow operation.

In view of the above problems, it is an object of the present invention to provide a buffer circuit capable of further increasing the operation speed and a semiconductor integrated circuit using the same.

[0006]

In the buffer circuit of the first invention, there is provided a first edge detection circuit for detecting one of rising and falling edges of an input signal to generate a first pulse, and A second edge detection circuit that detects the other edge of the rising edge and the falling edge of the input signal and generates a second pulse, and a first a terminal is connected to the first power supply line and the first pulse is supplied to the gate. And a first FET whose second end is connected to a first power supply line having a lower potential than the first power supply line and a second FET end being connected to the second FET end. Connected to the gate and the second pulse is supplied to the gate to turn on between the first b end and the second b end, and an output circuit including a second FET, and a second FET of the second a end in response to the input signal. An auxiliary gate for maintaining a potential, the first edge detection circuit Second edge detection circuit and the auxiliary gate is constituted by said 1FET and said 2FET smaller size of the FET.

According to the first aspect of the present invention, when the input signal transits from one of the high level and the low level to the other, the first pulse of the first edge detection circuit turns on the first FET of the output circuit. A current flows from one power supply line to the load through the first FET. At this time, the second FE of the output circuit
Since T is off, a through current does not flow from the first FET to the second FET, and the output of the output circuit rises quickly. Even if the charge accumulated in the load leaks, the leaked charge is compensated by the output of the auxiliary gate and the output potential is maintained at a high level.

Further, when the input signal transits from the other of the high level and the low level to the one, the second pulse of the second edge detection circuit turns on the second FET of the output circuit. A current flows through the 2FET to the second power supply line. At this time, since the first FET of the output circuit is off, a through current does not flow from the first FET to the second FET, and the output of the output circuit falls at a high speed. Even if leakage charge from around the load flows into the load, the charge is removed by the output of the auxiliary gate, and the output potential is maintained at a low level.

In the first aspect of the first invention, the first FET is provided.
Is a pMIS transistor, and the second FET is nM
It is an IS transistor, and the first edge detection circuit, the second edge detection circuit, and the auxiliary gate are composed of a CMIS circuit. According to the first aspect, since the buffer circuit is the CMIS circuit, the power consumption can be reduced.

In the second aspect of the first invention, for example, as shown in FIG. 1, the first edge detection circuit detects a rising edge of the input signal Vi and generates a negative pulse as the first pulse. 21, the second edge detection circuit is a falling edge detection circuit 22 that detects a falling edge of the input signal Vi and generates a positive pulse as the second pulse, and the auxiliary gate is a non-inverting gate 23. is there.

In the third aspect of the first invention, for example, as shown in FIG. 2, the first edge detection circuit detects the falling edge of the input signal Vi and generates a negative pulse as the first pulse. The detection circuit 22 is the detection circuit 22, the second edge detection circuit is the rising edge detection circuit 21 which detects the rising edge of the input signal Vi and generates a positive pulse as the second pulse, and the auxiliary gate is the inversion gate 24. .

In the fourth aspect of the first invention, for example, as shown in FIG. 3, the first edge detection circuit delays the input signal Vi to invert the logic level, a delay circuit 27, the input signal Vi and the delay circuit. A NAND gate 25 for outputting a signal obtained by inverting the logical product of the output from the output circuit 27 as the first pulse, and the second edge detection circuit includes a delay circuit 27 and
The NOR gate 26 outputs a signal obtained by inverting the logical sum of the input signal Vi and the output of the delay circuit as the second pulse.

In a fifth aspect of the first aspect of the invention, one of the first edge detection circuit and the second edge detection circuit is an average potential of the potential of the first power supply line and the potential of the second power supply line. The rising edge of the input signal is detected at a lower threshold potential, and the other of the first edge detection circuit and the second edge detection circuit detects the falling edge of the input signal at a threshold potential higher than the average potential. To detect.

According to the fifth aspect, it is possible to further speed up the fall and rise of the output of the output circuit. In a normal inverter or a conventional buffer circuit in which a plurality of cascaded inverters are connected, even if the threshold potential of the FET is adjusted, only the fall or rise of the output can be speeded up. A semiconductor integrated circuit according to a second aspect of the invention has any of the above buffer circuits.

This buffer circuit is a circuit which is required to have driving capability in a semiconductor integrated circuit, for example, a clock buffer circuit which supplies a clock to clock input terminals of many flip-flops, and an output buffer circuit which drives an external circuit. It is used as such, and enables high speed operation of a semiconductor integrated circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a configuration example of the buffer circuit in FIG. The NAND gate 25 is a pMIS transistor P2.
And the pMIS transistor P3 are connected in parallel,
The S-transistor N2 and the nMIS transistor N3 are connected in series, and the gates of the pMIS transistor P2 and the nMIS transistor N3 are connected to each other to be one input terminal of the NAND gate 25.
And the nMIS transistor N2 have their gates connected to each other to form the other input terminal of the NAND gate 25, and the drains of the pMIS transistors P2 and P3 and the nMIS transistor N2 are connected to each other to form the output terminal of the NAND gate 25.

In the NOR gate 26, a pMIS transistor P4 and a pMIS transistor P5 are connected in series, and n
The MIS transistor N4 and the nMIS transistor N5 are connected in parallel, and the pMIS transistor P5 and the nMIS transistor N5 are connected in parallel.
The gates of the transistors N5 are connected to each other to serve as one input end of the NOR gate 26, and the pMIS transistor P
4 and the gate of the nMIS transistor N4 are connected to each other to serve as the other input end of the NOR gate 26, and the drains of the pMIS transistor P5 and the nMIS transistors N4 and N5 are connected to each other to serve as the output end of the NOR gate 26.

The signal Vi is supplied to one input terminal of the NAND gate 25 and the NOR gate 26, and the NAND gate 25 is supplied with the signal Vi.
A signal Vib obtained by delaying the signal Vi by the delay circuit 27 is supplied to the other input terminal of the NOR gate 26. The outputs of the NAND gate 25 and the NOR gate 26 are the signals Vu, respectively.
And as Vd, the pMIS transistor P of the output circuit 20.
1 and the gate of the nMIS transistor N1.

The delay circuit 27 is a CMIS inverter 27.
1 to 275 are connected in cascade, and CMIS inverter 271
Of the output circuit 2 via the CMIS inverter 28
It is connected to the output terminal of 0. CMIS inverter 27
The outputs of 1 and the output circuit 20 are referred to as signal Via and signal Vo, respectively. The NAND gate 25 and the delay circuit 27 shown in FIG.
Of the CMIS inverter 271 and the CM are configured by the NOR gate 26 and the delay circuit 27 to configure the falling edge detection circuit 22 of FIG.
The IS inverter 28 constitutes the non-inverting gate 23 of FIG. The transistor size of the NAND gate 25, the NOR gate 26, the delay circuit 27, and the CMIS inverter 28 is smaller than the transistor size of the output circuit 20.

Next, the operation of the buffer circuit configured as described above will be described. FIG. 3 is a timing chart showing the operation of this circuit. First, it is assumed that the potentials Vi and Vo are at a low level, the potentials Via and Vib are at a high level, and they are in a steady state. At this time, the NAND gate 25 has the pMIS
The transistor P2 and the nMIS transistor N2 are turned on, and the pMIS transistor P3 and the nMIS transistor N3 are turned off.
The IS transistor P1 is off. In the NOR gate 26, the pMIS transistor P5 and the nMIS transistor N4 are turned on, and the pMIS transistor P4 and nM are provided.
The IS transistor N5 is off, the potential Vd is low level, and the nMIS transistor N1 is off.

When the potential Vi transits to a high level from this state, the NAND gate 25 causes the nMIS transistor N
3 is turned on, the pMIS transistor P2 is turned off, the potential Vu is changed to the low level, and the pMIS transistor P1 is turned on.
Turns on. On the other hand, in the NOR gate 26, the nMIS transistor N5 is turned on, the pMIS transistor P5 is turned off, the potential Vd maintains a low level, and the nMIS transistor N1 remains off. Therefore, a current flows from the power supply line Vdd to the load capacitance C through the pMIS transistor P1 and the pMIS transistor P1 transfers to the nMI.
No through current flows to the S transistor N1.

Since the potential Vi changes to a high level and the nMIS transistor N3 turns on, the potential Vu changes to a low level. Therefore, (gate width) / (gate length) of the nMIS transistor N3 is increased to increase the nMIS transistor. By lowering the threshold voltage of N3, the fall of the potential Vu and the rise of the potential Vo can be made faster.

Next, the potential Via transits to the low level and CM
The output of the IS inverter 28 transitions to high level. Next, the potential Vib transits to the low level, which causes the nAND gate 25 to turn off the nMIS transistor N2 and pM.
The IS transistor P3 turns on, the potential Vu transits to a high level, and the pMIS transistor P1 turns off. On the other hand, the NOR gate 26 is connected to the pMIS transistor P.
4 turns on and the nMIS transistor N4 turns off,
Since the pMIS transistor P5 is off and the nMIS transistor N5 is on, the potential Vd maintains a low level, and the nMIS transistor N1 remains off. Therefore, the pMIS transistor P1 and the nMIS
The transistor N1 and the transistor N1 are not turned on at the same time, and no through current flows in the output circuit 20.

Since the transistor size of the NAND gate 25, the NOR gate 26, the delay circuit 27 and the CMIS inverter 28 is smaller than the transistor size of the output circuit 20, the NAND gate 25, the NOR gate 26 and the delay circuit 2 are provided.
7 and the CMIS inverter 28 when the inputs are at an intermediate potential, the through current flowing through them can be ignored. Even if the charge accumulated in the load capacitance C leaks, the CMIS inverter 28
Is high level, the leakage charge is compensated and the potential Vo is maintained at high level.

Next, when the potential Vi changes to a low level,
In the NAND gate 25, the nMIS transistor N3 is turned off and the pMIS transistor P2 is turned on.
S-transistor P3 is on, nMIS transistor N2
Is off, the potential Vu remains high and pM
The IS transistor P1 remains off. On the other hand, in the NOR gate 26, the nMIS transistor N5 is off, pM
The IS transistor P5 turns on, the potential Vd transitions to a high level, and the nMIS transistor N1 turns on.
Therefore, from the load capacitance C to the nMIS transistor N1
A current flows to the power supply line Vss through the through line, and a through current does not flow from the pMIS transistor P1 to the nMIS transistor N1.

The potential Vd transits to a high level when the potential Vi transits to a low level and the pMIS transistor P5 is turned on. Therefore, (gate width) / (gate length) of the pMIS transistor P5 is increased to increase the pMIS transistor. By raising the threshold voltage of P5, the rise of the potential Vd and the fall of the potential Vo can be made faster.

Next, the potential Via transits to a high level and CM
The output of the IS inverter 28 transits to the low level. Next, the potential Vib changes to the high level, which causes the NAND gate 25 to turn on the nMIS transistor N2 and pM.
The IS transistor P3 is turned off, but the pMIS transistor P2 is turned on and the nMIS transistor N3 is turned off, so that the potential Vu is maintained at a high level and the pMIS transistor P1 is still turned off. On the other hand, in the NOR gate 26, the pMIS transistor P4 is off and the nMIS is
The transistor N4 turns on, the potential Vd transits to the low level, and the nMIS transistor N1 turns off. Therefore, the pMIS transistor P1 and the nMIS transistor N1 are not turned on at the same time, and the output circuit 2
No through current flows in 0.

Even if leakage charges from the surroundings flow into the load capacitance C, the output of the CMIS inverter 28 is at a low level, so this charge is removed and the potential Vo is maintained at a low level. In addition, the present invention includes various modifications. For example, at the input end of the buffer circuit of FIG.
If one IS inverter is connected, the configuration example of the buffer circuit in FIG. 2 is obtained. Further, in FIG. 3, the NAND gate 2
5 and NOR gate 26 are replaced by AND gates and OR gates respectively, and the input end of the CMIS inverter 28 is connected to the output end of the CMIS inverter 271 and is connected to the input end of the buffer circuit. Is an example of the configuration.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a buffer circuit and one operation of one embodiment of the present invention.

FIG. 2 is a diagram showing a buffer circuit and another operation thereof according to another aspect of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a buffer circuit in FIG.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

FIG. 5 is a diagram showing a conventional buffer circuit.

[Explanation of symbols]

10, 11, 24, 271-275, 28 CMIS inverter 20 output circuit 21 rising edge detection circuit 22 falling edge detection circuit 23 non-inverting gate 25 NAND gate 26 NOR gate 27 delay circuit P1 to P5 pMIS transistor N1 to N5 nMIS transistor C load capacity

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03K 19/0948

Claims (7)

[Claims] 1. A first edge detection circuit for detecting one of rising and falling edges of an input signal to generate a first pulse, and detecting the other edge of rising and falling of the input signal. A second edge detection circuit for generating a second pulse; a first a terminal is connected to a first power supply line and the gate is supplied with the first pulse to turn on between the first a terminal and the second a terminal. The first FET and the second power supply line having a lower potential than the first power supply line, the 1b end is connected, the 2b end is connected to the 2a end, and the second pulse is supplied to the gate. 1b
An output circuit including a second FET that is turned on between an end and the second b end, and an auxiliary gate for maintaining the potential of the second a end according to the input signal, A buffer circuit, wherein the edge detection circuit, the second edge detection circuit, and the auxiliary gate are composed of an FET having a size smaller than the first FET and the second FET. 2. The first FET is a pMIS transistor, the second FET is an nMIS transistor, and the first edge detection circuit, the second edge detection circuit and the auxiliary gate are composed of a CMIS circuit. The buffer circuit according to claim 1, wherein the buffer circuit is a buffer circuit. 3. The first edge detection circuit is a rising edge detection circuit that detects a rising edge of the input signal and generates a negative pulse as the first pulse, and the second edge detection circuit is the input signal. 3. The buffer circuit according to claim 2, wherein the buffer circuit is a falling edge detection circuit that detects a falling edge of a positive pulse as the second pulse, and the auxiliary gate is a non-inverting gate. 4. The first edge detection circuit is a falling edge detection circuit that detects a falling edge of the input signal and generates a negative pulse as the first pulse, and the second edge detection circuit is The rising edge detection circuit for detecting a rising edge of an input signal and generating a positive pulse as the second pulse, wherein the auxiliary gate is an inverting gate. 5. The first edge detection circuit delays the input signal to invert the logic level, and a signal obtained by inverting the logical product of the input signal and the output of the delay circuit. A NAND gate for outputting as a pulse, wherein the second edge detection circuit includes the delay circuit, and a NOR gate for outputting as the second pulse a signal obtained by inverting the logical sum of the input signal and the output of the delay circuit. The buffer circuit according to claim 3, further comprising: 6. One of the first edge detection circuit and the second edge detection circuit has the threshold potential lower than an average potential of the potential of the first power supply line and the potential of the second power supply line. The rising edge of the input signal is detected, and the other of the first edge detection circuit and the second edge detection circuit detects the falling edge of the input signal at a threshold potential higher than the average potential. The buffer circuit according to claim 1. 7. A semiconductor integrated circuit comprising the buffer circuit according to claim 1. Description: