JP2005115365A - High slew rate amplifier circuit for driving tft-lcd - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit of a large slew rate for driving a TFT-LCD. <P>SOLUTION: The slew rate amplifier circuit for driving the TFT-LCD includes an OP amplifier, a pull-up transistor (TR) connected to the output end of the OP amplifier, a pull-down transistor (TR) connected to the output end of the OP amplifier and a control circuit for selectively activating the pull-up TR and the pull-down TR, respectively. As a result, load can be rapidly charged and discharged when the amplifier circuit is used for an output buffer for the purpose of driving the source line of a liquid crystal display device and therefore an after-image effect can be eliminated. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor (TFT) -liquid crystal display (LCD), and more particularly to a source line driving circuit of an LCD panel included in a TFT-LCD.

  The LCD is one of the most widely used flat panel displays. The LCD panel is composed of an upper plate and a lower plate having a number of electrodes for forming an electric field. There is a liquid crystal layer between the upper plate and the lower plate, and the upper plate is also used to polarize light. And a polarizing plate attached to the lower plate. In the LCD, the luminous intensity is adjusted by applying a grayscale voltage to an electrode for rearranging liquid crystal molecules. The lower panel of the LCD panel is provided with a number of switching elements such as TFTs connected to the electrodes in order to switch the grayscale voltage to be applied to the electrodes.

  The LCD includes a driving circuit unit including a source driving unit and a gate driving unit, and a controller unit that controls the driving circuit unit in order to supply a grayscale voltage to an electrode through a switching element. In general, the controller unit is disposed outside the LCD panel, and the drive circuit unit is disposed on the LCD panel or outside the LCD panel.

  FIG. 1 is a block diagram showing a conventional output buffer for buffering gradation voltages applied to an LCD panel. In FIG. 1, the output buffer includes N R2R amplifiers 102, each of which buffers any one of the N source voltages buffered in parallel. Ring. While amplifier 102 as shown in FIG. 1 exhibits good slew rate output characteristics, there are still problems to be solved. That is, there is a problem in that current consumption is large and the layout of the source driving circuit occupies a large layout area.

  FIG. 2 is a block diagram illustrating another conventional output buffer for improving the amplifier characteristics shown in FIG. In FIG. 2, the output buffer includes a number of amplifier circuits 202 and a controller 208. Each of the amplification circuits 202 includes a P-type OP amplifier (operation amplifier) 204 that buffers one source voltage using a P-type transistor, and an N-type that buffers one source voltage using an N-type transistor. An OP amplifier 206 is provided.

  As is well known, in order to prevent the material characteristics of the liquid crystal injected into the LCD panel from being deteriorated, the output buffer is set to a positive voltage greater than the common voltage Vcom and a negative voltage smaller than the common voltage Vcom. Supply. For example, the common voltage Vcom may have a constant ½ VDD voltage, or the voltage may be a voltage that is applied in various ways and is repeated in units of frames. The P-type OP amplifier 204 buffers the positive voltage among the grayscale voltages in a mutually inverted relationship, and the N-type OP amplifier 206 buffers the negative voltage among the grayscale voltages. The output terminals of the P-type OP amplifier 204 and the N-type OP amplifier 206 are interconnected. The controller 208 turns off the N-type OP amplifier 206 when the P-type OP amplifier 204 is turned on, and turns off the P-type OP amplifier 204 when the N-type OP amplifier 206 is turned on.

  The controller 208 turns on / off the OP amplifiers 204 and 206 through the first control signal CTL-H and the second control signal CTL-L. A timing controller (not shown) generates a polarity signal POL indicating the polarity of the grayscale voltage output through the output buffer, whereby the controller 208 receives the control signal CTL-H, under the control of the polarity signal POL. Generate CTL-L.

  FIG. 3 is a timing diagram for explaining the operation of the output buffer of FIG. FIG. 3A is a waveform diagram showing an output enable signal generated by the timing controller. FIG. 3B is a waveform diagram showing the polarity signal POL. 3C and 3D are waveform diagrams showing the first control signal CTL-H and the second control signal CTL-L output from the controller 208, respectively. FIG. 3E is a waveform diagram VH PART showing the output of the P-type OP amplifier 204. FIG. 3F is a waveform diagram VL PART showing the output of the N-type OP amplifier 206.

  As shown in FIGS. 3C and 3E, the output waveform VH PART of the P-type OP amplifier 204 is the same as the polarity of the first control signal CTL-H. Similarly, as shown in FIGS. 3D and 3F. In addition, the output waveform VL PART of the N-type OP amplifier 206 is the same as the polarity of the second control signal CTL-L. However, as indicated by reference numeral 302, the output waveform VH PART of the P-type OP amplifier 204 has a long rise time, and as indicated by reference numeral 304, the output waveform VL PART of the N-type OP amplifier 206 has a long fall time.

  As described above, the conventional output buffer characteristic has a slow rise time and fall time, so that an LCD having the same has a problem of displaying an afterimage when displaying a moving image.

  A technical problem to be solved by the present invention is to provide an amplifier circuit having a large slew rate in order to drive an LCD.

  A high slew rate amplifier circuit for driving a TFT-LCD according to the present invention for achieving the above technical problem includes an OP amplifier, a pull-up transistor connected to an output terminal of the OP amplifier, and the OP amplifier. And a pull-down transistor connected to an output terminal, and a control circuit for selectively activating each of the pull-up transistor and the pull-down transistor.

  The control circuit may selectively activate each of the pull-up transistor and the pull-down transistor in a time shorter than a half of a polarity signal period or an output enable signal period. The control circuit may selectively activate each of the pull-up transistor and the pull-down transistor in a time shorter than 1/20 of the polarity signal period or 1/10 of the output enable signal period. . The control circuit may selectively activate each of the pull-up transistor and the pull-down transistor in a time shorter than 1/200 of the polarity signal period or 1/100 of the output enable signal period. .

  The control circuit generates and outputs a low signal generator for generating and outputting a first pulse for determining the activation time of the pull-up transistor, and a high signal for generating and outputting a second pulse for determining the activation time of the pull-down transistor. And a signal generation unit. The first pulse and the second pulse are determined by a function with respect to an output enable signal. Each of the low signal generation unit and the high signal generation unit includes at least one delay unit that delays the output of each pulse from the output enable signal.

  The OP amplifier includes a positive signal amplifier circuit and a negative signal amplifier circuit. The positive polarity signal amplifier circuit has a voltage follower configuration including a plurality of transistors. The positive signal amplifier circuit further includes at least one capacitor. The negative polarity signal amplifier circuit has a voltage follower configuration including a plurality of transistors. The negative signal amplification circuit further includes at least one capacitor.

  The pull-up transistor is connected to an output terminal of the positive signal amplifier circuit, and the pull-down transistor is connected to an output terminal of the negative signal amplifier circuit. The control circuit can selectively control each of the pull-up transistor and the pull-down transistor under the control of an output enable signal.

  An LCD according to the present invention for achieving the above technical problem includes an LCD panel and a plurality of source drivers connected to the LCD panel, each of the source drivers including an output buffer, and the output. The buffer selectively activates an OP amplifier, a pull-up transistor connected to the output terminal of the OP amplifier, a pull-down transistor connected to the output terminal of the OP amplifier, and each of the pull-up transistor and the pull-down transistor. And a control circuit for generating the control circuit.

  The control circuit includes a time shorter than 1/2 of the polarity signal period, a time shorter than the output enable signal period, a time shorter than 1/20 of the polarity signal period, and a time shorter than 1/10 of the output enable signal period. The pull-up transistor and the pull-down transistor can be selectively activated at any one of a time shorter than 1/200 of the polarity signal period and a time shorter than 1/100 of the output enable signal period. It is characterized by that.

  The amplifier circuit according to the present invention as described above improves the slew rate characteristic. Therefore, when used as an output buffer for driving the source line of the LCD, the load is quickly charged / discharged, so that an afterimage effect can be eliminated.

  For a full understanding of the invention, its operational advantages, and the objectives achieved by the practice of the invention, reference should be made to the drawings illustrating the preferred embodiments of the invention and the contents described in the drawings. Don't be.

  Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numerals provided in each drawing denote the same members.

  Some items according to an embodiment of the present invention are based on the following points. Adding one or more pull-up / pull-down transistors to the output terminals of the P-type OP amplifier and the N-type OP amplifier can substantially improve the rise / fall time. However, if the pull-up / pull-down transistor is operated at a similar time or substantially the same time as the OP amplifier, the pull-up / pull-down transistor will also substantially increase the amount of current consumed by the output buffer. Let If one or more pull-up / pull-down transistors are operated in a shorter time than the OP amplifier, the rise / fall time can be significantly improved without increasing the amount of current consumed by the output buffer.

  FIG. 4 is a block diagram illustrating an LCD 400 according to an embodiment of the present invention. Referring to FIG. 4, the LCD 400 includes a TFT-LCD 404 and a graphic controller 402 that provides display data to the TFT-LCD 404. The graphic controller 402 according to an exemplary embodiment of the present invention includes a signal transmission unit 406 that transmits the display data to a signal reception unit 416 included in the TFT-LCD 404. Various signal processing techniques, in particular, low voltage differential signaling (LVDS) techniques may be applied to the signal transmission unit 406 and the signal reception unit 416.

  Referring to FIG. 4, the TFT-LCD 404 further includes a timing controller 408, a gate driving unit 412, a source driving unit 414, and a TFT-LCD panel 410. The signal receiving unit 416 is a part of the timing controller 408, and the timing controller 408 includes a signal transmitting unit 418. The timing controller 408 processes display data received from the signal receiver 416 and transmits the processed data to the gate driver 412 and the source driver 414 through the signal transmitter 418. The signal transmission unit 418 may use a signal processing technology such as the signal transmission unit 406 and the signal reception unit 416, for example, an LVDS technology. Alternatively, other techniques, such as a reduced swing differential signaling (RSDS) technique, may be used. The RSDS technique is a technique well known to those skilled in the art.

  FIG. 5 is a block diagram illustrating the source driver 414 according to an embodiment of the present invention. The source driver 414 includes an N-bit shift register 502, a data latch 504, a digital / analog converter 506, and an output buffer 508. Such components are continuously connected so that data is output from the timing controller 408 and output to the TFT-LCD panel 410 via 502 to 508. The digital-analog converter 506 can be implemented with a resistor or a capacitor.

  FIG. 6 is a block diagram illustrating an output buffer 600 according to one embodiment of the present invention. The output buffer 600 has the same function as the output buffer 508 of FIG.

  The output buffer 600 of FIG. 6 includes a plurality of amplifier circuits 602, a first controller 608, and a second controller 616. Each of the multiple amplifier circuits 602 includes a first OP amplifier 604, a second OP amplifier 606, at least one pull-up transistor 612, and at least one pull-down transistor 610. According to an embodiment of the present invention, the first OP amplifier 604 may be an N-bit OP amplifier configured with a P-type transistor, and the second OP amplifier 606 may be an N-bit OP amplifier configured with an N-type transistor. Here, N is a positive integer and is the number of input data. For example, each of the OP amplifiers 604 and 606 may be an OP amplifier having the voltage follower configuration shown in FIGS. 10A and 10B. In order to further improve the affinity, the pull-up transistor 612 is preferably a P-type that is an impurity form like the transistor constituting the first OP amplifier 604. Similarly, it is desirable that the pull-down transistor 610 be an N-type which is an impurity form like the transistor constituting the second OP amplifier 606.

  The first controller 608 of FIG. 6 generates control signals CTL-H and CTL-L to control the first OP amplifier 604 and the second OP amplifier 606, respectively. The first OP amplifier 604 processes the positive polarity signal of the input signal that is periodically repeated, and the second OP amplifier 606 processes the negative polarity signal of the input signal that is periodically repeated. Here, the periodically repeated input signal is output from the digital-analog converter 506. The output terminals of the first OP amplifier 604 and the second OP amplifier 606 are interconnected, and the output signal of the output buffer 600 is output from this output terminal.

  The first controller 608 controls the second OP amplifier 606 to be turned off when the first OP amplifier 604 is turned on or activated, and conversely, when the second OP amplifier 606 is turned on or activated. The first OP amplifier 604 is controlled to be turned off. The first controller 608 turns on / off the second OP amplifier 606 through a second control signal CTL-L, and turns on / turn off the first OP amplifier 604 through a first control signal CTL-H. The timing controller 408 generates a polarity signal POL that indicates the polarity of data output through the output buffer 600, whereby the first controller 608 is controlled by the polarity signal POL to control the control signals CTL-H and CTL-. L is generated.

  The output terminals of the first OP amplifier 604 and the second OP amplifier 606 may be connected to the system source voltage VDD through the pull-up transistor 612 and may be connected to the system ground voltage VSS through the pull-down transistor 610.

  The second controller 616 in FIG. 6 controls the pull-up transistor 612 and the pull-down transistor 610 through a first pulse (Half Pull Up: HPU) and a second pulse (Half Pull Down: HPD), respectively. Before it will be described later, the pull-up transistor 612 and the pull-down transistor 610 are operated for a shorter time than the first OP amplifier 604 and the second OP amplifier 606, thereby significantly increasing the amount of current consumed by the output buffer 600. Without any increase in the rise / fall time. Each of the pull-up transistor 612 and the pull-down transistor 610 is operated through the first pulse HPU and the second pulse HPD generated by the second controller 616.

  FIG. 7 is a block diagram illustrating the second controller 616 of FIG. 6 according to one embodiment of the present invention.

  The second controller 616 of FIG. 6 includes a low signal generation unit 704 and a high signal generation unit 704 that generate the first pulse HPU and the second pulse HPD, respectively, under the control of the output enable signal OE. Here, the output enable signal OE may be generated by the timing controller 408 of FIG.

  FIG. 8A is a block diagram illustrating the high signal generator 702 of FIG. 7 according to an embodiment of the present invention. The high signal generator 702 includes a number of non-inverting (or buffering) circuits 802 (here, for example, four), an inverter 804, and an OR gate 806. The plurality of non-inverting circuits 802 are connected in series between the output enable signal OE and the inverter 804. The output terminal of the inverter 804 is connected to one of the two input terminals of the OR gate 806. The other input terminal of the OR gate 806 directly receives the output enable signal OE. The high signal generator 702 delays the turn-on time of the pull-up transistor 612 from the turn-on time of the first OP amplifier 604, and pulls up the pull-up signal in a time relatively shorter than the turn-on time of the P-type first OP amplifier 604. Transistor 612 is turned on.

  FIG. 8B is a block diagram illustrating the low signal generator 704 of FIG. 7 according to an embodiment of the present invention. The low signal generation unit 704 includes a number of non-inverting (or buffering) circuits 808 (here, for example, four), an inverter 810, and an AND gate 812. The plurality of non-inverting circuits 808 are connected in series between the output enable signal OE and the inverter 810. The output terminal of the inverter 810 is connected to one of the two input terminals of the AND gate 812. The other input terminal of the AND gate 812 directly receives the output enable signal OE. The low signal generator 704 delays the turn-on time of the pull-down transistor 610 from the turn-on time of the second OP amplifier 606, and reduces the pull-down transistor 610 in a time relatively shorter than the turn-on time of the N-type second OP amplifier 606. Turn on.

  Hereinafter, the turn-on time (or operation time) of the pull-up transistor 612 and the pull-down transistor 610 will be described mathematically. The polarity signal POL period is assumed to be about 80 μs. As described above, the first OP amplifier 604 operates during the positive polarity period of the polarity signal POL, and the second OP amplifier 606 operates during the negative polarity period of the polarity signal POL. At this time, the first OP amplifier 604 and the second OP amplifier 606 are turned on for about 40 μs. Each of the pull-up transistor 612 and the pull-down transistor 610 may be turned on after a delay time of about 0.5 μs after the polarity signal POL transitions from positive polarity to negative polarity (or from negative polarity to positive polarity). Each of the pull-up transistor 612 and the pull-down transistor 610 can be kept turned on for 0.1 μs, and thereafter can be turned off until the next transition after the polarity signal POL.

  A person skilled in the art can understand that the delay time, the turn-on time, and the like may vary depending on the situation where the output buffer 600 is applied. The turn-on time (or activation time) is selected for an economic purpose that can reduce the return of products that have been marketed. As the turn-on time increases, the amount of current consumed by the output buffer 600 increases and the slew rate is further improved. Therefore, an appropriate choice must be made between the disadvantage of increased power consumption and the advantage of improved slew rate.

  Each of the pull-up transistor 612 and the pull-down transistor 610 is activated at any one of a time shorter than 1/20 of the polarity signal period POL and a time shorter than 1/10 of the output enable signal OE period. In some cases. In addition, each of the pull-up transistor 612 and the pull-down transistor 610 is activated at any one of a time shorter than 1/200 of the polarity signal period POL or a time shorter than 1/100 of the output enable signal OE period. There is also a case.

  FIG. 9 is a timing diagram for explaining the operation of the output buffer 600 of FIG. 6 according to an embodiment of the present invention. FIG. 9A is a waveform diagram showing an output enable signal OE that can be generated by the timing controller 408 of FIG. FIG. 9B is a waveform diagram showing the polarity signal POL. 9C and 9D are waveform diagrams showing the first control signal CTL-H and the second control signal CTL-L generated by the first controller 608 of FIG. FIG. 9E is a waveform diagram showing the first pulse HPU. FIG. 9F is a waveform diagram showing the second pulse HPD. FIG. 9G is a waveform diagram (VH PART) showing an output signal of the first OP amplifier 604 when pulled up by the pull-up transistor 612 by the first pulse HPU. FIG. 9H is a waveform diagram (VL PART) showing an output signal of the second OP amplifier 606 when it is pulled down by the pull-down transistor 610 by the second pulse HPD.

  As shown in FIGS. 9C and G, the output signal waveform VH PART of the first OP amplifier 604 is the same as the polarity of the first control signal CTL-H, and similarly, as shown in FIGS. 9D and 9H. The output waveform VL PART of the second OP amplifier 606 is the same as the polarity of the second control signal CTL-L. However, unlike the prior art, its tracking slew rate is even better. That is, as shown by reference number 902, the output signal waveform VH PART of the first OP amplifier 604 has a fast rise time, and as shown by reference number 904, the output waveform VL PART of the second OP amplifier 606 has a fast fall time. Therefore, since the RC (Resitive-Capacitive) load of the source line is very large in the LCD panel 410 of FIG. 4, the output buffer 600 of FIG. 6 fills the source line load faster than the conventional output buffer of FIG. Can discharge.

  FIG. 10A is an example showing a circuit diagram of the first OP amplifier 604 and the pull-up transistor 610 of FIG. FIG. 10B is an example showing a circuit diagram of the second OP amplifier 606 and the pull-down transistor 610 of FIG.

  In FIG. 10A, the first OP amplifier 604 has a voltage follower configuration including a plurality of transistors 1002 to 1016. The first OP amplifier 604 may further include at least one capacitor 1018. Since voltage followers are well known to those skilled in the art, a detailed description thereof will be omitted. In FIG. 10A, the input signal INPUT input to the input terminal is converted to the output signal OUTPUT through the output terminal in response to the first pulse HPU.

  In FIG. 10B, the second OP amplifier 606 has a voltage follower configuration including a plurality of transistors 1022 to 1036. The second OP amplifier 606 may further include at least one capacitor 1038. Since the voltage follower is well known to those skilled in the art, a detailed description is omitted. In FIG. 10B, the input signal INPUT input to the input terminal is converted to the output signal OUTPUT through the output terminal in response to the second pulse HPD.

  As described above, the optimum embodiment has been disclosed in the drawings and specification. Although specific terms are used herein, they are merely used to describe the present invention and are intended to limit the scope of the invention as defined in the meaning and claims. It was not used for Accordingly, those skilled in the art can understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The slew rate amplifier circuit according to the present invention can be used for a source line driving circuit of an LCD panel included in a TFT-LCD.

It is a block diagram which shows the conventional output buffer. It is a block diagram which shows the other conventional output buffer. FIG. 3 is a timing diagram for explaining the operation of the output buffer of FIG. 2. 1 is a block diagram illustrating an LCD according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a source driver according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating an output buffer according to an embodiment of the present invention. FIG. 7 is a block diagram illustrating a second controller of FIG. 6 according to an embodiment of the present invention. FIG. 8 is a block diagram illustrating a high signal generation unit of FIG. 7 according to an embodiment of the present invention. FIG. 8 is a block diagram illustrating a low signal generation unit of FIG. 7 according to an embodiment of the present invention. FIG. 7 is a timing diagram for explaining an operation of the output buffer of FIG. 6 according to an embodiment of the present invention. FIG. 7 is a circuit diagram illustrating an example of a first OP amplifier and a pull-up transistor in FIG. 6. FIG. 7 is a circuit diagram illustrating an example of a second OP amplifier and a pull-down transistor in FIG. 6.

Explanation of symbols

600 output buffer 602 amplifier circuit 604 first OP amplifier 606 second OP amplifier 608 first controller 610 pull-down transistor 612 pull-up transistor 616 second controller POL polarity signal OE output enable signal CTL-L second control signal CTL-H first control signal HPD 2nd pulse HPU 1st pulse VDD System source voltage VSS System ground voltage

Claims (29)

With an OP amp,
A pull-up transistor connected to the output terminal of the OP amplifier;
A pull-down transistor connected to the output terminal of the OP amplifier;
And a control circuit for selectively activating each of the pull-up transistor and the pull-down transistor, and a high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device. The control circuit is
2. The thin film transistor liquid crystal display device according to claim 1, wherein each of the pull-up transistor and the pull-down transistor can be selectively activated in a time shorter than a half of a polarity signal period or an output enable signal period. High slew rate amplifier circuit for driving. The control circuit is
3. The pull-up transistor and the pull-down transistor can be selectively activated in a time shorter than 1/20 of the polarity signal period or 1/10 of the output enable signal period. High-slew rate amplifier circuit for driving a thin film transistor liquid crystal display device. The control circuit is
4. The pull-up transistor and the pull-down transistor can be selectively activated in a time shorter than 1/200 of the polarity signal period or 1/100 of the output enable signal period. High-slew rate amplifier circuit for driving a thin film transistor liquid crystal display device. The control circuit is
A low signal generator for generating and outputting a first pulse for determining an activation time of the pull-up transistor;
The high-throughput for driving the thin film transistor liquid crystal display device according to claim 1, further comprising: a high signal generation unit that generates and outputs a second pulse that determines an activation time of the pull-down transistor. Rate amplification circuit. The first pulse and the second pulse are:
6. The high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 5, wherein the high slew rate amplifier circuit is determined by a function for an output enable signal. Each of the low signal generator and the high signal generator is
6. The high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 5, further comprising at least one delay unit for delaying an output of each pulse from an output enable signal. The operational amplifier is
2. The high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 1, further comprising a positive signal amplifier circuit and a negative signal amplifier circuit. The positive polarity signal amplification circuit includes:
9. The high-slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 8, wherein the high-rate amplifier circuit has a voltage follower configuration including a plurality of transistors. The positive polarity signal amplification circuit includes:
The high slew rate amplifier circuit for driving the thin film transistor liquid crystal display device according to claim 9, further comprising at least one capacitor. The negative polarity signal amplifier circuit includes:
9. The high-slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 8, wherein the high-rate amplifier circuit has a voltage follower configuration including a plurality of transistors. The negative polarity signal amplifier circuit includes:
The high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 11, further comprising at least one capacitor. The pull-up transistor is
2. The thin film transistor liquid crystal display device according to claim 1, wherein the thin film transistor liquid crystal display device is connected to an output terminal of the positive polarity signal amplifier circuit, and the pull-down transistor is connected to an output terminal of the negative polarity signal amplifier circuit. High slew rate amplifier circuit. The control circuit is
9. The high slew rate amplifier circuit for driving a thin film transistor liquid crystal display device according to claim 8, wherein each of the pull-up transistor and the pull-down transistor can be selectively controlled under the control of an output enable signal. OP amplifier means,
Pull-up means for pulling up an output signal of the OP amplifier means;
Pull-down means for pulling down the output signal of the OP amplifier means;
And a control means for selectively turning on / off each of the pull-up means and the pull-down means, and a high slew rate amplifying device for driving a thin film transistor liquid crystal display device. The control means includes
16. The driving of a thin film transistor liquid crystal display device according to claim 15, wherein each of the pull-up means and the pull-down means can be selectively turned on at a time shorter than a half of a polarity signal period or an output enable signal period. High slew rate amplification device for. The control means includes
The pull-up transistor and the pull-down transistor can be selectively turned on in a time shorter than 1/20 of the polarity signal period or 1/10 of the output enable signal period. High slew rate amplifier for driving thin film transistor liquid crystal display devices. The control means includes
18. The pull-up transistor and the pull-down transistor can be selectively turned on in a time shorter than 1/200 of the polarity signal period or 1/100 of the output enable signal period. High slew rate amplifier for driving thin film transistor liquid crystal display devices. The control means includes
Low signal generating means for providing a first pulse for determining a turn-on time of the pull-up means;
16. The high slew rate amplifying apparatus for driving a thin film transistor liquid crystal display device according to claim 15, further comprising a high signal generating means for providing a second pulse for determining a turn-on time of the pull-down means. The first pulse and the second pulse are:
20. The high slew rate amplifying device for driving a thin film transistor liquid crystal display device according to claim 19, which is controlled by an output enable signal. Each of the low signal generation means and the high signal generation means,
20. The high slew rate amplifying device for driving a thin film transistor liquid crystal display device according to claim 19, further comprising at least one delay means for delaying the output of each pulse from the output enable signal. The OP amplifier means includes:
Comprising positive polarity signal amplification means and negative polarity signal amplification means,
16. The thin film transistor liquid crystal display device according to claim 15, wherein the pull-up means pulls up the output terminal of the positive polarity signal amplification means, and the pull-down means pulls down the output terminal of the negative polarity signal amplification means. High slew rate amplifier for driving. The control means includes
16. The high slew rate amplifier for driving a thin film transistor liquid crystal display according to claim 15, wherein each of the pull-up transistor and the pull-down transistor can be selectively controlled under the control of an output enable signal. An LCD panel;
A plurality of source drivers coupled to the LCD panel;
Each of the source drivers comprises an output buffer,
The output buffer is
With an OP amp,
A pull-up transistor connected to the output terminal of the OP amplifier;
A pull-down transistor connected to the output terminal of the OP amplifier;
And a control circuit that selectively activates each of the pull-up transistor and the pull-down transistor. The control circuit is
A time shorter than half of the polarity signal period;
A time shorter than the output enable signal period;
A time shorter than 1/20 of the polarity signal period;
A time shorter than 1/10 of the output enable signal period;
A time shorter than 1/200 of the polarity signal period;
25. The liquid crystal display device according to claim 24, wherein each of the pull-up transistor and the pull-down transistor can be selectively activated during any one of times shorter than 1/100 of an output enable signal period. . The control circuit is
A low signal generator for generating and outputting a first pulse for determining an activation time of the pull-up transistor;
A high signal generation unit that generates and outputs a second pulse for determining an activation time of the pull-down transistor,
The liquid crystal display device of claim 25, wherein the first pulse and the second pulse are determined by a function with respect to an output enable signal. Each of the low signal generator and the high signal generator is
27. The liquid crystal display device according to claim 26, further comprising at least one delay unit that delays the output of each pulse from an output enable signal. The operational amplifier is
A positive polarity signal amplification circuit and a negative polarity signal amplification circuit;
26. The liquid crystal display of claim 25, wherein the pull-up transistor is connected to an output terminal of the positive polarity signal amplifier circuit, and the pull-down transistor is connected to an output terminal of the negative polarity signal amplifier circuit. The control circuit is
26. The liquid crystal display device according to claim 25, wherein each of the pull-up transistor and the pull-down transistor can be selectively controlled under the control of an output enable signal.

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