JPS60132392A - High density multilayer circuit board - Google Patents
High density multilayer circuit boardInfo
- Publication number
- JPS60132392A JPS60132392A JP8208783A JP8208783A JPS60132392A JP S60132392 A JPS60132392 A JP S60132392A JP 8208783 A JP8208783 A JP 8208783A JP 8208783 A JP8208783 A JP 8208783A JP S60132392 A JPS60132392 A JP S60132392A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- circuit board
- conductor
- multilayer circuit
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は大型コンピー−り等に用いるＬＳＩもしくは超
ＬＳＩを実装する高密度多層回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-density multilayer circuit board on which an LSI or very large scale integrated circuit (LSI) for use in large-scale computers or the like is mounted.
従来技術
従来この種の高密度多層回路基板は、第１図に示すよう
に、絶縁基板１と、絶縁基板１上に形成された金属導体
層２と、この金属導体）ＷＩ２と絶縁基板１とを覆うよ
うにかつ上下金属導体層接続用穴（以下ダイアホール）
を明けた有機絶縁層３と、この有機絶縁Ｊｉｉ３および
金属導体層２に接続するように形成された第２番目の金
属導体層５とから構成されている。しかしながら、有機
絶縁層３の膜厚が２０μ（ミクロン９以上でかつ」ニ下
）Ｍ接続のためのダイアホール径が５０μ（ミクロン）
以下となると金属導体層２と金属導体層５の接続が困難
となる。特に金属導体層５のダイアホール部分の形成が
ダイアホール径と段差の関係から困難となり首切れ状態
となる。し／ζかって、多層回路基板形成後の電気検査
で回路オープン不良および信頼性上重大な問題を発生す
るといつ欠点がある。Prior Art Conventionally, this type of high-density multilayer circuit board, as shown in FIG. and holes for connecting the upper and lower metal conductor layers (hereinafter referred to as dia holes)
The second metal conductor layer 5 is formed to be connected to the organic insulating layer 3 and the metal conductor layer 2. However, the film thickness of the organic insulating layer 3 is 20 μm (more than 9 microns and below 2 μm), and the diameter of the dia hole for M connection is 50 μm (microns).
Below this, it becomes difficult to connect the metal conductor layer 2 and the metal conductor layer 5. In particular, it becomes difficult to form the dia hole portion of the metal conductor layer 5 due to the relationship between the dia hole diameter and the difference in level, resulting in a broken state. However, there is a drawback when a circuit open failure and a serious reliability problem occur during electrical inspection after forming a multilayer circuit board.
発明の目的
本発明の目的は上述の欠点′ｆ：Ｐ＃決し、金属層間の
接続を確実にするようにした高密度多層回路基板を提供
することにある。OBJECTS OF THE INVENTION It is an object of the present invention to provide a high-density multilayer circuit board which overcomes the above-mentioned drawbacks and ensures reliable connections between metal layers.
発明の構成
本発明の高密度多層回路基板の構造は、絶縁基板と、
機絶縁層と、
前記上下金属導体層接続穴にうめ込−まれ／こ低温焼成
金属ど、
前記有機絶縁上および低温焼成金属上に形成された第２
の金属導体層とからなる層を多層にしたことを特徴とす
る。Structure of the Invention The structure of the high-density multilayer circuit board of the present invention includes: an insulating substrate, a mechanical insulating layer, a low-temperature-fired metal embedded in the connection hole of the upper and lower metal conductor layers, and a low-temperature-fired metal on the organic insulation layer and a low-temperature-fired metal. second formed on metal
It is characterized by having a multilayer structure consisting of a metal conductor layer and a metal conductor layer.
発明の実施例 次に本発明について図面を参照して詳卸１に説明する。Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.
第２図を参照すると、本発明の一実施例は９７チのアル
ミナからなるセラミック基板１１と、このセラミック基
板１１上にチタンＴｉ、クロムＯｒ。Referring to FIG. 2, one embodiment of the present invention includes a ceramic substrate 11 made of 97-inch alumina, and titanium Ti and chromium Or on the ceramic substrate 11.
タングステンＷ、パラジウムＰｄ等を下地とした金Ａｕ
導体パターン（第１導体Ｉｃ１）１２と、この第１導体
層１２の上のあらかじめ必要部分をダイアホールとして
明けである３０μ（ミクロン）厚のポリイミド絶縁Ｎ１
３と、前記ダイアホール部分にうめ込まれた低温焼結金
（Ａｕ）導体１４と、この低温焼結Ａｕ導体１４および
ポリイミド絶縁（第２導体層）１５とから構成されてい
る。Gold Au based on tungsten W, palladium Pd, etc.
A conductor pattern (first conductor Ic1) 12 and a polyimide insulation N1 with a thickness of 30μ (microns) are formed by making a necessary part on this first conductor layer 12 a dia hole in advance.
3, a low temperature sintered gold (Au) conductor 14 embedded in the dia hole portion, and this low temperature sintered Au conductor 14 and polyimide insulation (second conductor layer) 15.
ここで低温焼結金（Ａｕ）導体１４としては次の２蝋類
がある。１つは金（Ａｕ）粉体と４００’″Ｃで焼結す
る無機粉末ガラスからなる低温焼成金（Ａｕ）ペースト
をダイアホールにうめ込み印刷し焼成ぜせたものである
。Here, the following two waxes are available as the low temperature sintered gold (Au) conductor 14. One is a low-temperature fired gold (Au) paste made of gold (Au) powder and inorganic powdered glass sintered at 400'''C, which is embedded in a dia hole, printed, and fired.
他の１つは金（Ａｕ）ノ超微粉（１００ＯＡ）−にダイ
アホール部分に直接仲人４０ ｎ ”ＴＪＬ焼結させた
ものである。The other one is made by sintering ultrafine gold (Au) powder (100 OA) directly onto the diahole portion to a diameter of 40 n'' TJL.
いずれの場合も４００℃という低温で焼結させているた
め金（Ａｕ）導体１４の形成時（、／ｆｌポリイミドの
耐熱範囲に人っｔ・繁り、絶縁層１３の炭化による劣化
の問題はない。In both cases, since sintering is carried out at a low temperature of 400°C, there is no problem of deterioration due to carbonization of the insulating layer 13 during the formation of the gold (Au) conductor 14. .
本高蕾度多層回路基板ではダイアホールの大きさが５０
μ×５０μかつポリイミド絶縁層１３の厚さが３０μに
もかかわらず低温焼結金（Ａｕ ）導体１４をうめ込む
構成により第１導体層１１と第２導体層１５のダイアホ
ール部分段差が小さくなり接続が確実となる。The diameter of the diameter hole in this high bud multilayer circuit board is 50mm.
Despite the size of μ×50μ and the thickness of the polyimide insulating layer 13 of 30μ, the structure in which the low-temperature sintered gold (Au) conductor 14 is embedded reduces the step difference in the diameter hole portion between the first conductor layer 11 and the second conductor layer 15. The connection is secure.
このように本発明の一実施例による効果はポリイミド絶
縁を使った多層化における欠陥を無くした高密度多層回
路基板を得ることができることにある。As described above, the effect of one embodiment of the present invention is that it is possible to obtain a high-density multilayer circuit board that eliminates defects caused by multilayering using polyimide insulation.
発明の効果
本発明には有機絶縁のダイアホールに低温焼結、金属を
うめ込むことにより確実かつ信頼性の高い高密度多層回
路基板を構成できるという効果がある０Effects of the Invention The present invention has the effect that it is possible to construct a reliable and highly reliable high-density multilayer circuit board by low-temperature sintering and injecting metal into organic insulating dia holes.
第１図は従来技術を示す図、および第２図は本発明の一
実施例を示す図である。
第１図および第２図において、１・・・・・・絶縁基板
、２・・・・・・金属導体層、３・・・・・・有機絶縁
層、５・・・・・・金属導体層、１１・・・・・・セラ
ミック基板、１２・・・・・・第１導体層、１３・・・
・・・ポリイミド絶縁層、１４・・・・・・低温焼結金
（Ａｕ）導体、１５・・・・・・第２導体１Ｔｈ、ｔ。
、％ を図
／＜′
牛２区
５＋＋、：ｔ、１０
昭和 年 月 日
特許庁長官 殿
１、事件の表示 昭和５８年特 許 願第８２０８７号
２、発明の名称 高密度多層回路基板
３、補正をする者
事件との関係 出 願 人
東京都港区芝五Ｊ−１１３３計１号
／４２３） 日本電気株式会社
代表者 関本忠弘
４、代理人
５ 補正の対象
（１）明細書の特許請求の範囲の欄
（２）明細書の発明の詳細な説明の欄
（３）明細書の図面の簡単な説明の欄
６ 補正の内容
（１）別紙のとおり
（２）明細書の発明の詳細な説明の欄および明細書の図
面の簡単な説明の欄を下記のように訂正します。
記
１、第３貞第１０行目の記載「金属と、」を「金属もし
くは導電性有機ペースト、」と訂正します。
２、同頁第１１ｆ１目の記載「金属上に」を「金属もし
くは導電性有機ペースト上に」と訂正します。
３ 第４頁第４行目の記載「導体１４」を「導体もしく
は導電性有機ペースト１４」と訂正します。
４ 同頁第５行目の記載「導体１４」を「導体もしくは
導電性有機ペースト１４」と訂正します。
５、同頁第５行目の記載「のである。」を［のである。
さらに導電性有機ペースト１４は１ミクロンの金（Ａｕ
）粉体８５％ｔＦ＆比とポリイミド前駆体であるポリイ
ミド酸を１５係車量比で混合、４００°Ｃでキュアーし
導電性をもたせたものである。」と訂正します。
６、同頁第５行目の記載「導体１４」を「導体もしくは
導電性有機ペースト１４」と訂正します。
２ 第５頁第４行目の記載「体１４」を「体もしくは導
電性有機ペースト１４」と訂正し捷す。
８ 同頁第５行目の記載「金属を」を「金属もしくは導
電性有機ペーストを」と訂正し捷す。
９、第６頁第４行目の記載［・・・・・・（Ａｕ）導体
、」を「・・・・・・（Ａｕ）導体もしくは導屯性有機
ベースト、」と訂正します。
手続補正書（方式）
％式％
：
１、事件の表示 昭和５８年 付 許願第８２０８７号
２、発明の名称 高密度多層回路基板
３、補正をする者
事件との関係 出 願 人
東京都港区芝ｌＬ丁１−１３３番１号
（４２３） 日本電気株式会社
代表者 関本忠弘
４、代理人
〒１０８ 東京都港区芝五丁［１３７番８′；Ｊ−住友
三田ビル５、補正命令の日付
昭和５９年１０月９日（発送日）
６、補正の対象
昭和５９年８月１０日付差出しの手続補正臀（自発）
７、補ｉＥの内容
１）別紙のとおり手続補正書（差出書）を提出しのを削
除します。
代理人 弁理士 内 原 晋
手続補正書（自発）
昭和５９年 ８月１０日
特許庁長官 殿
１、事件の表示 昭和５８年 特 許 願第８２０８７
号２、発明の名称 高密度多層回路基板
３、補正をする者
事件との関係 出 願 人
東京都港区芝五丁目３３番１号
（４２３） 日本電気株式会社
代表右 関本忠弘
４、代理人
〒１０８ 東京都港区芝り丁１１３７？ｌ’ｆ８″ｌＥ
住友三ｆｆｌビル日本電気株式会社内
（６５９１＞ 弁理士 内 原 、會
電話 東京（０３）４５６”−３１１１（大代表）゛（
連絡先 口本電気株式会社持許部）
５、補正の対象
（１） 明細書の発明の詳細な説明の欄（２）明細書の
図面の簡単な説明の欄FIG. 1 is a diagram showing the prior art, and FIG. 2 is a diagram showing an embodiment of the present invention. 1 and 2, 1...Insulating substrate, 2...Metal conductor layer, 3...Organic insulating layer, 5...Metal conductor Layer, 11... Ceramic substrate, 12... First conductor layer, 13...
... Polyimide insulating layer, 14 ... Low temperature sintered gold (Au) conductor, 15 ... Second conductor 1Th, t. Figure , %/<' Ushi 2 Ward 5++, :t, 10 Showa Year Month Date Director General of the Patent Office 1, Indication of the case 1982 Patent Application No. 82087 2, Title of the invention High-density multilayer circuit board 3, Relationship with the case of the person making the amendment Applicant: Shibago J-1133, Minato-ku, Tokyo, Total No. 1/423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent 5 Target of amendment (1) Patent claim in the specification (2) Detailed explanation of the invention in the specification (3) Brief explanation of the drawings in the specification The description column and the brief description column of drawings in the specification will be corrected as follows. In the 10th line of Note 1 and 3, the statement ``metal'' has been corrected to ``metal or conductive organic paste.'' 2. The statement "on metal" in item 11f1 of the same page is corrected to "on metal or conductive organic paste." 3. The description "Conductor 14" in the 4th line of page 4 will be corrected to "Conductor or conductive organic paste 14." 4. The entry "Conductor 14" in the fifth line of the same page will be corrected to "Conductor or conductive organic paste 14." 5. In the fifth line of the same page, the statement ``nono deru.'' is changed to [nono deru.'' Furthermore, the conductive organic paste 14 is made of 1 micron gold (Au).
) Powder with a tF& ratio of 85% and polyimide acid, which is a polyimide precursor, are mixed at a ratio of 15% and cured at 400°C to make it conductive. ” I am corrected. 6. The description "Conductor 14" on the 5th line of the same page will be corrected to "Conductor or conductive organic paste 14." 2. The description "Body 14" on the 4th line of page 5 is corrected to "Body or conductive organic paste 14". 8 The statement ``metal'' in line 5 of the same page is corrected to ``metal or conductive organic paste.'' 9. In the fourth line of page 6, the statement [...(Au) conductor] has been corrected to "...(Au) conductor or conductive organic base." Procedural amendment (method) % formula %: 1. Indication of the case: Patent Application No. 82087, dated 1982. 2. Title of the invention: High-density multilayer circuit board 3. Person making the amendment. Relationship with the case. Applicant: Minato-ku, Tokyo Shiba L-chome 1-133-1 (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent Address: 108 Shiba 5-chome, Minato-ku, Tokyo [137-8'; J-Sumitomo Sanda Building 5, Date of amendment order October 9, 1980 (shipment date) 6. Subject of amendment: Amendment of procedure submitted dated August 10, 1980 (voluntary) 7. Contents of supplementary iE 1) Procedural amendment (letter of submission) as attached. Submit and delete. Agent Susumu Uchihara, patent attorney Procedural amendment (spontaneous) August 10, 1980 Commissioner of the Japan Patent Office 1, Indication of case 1982 Patent Application No. 82087
No. 2, Title of the invention High-density multilayer circuit board 3, Relationship to the amended person's case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Right: Tadahiro Sekimoto 4, Agent 1137 Shibaricho, Minato-ku, Tokyo 108? l'f8″lE
Sumitomo 3FFL Building, NEC Corporation (6591> Patent Attorney Uchihara, Company Telephone: Tokyo (03) 456”-3111 (Main Representative)゛(
(Contact information: Kuchimoto Electric Co., Ltd., Licensing Department) 5. Subject of amendment (1) Column for detailed explanation of the invention in the specification (2) Column for brief explanation of drawings in the specification
Claims (1)
導体層上に上下金属導体層接続穴を有する有機絶縁層と
、 前記上下金属導体層接続穴にうめ込まれた低温焼結金属
と、 前記有機絶縁上および低温焼結金属上に形成された第２
の金属体層とからなる層を複数積み（ｋねたことを特徴
とする高密度多層回路基板０[Scope of Claims] An insulating substrate, a first metal conductor layer formed on the insulating substrate, an organic insulating layer having upper and lower metal conductor layer connection holes on the metal conductor layer, and the upper and lower metal conductor layer connections. a low-temperature sintered metal embedded in the hole; and a second layer formed on the organic insulation and the low-temperature sintered metal.
A high-density multilayer circuit board characterized by stacking a plurality of layers consisting of metal body layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8208783A JPS60132392A (en) | 1983-05-11 | 1983-05-11 | High density multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8208783A JPS60132392A (en) | 1983-05-11 | 1983-05-11 | High density multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60132392A true JPS60132392A (en) | 1985-07-15 |
| JPH025022B2 JPH025022B2 (en) | 1990-01-31 |
Family
ID=13764656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8208783A Granted JPS60132392A (en) | 1983-05-11 | 1983-05-11 | High density multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132392A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
-
1983
- 1983-05-11 JP JP8208783A patent/JPS60132392A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025022B2 (en) | 1990-01-31 |
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