JPS62196811A - Ceramic substrate with built-in capacitor - Google Patents
Ceramic substrate with built-in capacitorInfo
- Publication number
- JPS62196811A JPS62196811A JP61036531A JP3653186A JPS62196811A JP S62196811 A JPS62196811 A JP S62196811A JP 61036531 A JP61036531 A JP 61036531A JP 3653186 A JP3653186 A JP 3653186A JP S62196811 A JPS62196811 A JP S62196811A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- ceramic substrate
- built
- ceramic
- ceramic body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims description 130
- 239000003990 capacitor Substances 0.000 title claims description 82
- 239000000758 substrate Substances 0.000 title claims description 78
- 239000004020 conductor Substances 0.000 claims description 37
- 238000010304 firing Methods 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000007650 screen-printing Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- -1 ffi Chemical compound 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005065 mining Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 150000004703 alkoxides Chemical class 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、積層コンデンサ内蔵型の多層セラミック基板
に関する。更に、詳しくは、スルーホール導体を含む端
子構造を有する積層コンデンサ内蔵型多層セラミック基
板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic substrate with a built-in multilayer capacitor. More specifically, the present invention relates to a multilayer ceramic substrate with a built-in multilayer capacitor having a terminal structure including through-hole conductors.
[従来の技術]
最近、電子機器の小型化に伴い、配線基板の小型化高密
度化が進んでいる。電子部品の中で重要な要素を占める
コンデンサ部品においても、比較的容量の小さいセラミ
ックコンデンサは、ディスク型から積層することにより
容量値を太きくシ。[Background Art] Recently, as electronic devices have become smaller, wiring boards have become smaller and more dense. Even in capacitor parts, which are an important element in electronic components, ceramic capacitors, which have relatively small capacitance, can be laminated to increase the capacitance value by starting from the disk type.
更に、1つのコンデンサチップの中に複数個の容量値を
有するコンデンサブロックへと積層化部品に進んでいる
。然し乍ら、前記のコンデンサブロックといえども、基
板上に搭載する必要があり、集積密度としては限界があ
る。そこで最近セラミ7り基板内部にコンデンサを内蔵
したコンデンサ内蔵型セラミック基板が開発きれつつあ
る。Furthermore, stacked components are progressing to capacitor blocks having multiple capacitance values in one capacitor chip. However, even the above-mentioned capacitor block needs to be mounted on a substrate, and there is a limit to its integration density. Therefore, recently, a capacitor-embedded ceramic substrate, in which a capacitor is built inside the ceramic substrate, is being developed.
しかし、従来のコンデンサ内蔵型セラミック基板では、
コンデンサを構成するセラミックは比較的に高い誘電率
を有すること、容量の興なるコンデンサを形成する場合
、電極の面積の大小により異なる容量にするため番こ、
大きく異なる容量値を持つコンデンサを同一基板内に形
成することは非常に困難であることなどの問題が多い。However, with conventional ceramic substrates with built-in capacitors,
The ceramic that makes up the capacitor has a relatively high dielectric constant, and when forming a capacitor with a high capacitance, it is important to have a different capacitance depending on the size of the electrode area.
There are many problems, such as the fact that it is extremely difficult to form capacitors with significantly different capacitance values on the same substrate.
最近では1以上の2つの問題を解決するため、誘電率の
異なるセラミックスを積層し同時に焼成することが考え
られているが、互いに収縮率を合致させる必要があり、
非常に困難である。Recently, in order to solve one or more of the two problems, it has been considered to stack ceramics with different dielectric constants and fire them at the same time, but it is necessary to match the shrinkage rates of each other.
Very difficult.
[発明が解決しようとする問題点]
本発明の目的は2以上の従来のコンデンサ内蔵型セラミ
ック基板の欠点を解消することである。[Problems to be Solved by the Invention] An object of the present invention is to eliminate two or more drawbacks of conventional ceramic substrates with built-in capacitors.
即ち9本発明は1個別に焼結した少なくとも1つの積層
コンデンサを内蔵する少なくとも1つの積層セラミ/り
体と、薄く、高絶縁性で低誘電率の少なくとも1つのセ
ラミック基板を相互に部分的に接合した構成で、異なる
収縮率のセラミック基板を組合わることのでき、容量値
の著しく異なる積層コンデンサを同一基板内に形成でき
るコンデンサ内蔵型セラミック基板を提供することを目
的・ とする。That is, the present invention is characterized in that: (1) at least one laminated ceramic body containing at least one individually sintered laminated capacitor and at least one thin, highly insulating, and low dielectric constant ceramic substrate are partially mutually connected; It is an object of the present invention to provide a capacitor-embedded ceramic substrate in which ceramic substrates having different shrinkage rates can be combined in a bonded configuration, and multilayer capacitors having significantly different capacitance values can be formed within the same substrate.
[問題点を解決するための手段コ
本発明は、内部導体層と誘電体重を積層して構成きれた
少なくとも1つのコンデンサ機能を有する少なくとも1
つの積層セラミック体と高絶縁性の少なくとも1つの薄
いセラミック基板とを接合した積層コンデンサ内蔵型セ
ラミック基板である。前記の積層セラミック体は1貫通
孔或いは最下部導体層まで貫通する孔を有し、その孔に
充填した導体ペーストにより、その内部電極と端子電極
を導通させ、積層セラミック体上面にコンデンサ端子を
設け、そして任意の位置にスルーホールを設けたセラミ
ンク基板の上面と導通しであることによりコンデンサ両
端子を最上面の任意の位置に設けることができる。前記
の接合は1個々の積層セラミック体と薄膜セラミック基
板を個別に焼成した後に、その積層セラミック体及び薄
膜セラミック基板の表面の一部において、ハンダ、ガラ
ス、厚膜導体ペーストのうち少なくとも1つを用いて行
なうことができる。そして、他の表面部分は積層セラミ
/り体或いは薄膜セラミ/り基板の相互間に空気!5(
空隙)が存在するようにできる。[Means for Solving the Problems] The present invention provides at least one capacitor having at least one capacitor function, which is constructed by laminating an inner conductor layer and a dielectric weight.
This ceramic substrate has a built-in multilayer capacitor, in which two multilayer ceramic bodies and at least one highly insulating thin ceramic substrate are bonded together. The laminated ceramic body has one through hole or a hole that penetrates to the lowest conductor layer, the internal electrode and the terminal electrode are electrically connected to each other by a conductive paste filled in the hole, and a capacitor terminal is provided on the upper surface of the laminated ceramic body. Since the capacitor is electrically connected to the upper surface of the ceramic substrate having through holes provided at arbitrary positions, both terminals of the capacitor can be provided at arbitrary positions on the uppermost surface. The above-mentioned bonding is carried out by firing at least one of solder, glass, and thick-film conductor paste on a portion of the surface of the laminated ceramic body and thin-film ceramic substrate after individually firing the laminated ceramic body and the thin-film ceramic substrate. It can be done using The other surface parts are made of laminated ceramic/resistance or thin film ceramic/resistance substrates with air between them! 5(
voids) can be made to exist.
本発明の′gtWIコンデンサ内蔵型セラミック基板は
1例えば、第8IyJの如き構造であり、積層コンデン
サを内蔵する積層セラミック体21.22と薄いセラミ
ンク基板9よりなり、その間に空隙部10を設け、所定
の個所に接合部を設け、互いに接合した構造のものであ
る。The 'gtWI capacitor built-in ceramic substrate 1 of the present invention has a structure such as, for example, No. 8 IyJ, and is composed of a multilayer ceramic body 21, 22 containing a multilayer capacitor and a thin ceramic substrate 9, with a gap 10 provided therebetween, and a predetermined It has a structure in which joints are provided at the locations and they are joined to each other.
即ち、積層コンデンサを内蔵するセラミック体21と2
2を構成するセラミック誘電体は、別々に製造、即ち、
焼成きれるためにその間に収縮率等が著しく異なっても
1問題が生じない。That is, ceramic bodies 21 and 2 containing multilayer capacitors
The ceramic dielectrics constituting 2 are manufactured separately, i.e.
Since it can be fired completely, no problem occurs even if the shrinkage rate etc. differ significantly during the firing process.
これは1本発明を構成する積層セラミック体。This is a laminated ceramic body that constitutes one of the present inventions.
セラミック基板の相互の間を間隔をとって接合するため
に、互いの収縮の差、膨張率の差などの影響がなくなる
からである。即ち、積層セラミック体、セラミック基板
の表面の一部のみで、ハンダ、ガラス、厚膜導電ペース
トで接合部を設は接合するものである。実際の製造法と
しては、積層セラミック体、セラミック基板の表面の接
合すべき所定の箇所に上記の接合剤のうち少なくとも1
つを、スクリーン印刷技法等により、置き、バンブ状の
ものを作り1次に、それらを組立てて(例えば、第7図
の如り)、リブロー炉などで比較的低温で焼成する。そ
れにより、積層セラミック体、セラミック基板は、互い
に、そのバンブ状のものが溶けなどして接合し、相互に
空隙をとって、即ち、空気層があるように結合し1本発
明の構造体ができる。This is because the ceramic substrates are bonded with a distance between them, so that the effects of differences in shrinkage and expansion coefficients between the ceramic substrates are eliminated. That is, only a portion of the surface of the laminated ceramic body or ceramic substrate is provided with a joint portion using solder, glass, or thick film conductive paste. In the actual manufacturing method, at least one of the above bonding agents is applied to the predetermined locations on the surfaces of the laminated ceramic body and ceramic substrate to be bonded.
The two pieces are placed using a screen printing technique or the like to form a bump-like product, which is then assembled (for example, as shown in FIG. 7) and fired at a relatively low temperature in a rib-blow oven or the like. As a result, the laminated ceramic body and the ceramic substrate are bonded to each other by melting their bump-like parts, and are bonded to each other with a gap, that is, an air layer, to form a structure of the present invention. can.
即ち1本発明の積層コンデンサ内蔵型セラミ・νり基板
では、各積層コンデンサを内蔵したセラミック体は、別
個に焼成9作成されたものである。従って、各積層コン
デンサ内蔵セラミyり体は、全く別の物性9例えば、著
しく異なる収縮率、誘電率を有するセラミック誘電体材
料であってもよく、それらを本発明に従い接合構成する
ことができる。That is, in the multilayer capacitor-embedded ceramic v-shaped substrate of the present invention, the ceramic body containing each multilayer capacitor is separately produced by firing. Therefore, each ceramic body with a built-in multilayer capacitor may be made of ceramic dielectric materials having completely different physical properties 9, for example, significantly different shrinkage rates and dielectric constants, and these can be bonded according to the present invention.
更に1本発明の積層コンデンサ内蔵型セラミック基板は
、その上面に所望の回路パターンを持つセラミック基板
を備え、内蔵した積層コンデンサとの導通が簡単にでき
る構造である。即ち、第8図の本発明の構造において、
薄いセラミック基板9の表面に導体及び抵抗パターン1
6を図示のごとく、導電性ペーストなどで形成し、所望
の回路を有する混成集積回路セラミック基板が得られる
。Furthermore, the ceramic substrate with a built-in multilayer capacitor of the present invention has a structure that includes a ceramic substrate having a desired circuit pattern on its upper surface, and allows easy conduction with the built-in multilayer capacitor. That is, in the structure of the present invention shown in FIG.
Conductor and resistance pattern 1 on the surface of thin ceramic substrate 9
6 is formed of a conductive paste or the like as shown in the figure, and a hybrid integrated circuit ceramic substrate having a desired circuit is obtained.
従って9本発明の積層コンデンサ内蔵型セラミック基板
は、全体の厚みを薄くでき、複数の積1コンデンサの間
の導通も簡単にできる。また。Therefore, the ceramic substrate with a built-in multilayer capacitor according to the present invention can have a small overall thickness, and can easily conduct electrical connections between a plurality of multilayer capacitors. Also.
内蔵コンデンサを導通する孔を任意の個所に設定でき1
回路パターン設計にも自由度が大きい。The hole that conducts the built-in capacitor can be set at any location.1
There is also a large degree of freedom in circuit pattern design.
導体パターン暦及び導通導体形成に利用きれる材料とし
ては、金、ffi、銅、白金、パラジウム。Materials that can be used to form conductor patterns and conductors include gold, ffi, copper, platinum, and palladium.
モリブデン、タングステンなど導電性金属であり、その
ペーストをスクリーン印刷法などによりセラミック基板
上面の表面上に印刷し、導体層或いはスルーホール導通
導体とすることができる。It is a conductive metal such as molybdenum or tungsten, and its paste can be printed on the top surface of a ceramic substrate by screen printing or the like to form a conductor layer or through-hole conductor.
本発明の接合部分形成に用いられる材料としては、ハン
ダ、ガラス、厚膜導体ペーストなどの比較的低温で溶融
でき、接合を行なうことができるものである。接合のた
めの接合部形成の焼成のときに、内蔵コンデンサを含む
積層セラミック体。Materials used for forming the joint portion of the present invention include solder, glass, thick film conductor paste, and the like, which can be melted at a relatively low temperature and can be joined. A laminated ceramic body containing a built-in capacitor during firing to form a joint for bonding.
回路パターンを含む薄膜セラミック基板に障害を与えな
いためになるべく低温焼成がよく、好適には、900℃
以下の焼成温度で接合できる材料を使用する。接合のた
めの焼成温度は好適には500℃〜600℃程度である
。ガラスによる接合は、電導性の接合部が不要の個所に
用いる。In order not to damage the thin-film ceramic substrate containing the circuit pattern, it is best to fire at a temperature as low as possible, preferably at 900°C.
Use materials that can be bonded at the following firing temperatures. The firing temperature for bonding is preferably about 500°C to 600°C. Glass bonding is used in locations where electrically conductive bonding parts are not required.
本発明に用いられるセラミック誘電体材料は。The ceramic dielectric material used in the present invention is:
アルミナなどの積層コンデンサ内蔵型セラミック基板に
通常用いられる材料でよいが、誘電率を適宜選択するこ
とにより、所望の積層コンデンサの容量値にすることが
できる。即ち、誘電率の低いセラミック誘電体から誘電
率の高いセラミック誘電体まで自由に利用1組合わせて
、所望の回路特性にできる。従って、セラミック基板、
積層コンデンサをはさむ材料としては、他に、誘電率の
低い基板材料、 Bao−riot等の高い誘電率のも
の、チタニア(TtO*)系の基板材料等を利用できる
。A material commonly used for ceramic substrates with built-in multilayer capacitors, such as alumina, may be used, but by appropriately selecting the dielectric constant, a desired capacitance value of the multilayer capacitor can be obtained. That is, desired circuit characteristics can be obtained by freely using a combination of ceramic dielectric materials having a low dielectric constant and ceramic dielectric materials having a high dielectric constant. Therefore, the ceramic substrate,
Other materials that can be used to sandwich the multilayer capacitor include substrate materials with a low dielectric constant, materials with a high dielectric constant such as Bao-riot, and titania (TtO*)-based substrate materials.
本発明により得られるコンデンサ内蔵型セラミック基板
は1例えば、電子機器等に使用される混成集積回路用の
多層配線基板などに使用され得る。例えば、第1図の如
き回路の製作組立てに用いられる0図示の4つのコンデ
ンサC1〜C4の中でC1及びC1は、比較的に低い容
量値であり、C+及びC4は、比較的に高い容量値を持
つ、この占うに著しく異なる容量値を持つコンデンサを
同一の基板中に内蔵するセラミック基板の製作に本発明
は用いられる。The capacitor built-in ceramic substrate obtained by the present invention can be used, for example, as a multilayer wiring board for hybrid integrated circuits used in electronic devices and the like. For example, among the four capacitors C1 to C4 shown in FIG. 1 used for manufacturing and assembling the circuit shown in FIG. 1, C1 and C1 have relatively low capacitance values, and C+ and C4 have relatively high capacitance values. The present invention is used to fabricate a ceramic substrate in which capacitors having significantly different capacitance values are built into the same substrate.
次に1本発明の積層コンデンサ内蔵型セラミック基板に
ついて説明するが1本発明は1次の実施例のものに限定
されるものではない。Next, a ceramic substrate with a built-in multilayer capacitor according to the present invention will be described, but the present invention is not limited to the first embodiment.
[実施例コ
図により本発明の積層コンデンサ内蔵型セラミック基板
の構造と組立て手順を説明する。第2〜3図で容量値の
低いコンデンサ内蔵型セラミック体の組立てを示し、第
4〜5図で容量値の高いコンデンサ内蔵型セラミック体
の組立てを示し。[Example] The structure and assembly procedure of a ceramic substrate with a built-in multilayer capacitor according to the present invention will be explained with reference to the drawings. 2 and 3 show the assembly of a ceramic body with a built-in capacitor having a low capacitance value, and FIGS. 4 and 5 show the assembly of a ceramic body with a built-in capacitor having a high capacitance value.
第7〜8図に本発明による以上の容量値の著しく異なる
積層コンデンサの構成及び組立てを示す。7 and 8 show the structure and assembly of multilayer capacitors having significantly different capacitance values according to the present invention.
即ち、第2図養、比較的に低い誘電率を持つ誘電体1と
、互いに対向する電極2,3を内部に積層し、焼成した
コンデンサ内蔵型セラミック体を示す平面図及び断面図
である。That is, the second image is a plan view and a sectional view showing a ceramic body with a built-in capacitor in which a dielectric 1 having a relatively low dielectric constant and electrodes 2 and 3 facing each other are laminated inside and fired.
第3図は、第2図の積層コンデンサ内蔵型セラミック体
に貫通孔或いは最下部導体まで孔14を設け、積層コン
デンサの対向する内部電極2.3と上面端子4との間に
貫通孔導体14で導通を取った後、積層コンデンサ内蔵
型セラミック体の上面に導体パターン4を印刷し設置し
たものである。この貫通孔導体14と導体パターン(:
+ンデンサ端子)4の形成は、第2図の積層コンデンサ
内蔵型セラミック体の表面にスクリーン印刷技法などで
銀パラジウムペーストなどの電導性ペーストを印刷形成
することにより、孔に導体を詰め。FIG. 3 shows a through hole or a hole 14 provided in the multilayer capacitor built-in ceramic body shown in FIG. After establishing continuity, a conductor pattern 4 is printed and installed on the top surface of the ceramic body with a built-in multilayer capacitor. This through-hole conductor 14 and the conductor pattern (:
The conductor terminal (4) is formed by printing a conductive paste such as silver-palladium paste on the surface of the ceramic body with a built-in multilayer capacitor shown in FIG. 2 using a screen printing technique, thereby filling the holes with a conductor.
一定ノパターンの端子をセラミック体の表面に形成する
ことができる。A pattern of terminals can be formed on the surface of the ceramic body.
第4図は、比較的に高い誘電率をもつ誘電体5により、
互いに対向するコンデンサ電極6.7を互いに積層し、
焼成して製造した積層コンデンサ内蔵型セラミック体を
示す平面図と断面図である。FIG. 4 shows that due to the dielectric material 5 having a relatively high dielectric constant,
mutually opposing capacitor electrodes 6.7 are stacked on each other;
FIG. 2 is a plan view and a cross-sectional view showing a ceramic body with a built-in multilayer capacitor produced by firing.
第5図は、第4図の容量値の比較的高い積層コンデンサ
を内蔵するセラミック体に貫通孔或いは最下部導体まで
孔15を設け、積層コンデンサの対向する内部電極6,
7と上面との間に導通を取った後、積層コンデンサ内蔵
型セラミック体の上面に導体パターン8を印刷し設置し
たものである。この孔の中に導通導体を設けること、及
びセラミック体上面への導体パターンの形成することは
、第3図の場合と同じく、導電性ペーストを旅すことに
より同様に作成できる。FIG. 5 shows a ceramic body containing a multilayer capacitor with a relatively high capacitance value as shown in FIG.
7 and the top surface, a conductor pattern 8 is printed and installed on the top surface of the ceramic body with a built-in multilayer capacitor. Providing a conductor in this hole and forming a conductor pattern on the top surface of the ceramic body can be similarly made by passing a conductive paste as in the case of FIG.
第6図は、厚さ150μm以下の高絶縁性で低誘電率の
セラミック基板9にスルーホール11を設けたものであ
る。このセラミック基板9は、金属アルコキシドを出発
原料として、ゾル−ゲル法により製造きれるアルミナ基
板が好適であり、実際的には、現在30/Zmの厚膜の
セラミック基板も実現きれている。In FIG. 6, through holes 11 are provided in a highly insulating and low dielectric constant ceramic substrate 9 having a thickness of 150 μm or less. This ceramic substrate 9 is preferably an alumina substrate that can be manufactured by a sol-gel method using metal alkoxide as a starting material, and in practice, ceramic substrates with a thickness of 30/Zm have now been realized.
第7図は、第3図の積層コンデンサ内蔵型セラミック体
21と第5図の積層コンデンサ内蔵型セラミック体22
と第6図のスルーホールを有する薄いセラミック基板を
、ハンダ、ガラス、厚膜導体ペーストの少なくとも1つ
を用いて1間隔を取って空隙層(空気層)10があるよ
うに、各表面の一部でのみ接合するように組立てたもの
である。この接合は2例えば1以上のような接合ペース
トをスクリーン印刷技法による厚膜形成技術で所定位置
に接合凸部を形成し、そのようなセラミンク基板を例え
ば9図示のごとく組立てて炉の中に入れ、焼成し、接合
ペーストを溶かすなどにより1行なうことができる。FIG. 7 shows a ceramic body 21 with a built-in multilayer capacitor shown in FIG. 3 and a ceramic body 22 with a built-in multilayer capacitor shown in FIG.
A thin ceramic substrate having through-holes as shown in FIG. It is assembled so that it is joined only at the parts. This bonding is performed by forming a bonding convex portion at a predetermined position using a thick film forming technique using a screen printing technique using a bonding paste such as 2 or more, and then assembling such a ceramic substrate as shown in FIG. 9 and placing it in a furnace. , firing, melting the bonding paste, etc.
第8図は、第7図の積層コンデンサ内蔵型セラミック基
板の最上面に導体、抵抗パターン16を印刷形成し、更
に装置チップ、例えば、トランジスタ18を搭載したも
のである1回路形成を完成させたものであり、第1図の
等価回路のものが完成された。FIG. 8 shows a completed circuit in which a conductor and resistance pattern 16 is printed on the top surface of the ceramic substrate with a built-in multilayer capacitor shown in FIG. 7, and a device chip, for example, a transistor 18 is mounted. The equivalent circuit shown in Figure 1 was completed.
[発明の効果]
本発明の積層コンデンサ内蔵型セラミック基板は、上記
の構造をとるにより、第1に、2つ以上の誘電率の異な
る誘電体を同一積層コンデンサ内蔵型セラミンク基板に
使用することが可能になったこと、第2に、従って、容
量値の大きく異なる2種以上の積層コンデンサを同一コ
ンデンサ内蔵型セラミック基板内に形成できるようにな
ったこと、第3に、内蔵の積層コンデンサの電極と上面
導体部とのカップリングや複数の積層体内部の電極間の
カップリングを小さく押さえることができること、第4
に、クロスオーバ一部を容易に設けることができ、設計
の自由度を大きくできること、第5に、積層コンデンサ
内蔵型セラミック基板の上面に設けられるコンデンサ端
子は接合面に導体パターンを印刷することにより、その
位置が比較的自由に設計できること、第6に、積層コン
デンサを形成する誘電体に非常に高い誘電率のものも利
用できること。[Effects of the Invention] The ceramic substrate with a built-in multilayer capacitor of the present invention has the above-described structure, so that, firstly, two or more dielectrics having different permittivity can be used in the same ceramic substrate with a built-in multilayer capacitor. Second, it has become possible to form two or more types of multilayer capacitors with significantly different capacitance values on the same ceramic substrate with a built-in capacitor. Third, the electrodes of the built-in multilayer capacitor can now be formed on the same ceramic substrate. Fourth, the coupling between the top surface conductor and the electrodes inside the plurality of laminates can be kept small.
Second, a part of the crossover can be easily installed, increasing the degree of freedom in design.Fifth, the capacitor terminals provided on the top surface of the ceramic substrate with built-in multilayer capacitors can be printed with a conductor pattern on the bonding surface. Sixth, the position can be designed relatively freely; and sixth, the dielectric material forming the multilayer capacitor can have a very high dielectric constant.
第1図は1本発明の積層コンデンサ内蔵型セラミック基
板に組立てられる回路の1例を示す。
第2図は1本発明に用いられる積着コンデンサ内蔵型セ
ラミック体の1例を示す平面図と断面図である。
第3図は、第2図の積層セラミック体に導通のための導
体孔と導体パターンを設けたものである。
第4図は2本発明に用いられる高い誘電率をもつセラミ
ックで積層された積層コンデシナ内蔵型セラミック体の
1例を示す平面図と断面図である。
第5図は、第4図の積層セラミック体に導通りための孔
と導体パターンを設けたものである。
第6図は、スルーホールを設けた薄いセラミック基板の
平面図と断面図である。
第7図は、第3図の積層セラミック体と第5図の積層セ
ラミyり体と第6図のセラミック基板を組立てた本発明
の積層コンデンサ内蔵型セラミ/り基板の構造を示す平
面図と断面図である。
第8図は、第7図の積層コンデンサ内蔵型セラミック基
板に導通のための導通導体孔と導体(回路)パターンを
設けたものである。
[主要部分の符号の説明〕
110.低い誘電率のセラミック体
2.3,6,7.、、、積層コンデンサ電極(導体層)
4.8.、、、、、導体パターン(端子)513.高い
誘電率のセラミック体
90..薄いセラミック基板
10、、、空間層(空気層)
11、、、スルーホール
14.15.17.、、貫通導通孔
16、、、最上面導体(抵抗)パターン1B、、、トラ
ンジスタ載置位置
特許出願人 三菱鉱業セメント株式会社代理人 弁
理士 倉 持 裕
特許庁長官 宇 賀 道 部 殿
1.9s件の表示 昭和61年特許願第036531号
2、発明の名称
コンデンサ内蔵型セラミック基板
3、補正をする者 事件との関係 出願人住所 東
京都千代田区丸の内−丁目5番1号三菱鉱業セメント株
式会社
代表者小林久明
4、代理人
〒102東京都千代田区一番町11の15、補正により
増加する発明の数 07、補正の内容
(1)別紙のとおり[特許請求の範囲コの項を訂正する
。
(2)明細書の第4頁第9行目の1組合わる」庖[組み
合わせるコに訂正する。
(3)明細書の第5頁第8行目、同頁第9〜10行目及
び同頁第13行目の「薄膜セラミ・ツク、を[薄いセラ
ミツクコに訂正する。
特許請求の範囲
[(1)内部導体層と誘電体層を積層して構成された少
なくとも1つのコンデンサ機能を有する少なくとも1つ
の積層セラミック体と高絶縁性の少なくとも1つの薄い
セラミック基板とを接合した構造を有することを特徴と
する積層コンデンサ内蔵型セラミック基板。
(2)前記の積層セラミック体は1貫通孔或いは最下部
導体層まで貫通する孔を有し、その孔に充填した導体ペ
ーストにより、その積石セラミック体上面にコンデンサ
端子を設け、そして任意の位置のセラミック基板中に設
けたスルーホール導体によりセラミック基板上面の端子
と導通することによりコンデンサ両端子を最上面の任意
の位置に設けることを特徴とする特許請求の範囲第1項
記載のコンデンサ内蔵型セラミック基板。
(3)前記の接合は2個々の積石セラミック体とセラミ
7り基板を個別に焼成した後に、その積層セラミック体
及び b’+’yiヱ’)基板の表面の所定個所に、ハ
ンダ、ガラス、厚膜導体ペーストのうち少な(とも1つ
を置いて2行ない、他の表面部分には積層セラミック体
、に二二二y’)基板の相互間に空気層があることを特
徴とする特許請求の範囲第1項記載の積層コンデンサ内
蔵型セラミック基板、〕FIG. 1 shows an example of a circuit assembled on a ceramic substrate with a built-in multilayer capacitor according to the present invention. FIG. 2 is a plan view and a sectional view showing an example of a ceramic body with a built-in stacking capacitor used in the present invention. FIG. 3 shows the laminated ceramic body of FIG. 2 provided with conductor holes and conductor patterns for electrical continuity. FIG. 4 is a plan view and a sectional view showing an example of a ceramic body with a built-in laminated condenser made of two ceramics having a high dielectric constant used in the present invention. FIG. 5 shows the laminated ceramic body of FIG. 4 provided with holes and conductive patterns for conduction. FIG. 6 is a plan view and a cross-sectional view of a thin ceramic substrate provided with through holes. FIG. 7 is a plan view showing the structure of a multilayer capacitor built-in ceramic/substrate of the present invention in which the multilayer ceramic body of FIG. 3, the multilayer ceramic body of FIG. 5, and the ceramic substrate of FIG. 6 are assembled; FIG. FIG. 8 shows a ceramic substrate with a built-in multilayer capacitor shown in FIG. 7 provided with conductor holes and conductor (circuit) patterns for electrical connection. [Explanation of symbols of main parts] 110. Ceramic body with low dielectric constant 2.3, 6, 7. ,,, Multilayer capacitor electrode (conductor layer) 4.8. , , , Conductor pattern (terminal) 513. High dielectric constant ceramic body 90. .. Thin ceramic substrate 10,...Space layer (air layer) 11,...Through holes 14.15.17. ,,Through conduction hole 16, ,Top conductor (resistance) pattern 1B, ,Transistor mounting position Patent applicant Mitsubishi Mining Cement Co., Ltd. Agent Patent attorney Hiroshi Kuramochi Commissioner of the Patent Office Michibe Uga 1.9s Display of the matter Patent Application No. 036531 of 1985 2, Name of the invention Ceramic substrate with built-in capacitor 3, Person making the amendment Relationship to the case Applicant address 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo Mitsubishi Mining Cement Co., Ltd. Representative Hisaaki Kobayashi 4, Agent Address: 11-15, Ichiban-cho, Chiyoda-ku, Tokyo 102 Number of inventions increased by the amendment 07 Contents of the amendment (1) As shown in the appendix [Claims of claims are to be corrected] . (2) The 9th line on page 4 of the specification is corrected to ``combined''. (3) "Thin film ceramics" in page 5, line 8, lines 9 to 10, and line 13 of page 5 of the specification is corrected to "thin ceramic." Scope of Claims [( 1) It has a structure in which at least one laminated ceramic body having at least one capacitor function, which is constructed by laminating an internal conductor layer and a dielectric layer, and at least one thin ceramic substrate with high insulation are joined. A ceramic substrate with a built-in multilayer capacitor. (2) The multilayer ceramic body has one through hole or a hole that penetrates to the lowest conductor layer, and the conductor paste filled in the hole allows the upper surface of the laminated ceramic body to be A patent claim characterized in that a capacitor terminal is provided, and both terminals of the capacitor are provided at an arbitrary position on the uppermost surface by connecting the capacitor terminal with a terminal on the upper surface of the ceramic substrate through a through-hole conductor provided in the ceramic substrate at an arbitrary position. A ceramic substrate with a built-in capacitor according to scope 1. (3) The above bonding is performed by firing the two individual laminated ceramic bodies and the ceramic substrate separately, and then bonding the laminated ceramic body and b'+'yiヱ' ) Apply a small amount of solder, glass, or thick film conductor paste to a predetermined location on the surface of the board (in two rows, placing one of them in two rows, and place a laminated ceramic body on the other surface area, and apply 222y') to each other on the board. A ceramic substrate with a built-in multilayer capacitor according to claim 1, characterized in that there is an air space therebetween.]
Claims (3)
くとも1つのコンデンサ機能を有する少なくとも1つの
積層セラミック体と高絶縁性の少なくとも1つの薄いセ
ラミック基板とを接合した構造を有することを特徴とす
る積層コンデンサ内蔵型セラミック基板。(1) It has a structure in which at least one laminated ceramic body having at least one capacitor function, which is constructed by laminating an internal conductor layer and a dielectric layer, and at least one thin ceramic substrate with high insulation properties are bonded. Features a ceramic substrate with a built-in multilayer capacitor.
導体層まで貫通する孔を有し、その孔に充填した導体ペ
ーストにより、その積層セラミック体上面にコンデンサ
端子を設け、そして任意の位置のセラミック基板中に設
けたスルーホール導体によりセラミック基板上面の端子
と導通することによりコンデンサ両端子を最上面の任意
の位置に設けることを特徴とする特許請求の範囲第1項
記載のコンデンサ内蔵型セラミック基板。(2) The laminated ceramic body has a through hole or a hole that penetrates to the lowest conductor layer, and a capacitor terminal is provided on the upper surface of the laminated ceramic body using a conductive paste filled in the hole, and a capacitor terminal is provided at an arbitrary position. The capacitor built-in ceramic according to claim 1, characterized in that both terminals of the capacitor are provided at arbitrary positions on the uppermost surface by conducting with the terminals on the upper surface of the ceramic substrate through a through-hole conductor provided in the ceramic substrate. substrate.
ック基板を個別に焼成した後に、その積層セラミック体
及び薄膜セラミック基板の表面の所定個所に、ハンダ、
ガラス、厚膜導体ペーストのうち少なくとも1つを置い
て、行ない、他の表面部分には積層セラミック体、薄膜
セラミック基板の相互間に空気層があることを特徴とす
る特許請求の範囲第1項記載の積層コンデンサ内蔵型セ
ラミック基板。(3) The above-mentioned bonding is performed by individually firing the laminated ceramic body and the ceramic substrate, and then applying solder or the like to predetermined locations on the surfaces of the laminated ceramic body and the thin-film ceramic substrate.
Claim 1, characterized in that at least one of glass and thick-film conductor paste is placed thereon, and there is an air layer between the laminated ceramic body and the thin-film ceramic substrate on the other surface portions. Ceramic substrate with built-in multilayer capacitor as described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61036531A JPH0754778B2 (en) | 1986-02-22 | 1986-02-22 | Ceramic board with built-in capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61036531A JPH0754778B2 (en) | 1986-02-22 | 1986-02-22 | Ceramic board with built-in capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62196811A true JPS62196811A (en) | 1987-08-31 |
JPH0754778B2 JPH0754778B2 (en) | 1995-06-07 |
Family
ID=12472372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61036531A Expired - Lifetime JPH0754778B2 (en) | 1986-02-22 | 1986-02-22 | Ceramic board with built-in capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0754778B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01166599A (en) * | 1987-12-22 | 1989-06-30 | Narumi China Corp | Manufacture of laminated ceramic substrate |
JPH01321695A (en) * | 1988-06-23 | 1989-12-27 | Mitsubishi Mining & Cement Co Ltd | Ceramic composite circuit substrate |
JPH02229462A (en) * | 1989-03-02 | 1990-09-12 | Tdk Corp | Structure of laminated hybrid integrated circuit component |
JPH02244796A (en) * | 1989-03-17 | 1990-09-28 | Mitsubishi Mining & Cement Co Ltd | Ceramic substrate with built-in capacitor |
JPH0465107A (en) * | 1990-07-05 | 1992-03-02 | Murata Mfg Co Ltd | Laminated composite part |
JP2010103559A (en) * | 2010-01-25 | 2010-05-06 | Kyocera Corp | Method of manufacturing electronic element built-in wiring board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55126631U (en) * | 1979-02-28 | 1980-09-08 | ||
JPS5878411A (en) * | 1981-11-05 | 1983-05-12 | 株式会社日立製作所 | Wet type multilayer ceramic board |
-
1986
- 1986-02-22 JP JP61036531A patent/JPH0754778B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55126631U (en) * | 1979-02-28 | 1980-09-08 | ||
JPS5878411A (en) * | 1981-11-05 | 1983-05-12 | 株式会社日立製作所 | Wet type multilayer ceramic board |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01166599A (en) * | 1987-12-22 | 1989-06-30 | Narumi China Corp | Manufacture of laminated ceramic substrate |
JPH01321695A (en) * | 1988-06-23 | 1989-12-27 | Mitsubishi Mining & Cement Co Ltd | Ceramic composite circuit substrate |
JPH02229462A (en) * | 1989-03-02 | 1990-09-12 | Tdk Corp | Structure of laminated hybrid integrated circuit component |
JPH02244796A (en) * | 1989-03-17 | 1990-09-28 | Mitsubishi Mining & Cement Co Ltd | Ceramic substrate with built-in capacitor |
JPH0465107A (en) * | 1990-07-05 | 1992-03-02 | Murata Mfg Co Ltd | Laminated composite part |
JP2010103559A (en) * | 2010-01-25 | 2010-05-06 | Kyocera Corp | Method of manufacturing electronic element built-in wiring board |
Also Published As
Publication number | Publication date |
---|---|
JPH0754778B2 (en) | 1995-06-07 |
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