TW200908828A - Circuitized substrate with internal resistor, method of making said circuitized substrate, and electrical assembly utilizing said circuitized substrate - Google Patents

Abstract

A circuitized substrate which utilizes at least one internal (embedded) resistor as part thereof, the resistor comprised of a material including resin and a quantity of powders of nano-particle and/or micro-particle sizes. The resistor serves to decrease the capacitance in the formed circuit while only slightly increasing the high frequency resistance, thereby improving circuit performance through the substantial elimination of some discontinuities known to exist in structures like these. An electrical assembly (substrate and at least one electrical component) is also provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to providing resistors in circuitized substrates such as printed circuit boards, wafer carriers, and the like, and more particularly to methods for achieving the same It relates to products including these internal resistors as part of them. Even more particularly, the present invention relates to such methods and products for forming internal resistors using powder materials having nanoparticle or microparticles or a combination of both as part of it. The agent filed on April 6, 2007 is EI-2-06-013 and titled "Non-Flaking Capacitor Material, Capacitive Substrate Having An Internal Capacitor Therein Including Said Non-Flaking Capacitor Material And Method Of Making In the serial number (SN) (_/_, _) of A Capacitor Member For Use In A Capacitive Substrate, the definition includes thermosetting resin (such as epoxy resin), high molecular weight toughening agent (such as phenoxy resin) and certain a capacitor material of a nano-particle of a quantity of ferroelectric ceramic material (eg, barium titanate), the capacitor material not including continuous or semi-continuous fibers (eg, fiberglass) as part of it. The material is suitable for positioning in a layer form first The conductor member is heated to a predetermined temperature at which the material will not have any substantial exfoliation characteristics. A second conductor member can then be positioned over the material to form a capacitor member, which can then be incorporated into the substrate to form a capacitive substrate. The component can be positioned on the substrate and capacitively coupled to the internal capacitor. The title is "Method Of Making A Capa Citive Substrate For

Use As Part Of A Larger Circuitized Substrate, Method of 131317.doc 200908828

Making Said Circuitized Substrate and Method of Making

An Information Handling System Including Said Circuitized Substrate " and in SN n/352,279, filed on Feb. 13, 2006, the method of forming an electric valley substrate, wherein at least one layer of capacitive dielectric material is screened or Inkjet printing onto the conductor and subsequent processing of the substrate further includes adding vias to couple the selected components within the substrate to form the inner cells of the substrate as the substrate. The capacitive substrate can be incorporated into, for example, a larger circuitized substrate to form an electron assembly. A method of fabricating an information processing system including such substrates is also provided. In one example, an epoxy phenol varnish resin and a phenoxy resin were mixed together with barium titanate (BaTi〇3) powder, propylene glycol monomethyl ether acetate and methyl ethyl ketone, and ball milled for three days. The 25 micron film of this mixed composite was then deposited on a copper substrate and dried in an oven at about 140 ° C for three minutes to remove residual organic solvent. Thereafter, it was cured in an oven at 19 CTC for two hours. A second electrical conductor is then formed on top of the cured film using a mask typically used for such sputtering operations using a sputtering operation. Method Of Making A Capacitive Substrate Using Photoimageable Dielectric For Use As Part Of A Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making An Information

Handling System Including Said Circuitized Substrate" and in SN 1 1/352,276, filed on Feb. 13, 2006, the disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire disclosure Printing onto the conductor and thereafter processing the substrate further includes adding a 131317.doc 200908828 via to couple the selected components within the substrate to form at least two capacitors as internal components of the substrate. Photoimageable materials are used to facilitate the positioning of the printed capacitive dielectric. The capacitive substrate can be incorporated into, for example, a larger circuitized substrate to form an electron assembly. A method of making an information processing system including such substrates is also provided. The title of the application is "Circuitized Substrate With Solder-Coated Microparticle Paste Connections, Multilayered Substrate Assembly, Electrical Assembly And Information Handling System Utilizing Same And Method Of Making Said Substrate " SN 11/244, 180 A circuitized substrate comprising a conductive paste for providing an electrical connection. In one embodiment, the paste comprises a binder component and at least one metal component comprising microparticles. In another embodiment, the paste comprises a binder and a plurality of nanowires. The choice of microparticle or nanowire includes the solder layer thereon. A method of fabricating the substrate is also provided as is suitable for an electronic assembly and an information processing system having the substrate as a part thereof. Under the title ’’Method Of Making An Internal Capacitive

Substrate For Use In a Circuitized Substrate And Method Of Making Said Circuitized Substrate 1 ' and in SN 11/172,794, filed on Jul. 5, 2005, a method of forming a capacitive substrate is defined, wherein the first and second guiding systems The electrical mass is formed oppositely and one of the conductors is electrically coupled to the via connection. Each acts as an electrode for the resulting capacitor. The substrate is then adapted to be incorporated into a larger structure to form a circuitized substrate such as a printed circuit board or wafer carrier. Additional capacitors are also possible 131317.doc 200908828. In one example (Example 5) cited in the application of this application, an epoxy novolac resin and a phenoxy resin together with barium titanate (BaTi〇3) powder and propylene glycol monomethyl ether acetate and Methyl ethyl ketone was mixed together and ball milled three times. A 2.5 micron film of this hybrid composite was deposited on a copper substrate and dried in an oven at about MOt for three minutes to remove residual organic solvent. After that, it was at 190 in the flood box. (: curing for two hours. Then use the (4) operation to form a second conductor on top of the cured film using the mask normally used for the sputtering operation. The title of the application was “Resist〇r Materiai” on July 5, 2005.汕

Metal Component For Use In Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate And Information Handling System Utilizing Said Circuhized - also batched "sn ll/m, 786, defines an interior suitable for use as a circuitized substrate The material of the Dengdao knife of the resistor includes a polymer resin and a quantity of nano powder comprising a mixture of at least one metal component and at least one type of ceramic: a component. The Tao Jing component can be a ferroelectric pottery and/or a high surface area pottery and/or a transparent oxide and/or a doped agar. Alternatively, the material will comprise a polymer tree sap and a non-semiconductor' wherein the nanopowder comprises at least one metal coated ceramic and/or at least one oxide coated metal component. A circuitized substrate suitable for use of the material and resistor therein and a method of fabricating the same are also provided. An electronic assembly (substrate and at least one electronic component) and an information processing system (such as a personal computer) are also provided.

The title of the request in January 10, 2005 is (10) μ Xian (5) W 131317.doc 200908828

Use In Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, And Information Handling System Utilizing Said Circuitized Substrate" SN ll/〇3i, 〇85, defines a portion suitable for use as an internal capacitor in a circuitized substrate The material, wherein the material comprises a polymer tree wax and a quantity of ceramic material nano-powder having a particle size substantially in the range between about 0.01 microns and about 〇90 microns and the selected one of the 4 particles The surface area is in the range of about 2. 〇 to about 20 square meters per gram of pillow. A circuitized substrate suitable for use of the material and the electric grid device and a method of manufacturing the same are also provided. An electronic assembly (substrate and at least one electronic component) and an information processing system (such as a personal computer) are also provided. The title of the application was also filed on January 1, 2005. Capacit〇r MateHal With Metal Component For Use In Circuitized Substrates, Circuitized Substrate Utilizing Same, Method Of Making

Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized sn 11/031, G74, defined as a material suitable for use as part of an internal capacitor within a circuitized substrate, comprising a polymer resin and a quantity comprising at least one metal a nano powder of a mixture of a component and at least one ferroelectric ceramic component, the ferroelectric ceramic component having a particle size substantially in a range between about 微米1 μm and about 9.9 μm And a surface area in the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate suitable for use of the material and capacitor therein and a method of fabricating the same are also provided. Also 131317.doc •10· 200908828 An electronic assembly (substrate and at least one electronic component) and an information processing system (such as a personal computer) are provided. S.N. 11/〇31, 〇74 division 5. Team 11/324, 273 application on January 4, 2002. S.N. 11/031,074 is currently U.S. Patent 7,025,607. In the title ""Electrical Assembly With Internal Memory,

Circuitized Substrate Having Electrical Components Positioned Thereon, Method Of Making Same, And (Informatlon Handling System Utilizing Same) and SN l〇/9〇〇, 386, filed on July 28, 2004, to define an electronic circuit including a circuitized substrate The circuit board includes an organic dielectric material having a first conductive pattern thereon. At least a portion of the dielectric layer and the pattern form a first base portion of the organic memory device, and the remaining portion is formed on the pattern portion a first conductive layer and a second conductive circuit formed on the polymer layer. If the second dielectric layer is formed on the second conductive circuit and the first circuit pattern to block the organic § memory device, the device is passed through the second The dielectric layer is electrically coupled to the first electronic component and the first electronic component is electrically coupled to the second electronic component. As with an information processing system suitable for using one or more of the electronic assemblies as part thereof, a dielectric processing system is also provided. A method of making the electronic assembly. SN 1〇/9〇〇, 386 is now U.S. Patent 7,045,897. In the title "Circuitized Substrate With Inte Rnal Organic

Memory Device, Method Of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same, and in a sn i〇/9〇〇, 385 application filed on July 28, 2004, a circuitized substrate is defined. It contains a layer of dielectric material with a conductive pattern on it to 131317.doc -11 - 200908828. At least a portion of the pattern is used as a first layer of an organic memory device, the device additionally including at least a second dielectric layer on the pattern and a second pattern aligned with the lower half to achieve a plurality of contact points The device is formed. The substrate is preferably combined with other dielectric circuit layered assemblies to form a multilayer substrate on which discrete electronic components (e.g., logic wafers) that are coupled to the internal memory device for operation in conjunction therewith. An electronic assembly capable of using the substrate is also provided as an information processing system suitable for using one or more of the electronic assemblies as a part thereof. All of the above claims are assigned to the same assignee as the present invention. This application is a continuation of S.N 1 1/172,786, which is a partial continuation of S.N 11/〇31, 〇 74 (now U.S. Patent 7,025,607) dated January 1, 2005. [Prior Art] Printed circuit boards (hereinafter also referred to as PCBs), wafer carriers, and the like are often referred to herein as circuitized substrates, usually in a laminated form.

131317.doc No increase in demand' so this situation will be set in the future to increase the available surface area of the substrate (usually • 12-200908828 also known as "effective area"), which has been carried out with a variety of functional components (such as resistors, capacitors and their Analogs) include various attempts to mount on a single component. When the passive device is in the configuration, the devices are commonly referred to collectively and individually as a monolithic passive device or the like, meaning that The functional components are integrated into a single component. Because of this external positioning, the components still utilize the "effective area" of the board, (although less than a single form of "effective area"). Corresponding to the above limitations, it has been proposed to embed discrete passive components in the 0 卩 0 卩 基板 in the substrate f, which are called embedded passive components. Capacitors or resistors designed to be disposed within a substrate (e.g., between selected layers) may therefore be referred to as embedded integral passive components, or more simply embedded resistors or capacitors. This capacitor thus provides internal capacitance while the resistor provides internal resistance. The result of this internal positioning is that the device is externally positioned on the outer surface of the PCB without the need to also save significant pcB surface area. Some of the documents listed below, in particular U.S. Patent No. 6, 〇 21, 〇 5, describe the internal use of resistors as passive components of PCBs. As described in SN 11/031, G74 (now U.S. Patent 7, G25, 6G7), internal capacitors and other internal conductive structures, components or devices have been provided in circuitized substrates (PCBs) in the past (- A good example is an internal semiconductor wafer), some of which include the use of nanopowders. The following are some examples of various substrate structures, including a four-substrate substrate structure of the embedded component as described above, including the substrate structure using the nano powder, and their anti-construction The citation of the present invention is not an admission that any of the prior art. 131317.doc •13· 200908828

The coating of high rocker polymers is described in U.S. Patent Application Publication No. 2005/0051360 A1, entitled "Polymer Thick-Film Resistive Paste, A Polymer Thick-Film Resistor And A Method And An Apparatus For The Manufacture Thereof. Thick film resistive paste for making a polymer thick film resistor with improved tolerance by providing an applicator having a blade that is inclined at an angle of from 1 to 85 to the surface of the printed circuit board, apparatus and method The tilting blade causes a rotational movement of the fluid within the polymer thick film resistive paste bead as the applicator blade moves relative to the printed circuit board. This rotational motion increases the shear strain rate experienced by the paste within the bead. And the cavity of the shape of the resistor is more effectively filled without the inclusion of gas/package, undergoes elastic recovery of the paste and does not cause surface cracking of the paste. vviui Kesistor is in the "Wiring Board Provided Process F" In the U.S. Patent Application Publication No. 2005/0000728 A1, the entire disclosure of which is incorporated herein by reference. The board includes an insulating substrate having a surface; a wiring pattern formed on the surface, the wiring patterns including first and second electrodes spaced apart from each other by a first resistor formed on the surface (horizontal type I resistor) The first resistor has respective ends connected to the first and second electrodes; the wiring patterns additionally include a third electrode 'occupying a first planar region on the surface formed on the third electrode A second resistor (vertical resistor) is formed on the fourth electrode on the resistor; the second resistor and the fourth electrode are located in a second planar region in the first planar region. "SilVer_C〇ated particles, Meth〇d And a叩 her s 131317.doc • 14- 200908828

The use of silver-containing powders and the high quality silver containing for the manufacture of small and narrow size distributions are described in US Patent Application Publication No. 2, 4/23, 1758 ai, of Manufacture, Silver-Containing Devices, Made There. Particle method and equipment. The aerosol is produced from the liquid. Feed and sent to the furnace' where the droplets of liquid in the aerosol vaporize to allow formation of the desired particles which are subsequently collected in a particle collector. Aerosol production involves the preparation of high quality aerosols having a narrow droplet size distribution, tight control of droplet size, and high droplet loading suitable for commercial applications. A resistive film for use in a potentiometer is described in U.S. Patent Application Publication No. 2003/0 1464 1 8 A1, entitled "Resistive Film". The film is in contact with a movable wiper. The film comprises a cured polymer resin and a cured thermosetting resin. The conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resin to have electrical resistance. The carbon nano particles are also dispersed in the film. The nano particles increase the wear resistance of the resistive film and reduce when the wiper moves over the film. A method of making a substrate having a buried capacitor, wherein the method of including a lower electrode pad is described in US Patent No. 6,967,138, entitled "Process For Manufacturing A Substrate", "Embedded Capacitor". A metal wiring layer is formed on the substrate base. The dielectric layer is formed on the substrate base by an accumulation coating process. A hole is formed in the dielectric layer to expose the lower electrode pad ' and then the dielectric material is filled in the hole. Grinding the dielectric material to have a ground surface coplanar with the dielectric layer. A second metal wiring layer including an upper electrode pad Formed on the dielectric layer, the upper electrode pad covers the ground surface of the dielectric material and is parallel to the lower electrode pad to form an embedded capacitor for 131317.doc -15-200908828. The title is ''Nanosized Intermetallic p〇wders&quot U.S. Patent No. 6,746,508, the disclosure of which is incorporated herein by reference in its entirety in U.S. Pat. Applications Nanosized powders can be used to make structural parts with enhanced mechanical properties, magnetic parts with enhanced magnetic saturation, and enhanced catalytic activity.

Cathode materials, thick film circuit components with enhanced resolution, and screen printed images such as magnetic strip codes with enhanced magnetic properties. In contrast to the non-magnetic monolithic (10) material at room temperature, the nanoparticles exhibit magnetic properties at room temperature. In U.S. Patent No. 4, entitled "Resistive Film", a resistive film for use in a potentiometer. The film is attached to a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resin to be electrically resistive. The carbon nanoparticle is also dispersed in the film. The nanoparticle increases the electrical resistance of the thin film to reduce the electrical noise when the wiper moves across the film. In the preparation of the exemplary composition, by mixing 10·20% by weight of the polymer with the total composition ((0% by weight of the thermosetting tree is mixed with 6〇_8〇% by weight) The polymer solution is prepared by mixing the polymer with the conductive and rice granules to form a paste having a fine particle size. At this time, if necessary, a surfactant and a rheological additive may be added to improve the resistive composition. Characteristics: Monitor the particle size range and viscosity of (4) to obtain the resistivity suitable for use in the positioner (4). Grinding time on the ball mill and research $ I31317.doc -16· 200908828 疋 final particle distribution, size and resulting rheology. U.S. Patent No. 6, '704, 2G7, issued on Mar. 9, 2004, entitled "Device and Method f0r Interstitial Components in a primed B. a first printed circuit board (pCB), wherein the above-described board device (eg, an Asic wafer) is mounted thereon. The PCB includes a second layer having third and fourth surfaces. One of the surfaces may include a securely holding the gap assembly Concave The via is electrically connected to the via layer and is also coupled to the trace of the interstitial component. The interstitial component includes components such as a diode, a transistor, a resistor, a capacitor, a thermocouple, and the like. In a preferred embodiment, the interstitial component is a resistor having a size similar to that of a "0402" resistor having a thickness of about 0.014 Å (manufactured by 11 〇 11111 (manufactured by 〇). In the title "Integral Capacitance For Printed Circuit Board A method of producing a monolithic capacitor assembly included in a printed circuit board is described in U.S. Patent No. 6,616,794, the disclosure of which is incorporated herein by reference. A dielectric layer that is electrically constant and easily penetrated by microvias. In the method described in this patent, a slurry or suspension of hydrothermally prepared nanopowder and solvent is prepared. Suitable bonding materials such as polymers are The nanopowder slurry is mixed to produce a composite mixture formed as a dielectric layer. It can be laminated or metallized (such as vapor deposition or sputtering). Plating) The dielectric layer is placed on the conductive layer and then cured, or the conductive layer can be applied to the cured dielectric layer. "High Dielectric Constant Nano-Structure 131317.doc 17- 200908828

Polymer-Ceramic Composite, and in U.S. Patent No. 6,544,651, issued to A.S. In particular, a certain percentage of c〇(Hi) increases the dielectric constant of an epoxide. The high dielectric polymer is combined with a filler, preferably a ceramic filler, to form A high dielectric constant two phase composite. It is apparent that a composite having a ceramic loading of from about 30 to about 90 volume percent and a high dielectric matrix polymer (preferably epoxide) has a dielectric constant greater than about 6 Torr. Also referred to in this patent is a composite having a dielectric constant greater than about 74 to about 150. Also mentioned is an inset having a capacitance density of at least 25 nF/cm2, preferably at least 35 nF/cm2, and an optimum 50 nF/cm2. A buried capacitor is defined in U.S. Patent No. 6,524,352, the entire disclosure of which is incorporated herein by its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire The power supply capacity of the parallel capacitor structure. Alternatively, a capacitor can be used as an interconnect to interconnect two different electronic components, such as a wafer carrier, a circuit board, and even a semiconductor wafer, while still providing the required capacitance level for one or more of such components. The capacitor includes at least one inner conductive layer, two additional conductor layers added on opposite sides of the inner conductor, and an inorganic dielectric material (preferably an oxide layer on the outer surface of the second conductor layer or coated on the second conductor layer) A suitable dielectric material such as barium titanate). In addition, the capacitor includes an outer conductor layer 'on top of the inorganic dielectric material' thereby forming a shunt capacitor between the inner and the added conductive layer and the outer conductor. In U.S. Patent 6,5GG, 35G, entitled "Formation of Thin Film Resist 〇 rs, <RTIgt;</RTI>> A method of electrically contacting a layer of patterned resistive material. Forming a three-layer structure comprising a metal conductive layer, an intermediate layer formed of a material degradable by a chemical surrogate, and a resistive material layer having a sufficient porosity such that the chemical agent of the intermediate layer is permeable to the f-resistance material and The intermediate layer is chemically degraded such that the resistive material can be removed from the conductive layer wherever the intermediate layer is chemically degraded. A patterned photoresist layer is formed on the layer of resistive material. The layer of resistive material is exposed to the chemical (iv) agent of the intermediate layer such that the (iv) engraving agent penetrates the layer of porous resistive material and degrades the intermediate layer. Subsequently, the resistive material layer is partially removed regardless of where the intermediate layer is degraded. In the title of "Hybrid Capacitor· And Meth〇d 〇f (4) (10) (10), and in U.S. Patent No. 6,446, 3i7 issued on September 1, 2002, the hybrid capacitors associated with integrated circuit packages are described. Provides multiple levels of excess, off-chip capacitance to the die load. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded in the package and electrically coupled to a second source of off-chip capacitance. A parallel plate capacitor is disposed beneath the die and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer of electrically isolated top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors and/or - or multiple discrete capacitors and/or additional parallel plate capacitors. Each of the self-aligned via capacitors is buried in the package and has an internal conductor and an external via. The inner body is electrically connected to the top or bottom ^ electrical layer, and is external. The P conductor is electrically connected to the S layer. The discrete capacitor is electrically connected to the contact from the conductive layer to the surface of the package. During operation, the low-inductance parallel plate in the conductive layer provides grounding, while the other conductive layer provides the power plane 131317.doc -19- 200908828. The Resistors F0r Electr〇nic pack, described in U.S. Patent No. 1, issued on Nov. 28, describes thin-layer resistors that are insulated and can be embedded in a printed circuit board. The preferred resistive material is a homogeneous mixture of a starting material such as a starting metal and a second electrical material such as cerium oxide or oxidized. Even a small amount of metal mixed with metal significantly increases the resistance of the metal. Preferably, the resistive material is deposited on the insulating substrate by combustion chemical vapor deposition (CCVD). In the case of zero-valent metals and dielectric materials, a homogeneous mixture is achieved by co-depositing metal and dielectric materials by CCVD. To form a discrete block of resistive material, any metal-based resistor material can be engraved, including those based on precious metals. Thus, the resistive material layer can be covered with a patterned anti-contact agent such as an exposed and developed photoresist, and the underlying resistive material is etched. <Exposed portion Q This patent also describes the formation of a thin layer resistor, such thin The layer resistor includes an insulating substrate, discrete blocks of the resistive material layer, and a conductive material in electrical contact with the spaced locations on the resistive material layer block, the conductive material providing electrical connection of the resistive material block to the electronic circuit. The structures of the insulating material, the resistive material, and the conductive material can be formed by a selective characterization process. In the title "Multi-layered Substrate With Built-In Capacitor

A multi-layer substrate having a built-in capacitor for voltageing between a power plane and a ground plane of a multilayer substrate is described in U.S. Patent No. 6,395,996, issued toK. Decoupling of high frequency noise generated by fluctuations. At least one dielectric material filled in the via between the power plane and the ground plane 131317.doc •20· 200908828 and including a high dielectric constant is used to form a built-in capacitor. An internal portion capable of forming a larger circuit board or the like is described in U.S. Patent No. 6,370,012, issued to <RTIgt;Capacitor Laminate For Use In a Printed Circuit Board And As An Inter-connector&quot; and issued on April 9, 2002. Part of the parallel capacitor structure for which a capacitor is provided. Alternatively, the capacitor can be used to interconnect two different electronic components

Interconnectors (e.g., wafer carriers, circuit boards, and even semiconductor wafers) while still providing the required capacitance levels for one or more of such components. The capacitor includes at least one inner conductive layer, two additional conductor layers added on opposite sides of the inner conductor, and an inorganic dielectric material (preferably an oxide layer on the outer surface of the second conductor layer or coated on the second conductor layer) A suitable dielectric material such as barium titanate). Additionally, the capacitor includes an outer conductor layer on top of the inorganic dielectric material, thereby forming a shunt capacitor between the inner and the added conductive layer and the outer conductor. A method of packaging a wafer, including a step of providing an interconnect layer, is described in U.S. Patent No. 5, the entire disclosure of which is incorporated herein by reference. Including an insulating material having a first side and a second side, an initial metal patterned on the second side metallized portion of the second side and not on the second side non-metallized portion of the second side, from the first side a substrate via extending to one of the second side metallization portions and a wafer via extending from the first side to the second side non-metallized portion. The method also includes positioning the wafer on the second side, wherein the wafer The wafer liner is aligned with the through-wafer via, and the connection metallization in the selected portion of the first side of the first side of the interconnect layer and the via lining extends to the second side metallization and wafer lining of FIG. 131317.doc 200908828 Pad. Molding &quot;substrate' or other dielectric material around the wafer. Titled on March 27, 2001, "Merminate (J Method of Manufacture There of) US Patent 6, 2 7,595, describes a fabric resin dielectric material for use in a layered structure and a method of manufacturing the same. The resulting structure is suitable for use in a printed circuit board or a wafer carrier substrate. The resin can be used for large scale such as when Lili is used worldwide. "FR4&quot; composite epoxy resin. Resin materials based on bismaleimide-triazine (BT) are also acceptable, and the patent supplements more preferably, the resin is a phenolic system known in the art. A hardenable resin material having a glass transition temperature of about 145 degrees FC. The title issued on November 21, 2000 is &quot;High Didectric c〇nstant

A flexible, high dielectric constant polyimide film comprising a single layer of an adhesive thermoplastic polyimide film or having a film and a film of a flexible, high dielectric constant polyimide film, is described in U.S. Patent No. 5,456. a multilayer polyimide film having one or both sides of an adhesive thermoplastic polyimide film layer bonded thereto, and having a ferroelectric ceramic of 4 to 85 weight / 〇 dispersed in at least one of the polyimide layers A filler such as barium titanate or barium titanate coated with polyimide, and having a dielectric constant of 4 to 6 Torr. High dielectric constant Polyimine films are used in electronic circuits and electronic components such as multilayer printed circuits, flexible circuits, semiconductor packages, and embedded (internal) thin film capacitors. The title issued on July 4, 2000 is &quot;Bridging Method of 131317.doc 200908828

An integrated circuit package having first and second layers; a plurality of routing pads integrated with the first layer; respectively disposed in the first layer, is described in US Pat. No. 6,084,306. a plurality of upper and lower conduits on the upper surface and the lower surface, one of the upper catheters being electrically connected; one of the plurality of liners disposed on the second layer; the gasket and the lower conduit electrically The through vias are bonded to the wafer having the second layer of bonded backing, and at least one of the bonded backings is electrically coupled to one of the routing pads. In the case of "Individual Embedded Capacitors For"

Laminated Printed Circuit Boards &quot; and U.S. Patent No. 6, ,68,782, issued May 30, 2000, describes a method of making ia. individual buried-type electric grids in a multilayer printed circuit board. This method is said to be suitable for implementation using standard printed circuit board fabrication techniques. Capacitor fabrication is based on a sequential construction technique using a first patternable insulator. After patterning the insulator, the pattern trench is filled with a high dielectric constant material, typically a polymer/ceramic composite. The capacitance value is defined by the pattern size, the thickness of the composite, and the dielectric constant. Capacitor electrodes and other circuitry can be formed by etching laminated copper, by metal evaporation, or by depositing a conductive ink. In the title, Printed Circuit B〇ards Whh Integrated

In U.S. Patent No. 6,021,05, the disclosure of which is incorporated herein by reference in its entirety, the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of Device. The method comprises the steps of: manufacturing an individual I of a printed circuit board having its circuit, and subsequently shielding a polymer ink having a resistance value of 131317.doc • 23-200908828; a zeta value or a magnetic value to form a resistor, Capacitors and inductors. Each layer of the board is cured to dry the polymer ink and thereafter the individual layers are bonded together to form a multilayer board. The title issued on November 3, 1998 is &quot;Bare Chip Mounting Printed Circuit Board and a Method of Manufacturing

A method of manufacturing a "bare-crystalline" multilayer printed circuit board in which any number of wiring circuit conductor layers and insulating layers are alternately stacked on a printed circuit board as a substrate, is described in US Pat. No. 5,831,833. One or both surfaces and a recessed portion having an upper portion of the resin-encapsulated bare portion is formed on the surface of the printed circuit board. In the preferred embodiment presented, one of the insulating layers It is made of a photosensitive resin, and the groove portion of the bare portion is formed by photolithography of an insulating layer made of a photosensitive tree. The title issued on June 20, 1995 is "Electr〇nic AssemMy".

An electronic assembly having a double-sided wireless assembly and two printed circuit boards is described in U.S. Patent No. 5,426,263, the entire disclosure of which is incorporated herein. The assembly has a plurality of electronic final 4 or pads on two opposing major surfaces. Each of the printed circuit boards has a printed circuit pattern&apos; having a plurality of linings corresponding to the electronic terminals on either side of the two-sided wireless assembly. The electronic terminals on one side of the assembly are connected to the pads on the first board and the electronic terminals on the other side of the no-wire assembly are connected to the linings on the first board. The printed circuit boards are joined together to form a multilayer circuit board ' such that the double-sided wireless assembly is embedded or recessed therein. The board is soldered to the pad of the printed circuit board. 131317.doc -24- 200908828 The title issued in the first month of January 1994 is: Ding hree dimensi〇nai Memory Card Structure with Internal (10) Chip She &quot; US Patent 5, 2_92, described - including the implant A card structure of an inner array of semiconductor wafers. § Hikka structure includes a power core and a plurality of wafer cores. Each wafer core is bonded to a power core on an opposite surface of the power core, and each wafer core includes a compensator core having a two-dimensional array of wafer apertures. Each of the wafer apertures allows one of the semiconductor wafers to be implanted in the armor. Additionally, a flexible dielectric material is placed over the major surface of the compensator core except the bottom of the wafer aperture. The flexible dielectric material has a low dielectric constant and has a coefficient of thermal expansion that is compatible with the thermal expansion coefficients of the semiconductor wafer and the compensation core to maintain thermal expansion stability with the wafer and the compensator core. In the title &quot;Printed Circuit Board Having An

Decoupling Capacitive Element" and 5,162,977 issued November 1, 1992, describes a pcB comprising a high capacitance power distribution core that is compatible with standard printed circuit board assembly technology. The high capacitance core has The dielectric constant of the plane constant of the dielectric constant consists of a ground plane and a power plane. The aμ constant energy material is usually a glass fiber impregnated with a bonding material such as an epoxy resin having a high dielectric constant loaded with a ferroelectric ceramic material. The ferroelectric ceramic material is usually a nano powder combined with an epoxy bonding material. According to this patent, the resulting capacitance of the power distribution core is sufficient to completely eliminate the need to decouple the capacitor. However, the use of the pre-layer in the dielectric layer The calcined and ground ceramic 1 nm powder poses an obstacle to the formation of through holes (electroconductive holes that allow electrons between the conductive layers of pCB). The pre-baked and ground ceramic nano-powder particles have a particle size of 500-20,000 nm (nm). Typical dimensions in the range. In addition, 131317.doc -25- 200908828 The particle distribution in this range is usually quite extensive, which means that it can coexist with 5〇〇nm particles. 10,000 nm particles. Particles of different sizes in the dielectric layer 7 are often the main obstacles to the formation of vias, which have a very large tool radius, which is also known as pores in the industry due to the presence of larger particles. Another problem associated with pre-cooked ceramics is the classic substantial voltage of the dielectric layer without the ability to traverse the layer. Typically, the capacitive layer within the core PCB is subjected to at least _volt (v) to have Qualifications are used as: (4) Construction of the components. In the capacitor layer, the presence of relatively larger ceramic particles in the pre-cooked (four) nano-powder prevents the use of very thin layers, because the voltage near the boundary of the large particles provides voltage breakdown. Path. Because the larger planar capacitance can also be achieved by reducing the thickness of the dielectric layer as shown in the equation above, this is further step-by-step. The thickness is therefore made of particles. In March 24, 1992 The title of the Japanese version is:, Three-dimensional M_ry Card Structure, h (4) Curry Dbect (3) 卩 her ch_t, US Patent 5, G99, 3G9, describes an embedded three-dimensional array containing semiconductor memory chips. Memory card structure The card structure includes at least one memory core and at least one power core bonded together in an overlapping relationship. Each memory core includes a two-dimensional array having wafer hole locations on each side of the plane The copper-recorded steel-copper (CIC) thermal conductor plane. The polytetrafluoroethylene (deleted) covers the main surface of the mature body except the bottom of the wafer hole. The memory wafer is placed on the wafer. The holes are covered by an insulating and wiring layer. Each of the power cores comprises at least one CIC conductor that is flat and ten-sided and covers the major surface of the conductor plane. Provide electrical connections for the vertical and horizontal planes inside the card structure. 131317.doc -26- 200908828 Prepare the path and cooling path. In U.S. Patent No. 5, 〇79, 〇69, issued on Jan. 7, 1992, the entire disclosure of which is incorporated herein by reference. Capacitor laminate of a bypass capacitive function of the device, the capacitor laminate being formed from a conventional conductive layer and a dielectric layer, whereby each individual external device is said to be proportional to the capacitor laminate unit

Capacitance is provided by a capacitor borrowed from other portions of the capacitor laminate. The capacitive function of the capacitor laminate depends on the device. That is, the resulting PCB still needs to utilize the external device on it = this does not provide the above-mentioned effective surface area savings of the PCB external surface that is required and required in today's technology. U.S. Patent No. 5, 〇i6, 〇 85, issued on May 14, 1st, which is incorporated herein by reference to the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the utility of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the utility of The groove is square and is set at 45 degrees to the outside of the rectangular shape of the package. The package uses a layer of the conductive plane constituting the package, wherein the inner opening is a stepped riser connection point, wherein the lowermost layer of the wafer opening can be Located outside the assembly, t, shallower wafer opening recess. This is of course different from the internally formed capacitive or semiconducting components, but does mention the internal H layer for the specified purpose as part of the internal structure. The teachings of the application in the application, which is incorporated herein by reference, is incorporated herein by reference. Doc -27- 200908828 Commercially available dielectric powders are known to have oxides or oxide precursors (such as carbonates, hydroxides or nitrates) of cerium, calcium, titanium and the like in an appropriate stoichiometric amount. The mixture of salts) is produced by a high temperature, solid state reaction. In the calcination process, the reactants are wet ground to achieve the desired final and final mixture. The slurry is dried and sometimes up to 1,300 degrees FC. Calcined at a high temperature to achieve the f-g reaction. Thereafter, the calcined product is ground to produce a powder. Although the pre-baked and ground dielectric formulation produced by the solid phase reaction can be used. Accepted 'but these formulations have several disadvantages. Firstly, the 'grinding step' acts as a source of smear, which can adversely affect electrical properties. Second, the abrasive product can be composed of irregularly shaped broken aggregates, which are usually too large in size And having a width distribution of 5 〇〇 2 〇, 〇〇〇 nm. Therefore, the film produced using the powders is limited to a thickness greater than the maximum particle size 'first, using a pre-fired ground ceramic powder to produce a powder suspension The liquid or composite must be used immediately after dispersion, due to the high sedimentation rate associated with large particles. The stability of barium titanate with particles larger than 2 GG nm will be met. 3⁄4. X } / 〇, ', σ曰曰 two crystals and a large increase in dielectric constant due to phase transition at high temperatures. Therefore, it is obviously dependent on the use of nanopowder as a PCB internal component or the like. Part of the advantageous features of the PCB manufacturing method, such as those described in the selection of the above patents, have the benefit of providing PC with optimum functional performance in terms of internal resistance, capacitance or other electrical properties: All kinds of improper aspects. The above situation is especially cautious when you try to meet the needs of today's miniaturization (including the use of the signal line and through hole (defined below) of the π-selection pattern). The extremely close positioning of such vias and signal lines can result in discontinuities occurring therein, which will adversely affect the product, especially at still frequencies (which are also required in many of today's products). Successful operation under ). These discontinuities may also be the result of a so-called through-hole &quot;wire foot&quot;, in which the energy of the same velocity nickname transmitted from the l-hole, such as the 〆, is from the end of the through-hole (referred to as &quot;rope&quot;)', Bounce back &quot;. Such reflections and resonances may be sufficient to cause signal degradation, particularly as described when the signal lines and/or vias are positioned in close proximity to one another. Therefore, the successful elimination of such discontinuities is highly desirable for many of today's circuitized substrates, particularly such circuitized substrates that are intended to transmit high speed signals using vias and/or signal lines. The invention in particular (d) substantially eliminates a number of such continuity by providing an internal t-resist material as part of the internal circuit structure. By doing so, the present invention is capable of reducing capacitance and increasing high frequency resistance at critical locations within the circuit&apos; thereby improving system performance. The present invention having such features and other features discernible from the teachings herein will constitute a significant advancement in the art. SUMMARY OF THE INVENTION It is therefore a primary goal of the present invention to enhance circuitized substrate technology by providing a circuitized substrate having the advantageous features taught herein. Another object of the present invention is to provide a method of fabricating the circuitized substrate that can be implemented in a relatively convenient manner and at relatively low cost. The present invention is directed to providing an electronic assembly capable of using the circuitized substrate and thus benefiting from several advantageous features thereof. Another object of the present invention is to provide an information processing system that can utilize a circuitized substrate as a p-knife to thereby also benefit from several advantageous features thereof. 1313l7.doc • 29-200908828 A method of providing a circuitized substrate for a portion of its circuitry, comprising the steps of providing a first dielectric layer and forming a first dielectric layer An electrical conductor, forming an opening in the first conductive body to position a predetermined amount of resistor material, substantially forming a second dielectric layer on the certain amount of resistor material in the opening, in the second dielectric layer Forming a second electrical conductor on the electrical layer and forming an electrical connection between the second electrical conductor and the first electrical conductor, the amount of electrical resistance material being used to substantially reduce capacitance between the electrical conductors and increase electrical conductors The high frequency resistance in the electrical connection. According to another aspect of the present invention, a circuitized substrate is provided, which preferably includes a dielectric layer, is positioned on the first dielectric layer, and includes an opening: a first electric body opening in a Susie County The 'inside ★ number of resistor materials are generally positioned at the sound: the second dielectric layer on the resistor material 'the second conductor positioned on the second dielectric layer, and the second and the second The predetermined amount of resistor material of a conductor, the capacitance between the bodies, and the first and second reductions - and the second conductive high frequency resistance. According to another aspect of the present invention, in an electrical connection between a conductor and a conductor, the sub-assembly includes: a dielectric layer on the second layer of the substrate and including an opening therein: Standing on the first-dielectric resistor material, substantially positioning the material two-two-on=inner-quantity electric two-dielectric layer, and positioning the second electric conductor on the first-conductor layer on the resistor material in the monk And the electrical connection between the second and the symplectic body, which - substantially reduces the capacitance between the first and the "resistor material for the body and increases the first - 盥 131317.doc • 30 · 200908828 two conductive A high frequency resistor in the electrical connection between the bodies, and at least one of the electronic components is positioned on and electrically coupled to the circuitized substrate. [Embodiment] This is a better understanding of the present invention, as well as additional and other objects, advantages and features. Similar figure numbers are used in the figures to identify similar ones in the drawings: 70. The term &quot;circuitized substrate&quot; as used herein is meant to include a substrate having at least one (and preferably a plurality) of dielectric layers and at least one (and preferably a plurality of gold conductive layers). Examples include Epoxy resins such as fiberglass reinforced (some of which are referred to in the art as &quot;FR_4&quot; dielectric materials), polytetrafluoroethylene (Teflon), polythenimine, polyamine, A structure made of a dielectric material of a cyanate resin, a photoimageable material, and other similar materials, wherein the conductive layers are each a metal layer (eg, power, signal, and/or ground) comprising a suitable metallurgical material such as copper. Other metals (e.g., nickel, aluminum, etc.) or alloys thereof may be included or included. Other examples are described in more detail herein below. Examples of such circuitized substrates as described above include printed circuit boards (or cards) and wafer carriers. The teachings of the present invention are also applicable to so-called &quot;flexible&quot; circuits that use dielectric materials such as polyimides, and circuits that use ceramic or other non-poly character dielectric layers, one of which An example is A so-called multilayer ceramic (MLC) module having or having a semiconductor wafer mounted thereon. The term &quot;electronic assembly is at least one circuitized substrate as defined herein and at least one electrically coupled thereto And forming a combination of electronic components 131317.doc-31.200908828 of the assembly. Examples of such assemblies are known to include a wafer carrier that includes a semiconductor wafer as an electronic component, the wafer being typically positioned on a substrate and Interspersed with or used with cloth, wires (such as pure germanium) on the outer surface of the substrate—or multiple vias that are coupled to the inner conductor. Perhaps most well known, this generally has a number of such external electronic components (including possible One or more wafer carriers) and a conventional printed circuit board (PCB) that is pure to the internal circuitry of the PCB and/or pure to each other. As used herein, the term &quot;electronic component,&quot; means, for example, a semiconductor wafer and the like. An assembly adapted to be positioned on an outer conductive surface of the substrate and electrically coupled to the substrate to transfer signals from the component to the substrate, the signals being transferable to the substrate Components (including components that are also mounted to the base) and other components (such as those components of the larger electronic system in which the substrate forms part of it). As used herein, the term &quot;information processing system,&quot; Designed to calculate, classify, 'process, transmit, receive, capture, generate, convert, store, display, perform, measure, detect, record, reproduce, dispose of, or use any form of information, intelligence, or information. An aggregate of any tools or tools for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc. These systems typically include or as a PCB, wafer carrier, etc. A component thereof, for example, a commonly used PCB includes a plurality of various components mounted thereon, such as a wafer carrier, a capacitor, a resistor, a module, and the like. One such pCB can be referred to as a &quot; main board, and various other boards (or cards) can be mounted thereon using suitable electrical connectors. About fifty terms micron particles mean "particles having an average size of about one micron (〗 〖Nano) to 131317.doc -32 - 200908828 micron (5_0 nm). The term "nanoparticles" as used in the meaning of particles having an average size of about one micron (1 - nanometer). (Materials used to form the right #h,, n, 卩4 as defined herein are understood to include powders having micro-unparticles and/or "nanoparticles" as part of them.). The term "screen printing" is used broadly to mean screen printing and stencil printing methods as is conventional in the art. For example, use _g # ' to make a screen or template for hunting. Ink, conductive composition, etc.) As used herein, the term &quot;涵7丨"立田田 。. Holes, each s month, is also commonly referred to in the industry, with a surface of usually 1 substrate to a predetermined distance therein Port; referred to as &quot;internal vias, which are vias or ports that are positioned inside the substrate and are typically formed in one or more inner layers β, which are then laminated to other layers to form the final structure; Also known as &quot;mine through hole&quot; (also known as PTHS), its f often penetrates the entire thickness of the substrate. All of these various openings are formed through an electronic circuit m of the substrate through which f-including or -" electrical layers (9) such as mineral copper are typically formed using mechanical drilling or laser ablation.

Ht ' provides a layer of dielectric material 1}. The dielectric material of layer u may be selected from the materials listed above and in the oligo-glass reinforced epoxy (&quot;FR4") material. At least one electrical conductor 13 is on top of layer 11. 'Preferably copper or copper alloy. In one embodiment, the conductor 13 is formed by bonding (e.g., laminated in the form of a solid sheet using conventional PCB processing) to a larger sheet material of layer li and subsequently subjected to Known photolithography in the PCB industry to ultimately define the configuration of the conductor. In short, in this process, light 1313l7.doc -33- 200908828

Blocking, patterning, and developing (removed in selected locations). A surname (such as copper chloride) is then applied to the exposed surface and the material (4) is removed. In the example shown in FIG. 1, the conductor 13 includes an opening 15 formed therein (preferably by the I), but may be any other acceptable group, including a plurality of openings and adjacent signal lines. , padding, etc. Alternatively, the conductor 13 may be formed by a conventional sputtering operation in which a seed layer is typically provided, after which at least one conductive layer is sputtered thereon. In such embodiments, layer u can have from about one mil to about twenty mils (one mil is one thousandth of a thickness) and conductor 13 can include from about 0.2 mils to about 2.5 mils. The thickness of the ear. As will be understood hereinafter, the conductor 13 forms part of the circuit of the invention. More specifically, the tongue, wherein the conductor having the opening 15 can be described as a "anti-pad", which means a signal conducting member (eg, plated through) The holes, as defined in more detail below, will pass through the opening and are not in direct electrical contact with the conductor. The next step after the second dielectric layer 17 (Fig. 2) is fixed on top of the conductor 13 is an optional step and involves processing the conductor 13 The upper surface enhances the adhesion of the dielectric layer 17 to the surface of the conductor. To achieve this, it is preferred to subject the exposed upper surface to an oxide (or oxidation) replacement process. A good example of this process involves exposing the conductor to a so-called &quot;;BondFilm&quot; solution, which is currently available on the market under the name Atotech Deutschland GmbH. 'This is an international company with US office address 1750 Overview Drive, R〇ck mu, s〇uth Carolina. BondFilm solution main package Three components: 〇) sulphuric acid; (2) hydrogen peroxide and (3) copper, and additional At〇tech DeutschUnd GmbH exclusive components. As stated, the process is also known as the oxide replacement process' means that it does not cause An oxide layer is formed on the treated material. For example, 131317.doc -34- 200908828 5 'The surface of the conductor 13 is always in the meandering and BondFilm process' after the mean square (RMS) roughness (standard measurement) The value of χ) is about 0.6 microns and the peak is from about 1.2 to about 2.2 microns. B〇ndFiim 裎 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 12 seconds period. As part of this treatment, the surface of the conductor is first cleaned and degreased, followed by a slight surface _. Finally, a thin organic coating is applied. In an example, the thin organic coating is benzotriene and has a thickness of from about 矣 (AngStr〇m) to about 5,000 angstroms. The thin coating remains on the outer surface of the conductor during subsequent processing. Because the Straight 〇 〇 U horse is so embarrassing, it is not shown in the drawing. Other examples of alternative oxide processes that can be used in the present invention are known in the art and are not considered to be further described.

L

The first dielectric layer 17 is now preferably applied in the form of a solid layer and using conventional lamination methods known in the manufacture of pCB. Layer 17 is preferably a photoimageable material, several examples of which are known in the art. An example is ASMDF (Advanced Solder Mask Dry Film). The composition may comprise a solids content of from about 85 to about 9%, the solids comprising about 27% PKHC (phenoxy resin), 41% Epirez 5 1 83 (four deserts A), 23% Epirez SU-8 (octafunctional epoxy bisphenol A formaldehyde novolac resin), 54% UVE 1014 photoinitiator; 0.07% ethyl violet dye; 0.03% FC 430 (3M fluorinated polyether non-woven) An ionic surfactant) and about 4% Aerosil 380 (amorphous cerium oxide from Degussa Corporation described above) to provide a solids content. There is from about 11 ° / ◦ to about 1 3.5 ° / of the total photoimageable dielectric composition. Solvent. This composition is known in the art and is believed to require no further description of 131317.doc-35-200908828. As mentioned, several photoimageable materials can be used, and the invention is not limited to the above. The dielectric layer taught herein can generally be from about 2 mils to about 4 mils thick, but can be thicker or thinner if desired. After bonding to the upper surface of the conductor 13, it is photoimaged (or photopatterned) and developed to reveal the desired circuit pattern, in this case at least one opening 19 of the same diameter as the opening 15 immediately below it. (image 3). The opening 19 may actually be slightly larger than the opening 15 of the thin (about 〇2 mil) conductor (13). The dielectric material forming layer 17 can be supplied by curtain coating "screen coating" or it can be supplied as a dry film. The finalization of the photoimageable material provides a burgeoning dielectric substrate on which the f-circuit (e.g., signal line or profile) can be formed. The following is the tomb of the female. The moon I 3 is no longer necessary, and it is not necessary to form the circuit at this time, but it is better to add a third dielectric layer (defined below) before the additional circuit. In one example, layer 17 can be two mils thick. In Figure 4, 'deposit a certain amount of resistor material 21 in alignment openings 15 and 19' is preferably screen printed (which may include stencil printing as well as conventional screen printing as defined above) . Several examples of this material are detailed below (see seven examples below). Briefly, the resistor comprises a polymeric resin (e.g., a cycloaliphatic epoxy tree containing - or a metal powdered metal material, each of which == • bismuth particles and/or micron sized particles. In the examples below) In the first case, the electric device material 2! can only contain (4) (4) in the resin mixture, and in the case of f, only copper powder can be used in the resin. In the last five examples, various combinations of copper, graphite and silver Included in the resin. Examples illustrate how a different resistance can be provided in the most formed resistor. The present invention can provide from about U0 milliohms Ω Ω) to about 12 mega ohms (for pcB and wafer carrier 131317) .doc •36· 200908828 Resistor of the typical resistance range of the resistor in the application). It will be appreciated that the present invention is capable of providing a resistor having a resistance indication outside the above range' and the invention is not limited to this range. It should also be understood that the invention is not limited to relying solely on silver as a metal, as other possibilities are also possible. In the following examples, the metal powders used each have particles having a size of from about 0.07 microns to about five microns. Here, the invention is also not limited to the same size and area. It will be appreciated that one purpose of the metal component of the resistor composition 21 is to produce a resistor comprising the resistor n material as part of the formed circuit line. It also ensures improved electrical properties of the resistor (eg reduced dielectric loss, improved temperature and frequency stability, etc.). Another purpose of the metal component is to produce a coefficient of thermal expansion (CTE) of the final mixture such that the cte of the mixture more closely approximates the final (laminated) substrate and the cte of the conductor bonded thereto. Therefore, the addition of a metal component to the mixture is an extremely important feature of the present invention. An important advantage of these closer CTE values is the reduced stress in the resulting laminate substrate during substrate operation. Most notably, as explained above, the resistor material, when positioned as shown and thus part of the internal circuitry of the circuitized substrate, is used to substantially reduce a pair of electrical conductors (the conductors 13 are in the electrical conductors) The capacitance between one of the two) increases the resistance in the electrical connection formed between the two electrical conductors. Further explanation is provided below. Significantly, the metal powder used herein is not calcined, and as such, has a small size that enables effective formation of a resistive structure, including when used in an opening in a dielectric as shown in FIG. The resistive structures have a small scale such that high density circuit patterns including their circuit patterns having vias of the type defined above are formed. The vias can have a very small straight shape (in the example order, as small as one to two mils) to thereby ensure such miniaturized, high density circuit patterns. As indicated, this miniaturization is considered to be extremely important relative to the design of many current circuitized substrates. In effecting printing of the resistor material 21, a screen or stencil (not shown) is positioned over the layer and the material is forced through there, for example using a squeegee or blade. The material h substantially fills the openings 15 and 19 and Thus physically contacting the respective ends of the conductors 13. In an embodiment, the resistor material 21 may be deposited in a paste form. However, it is also possible to apply a liquid material 21 through a suitable nozzle (not shown). Dispensing to fill the openings 15 and 19. The use of an ink jet printing apparatus having nozzles associated therewith can be used for this. After dispensing, the resistor material 21 is now "B-staged" (in such as conventional convection) The oven is heated in a spring oven to raise it to a state that is harder than when dispensed. In the example of I, material 21 can be heated to a temperature of about 19 degrees Celsius for a period of about two hours. The resulting metal particles of the resistor material 21 thus formed may thus comprise an oxide coating thereon or may comprise a coating of a polymeric resin material forming part of the composition as defined. Thus, the particles do not form a single continuous conductive path through the resistor material 21. In the embodiment shown in Figure 4, both openings 15 and 19 have an inner diameter of about sixteen mils and a total of about 0.09 milligrams of resistor material 21 is deposited therein. In another example, material 21 can comprise a polymer resin as defined herein and a mixture of at least one metal component as defined above and at least one high surface area ceramic component, the high surface area ceramic component The rice granules have a particle size generally ranging from about 0.01 microns to about 10 microns and a surface area ranging from about 1 to about 1500 square meters per 131317.doc -38 to 200908828 grams. Another suitable resistor material for use herein is a material comprising a mixture of a polymer resin as defined and at least a metal coated ceramic component having particles substantially Particle size in the range of about 1 micron to about working meters. Thus, in this embodiment, it is understood that the ceramic component is coated with a metal component to produce a mixture of particles comprising a combined structure of the two components. In another embodiment, the resistor material may comprise a poly-resin of the type defined herein and at least one oxide-coated metal component as defined above. The oxide-coated metal component particles preferably have Particle size generally in the range of from about Η to about 10 microns. Another acceptable resistor material for use herein includes a polymeric resin as defined herein and at least one metal component and at least one transparent a mixture of oxide components. The particles of the 'transparent oxide component in the mixture preferably comprise a particle size substantially in the range of from about 〇·〇! micron to about 10 micrometers and from about 3,000 to about (10) square gram per gram. In addition, a resistor material having the unique characteristics defined herein may comprise a polymer resin as defined herein and a mixture of at least one metal component and at least one doped sub-salt salt component. In the mixture, the nanoparticle doped with the sub (tetra) salt component preferably has a particle size substantially in the range of from about 0.01 micron to about 1 micron and: : = about 1 to about Η). Surface area in the square meter range. For the above embodiments in which: = one less metal and the at least one (four) part is iron :::: ceramics, the mixture may additionally comprise a carbon i untreated component. The resistors may be of the form of polymer thick film resistors or ring-metal (gold, steel, copper-tin) coated polymer sphere-based resistors π 131317.doc -39- 200908828. Sputtering can also be used to deposit resistor materials using physical masks. Some of the typical metal alloys of these sputter resistors include Nip (nickel chrome), NiCrAlSi (nickel chrome, aluminum, tantalum) and TaN (tantalum nitride). Sputter and printed resistors can also be used in combination. For example, a portion of the resistor material is sputtered on top of the printed portion of the resistor material. In Figure 5, a third dielectric layer 23 is positioned over layer 17 and the currently partially cured resistor material 21, the material The layer 23 is sufficiently cured to fully support the layer 23. The layer 23 can be any of the above dielectric materials, including a photoimageable material such as layer 17. In the preferred embodiment, layer 27 has conventional &quot;FR4&quot; enhancements The resin material is applied using a conventional PCB lamination process. During the lamination, the process temperature is also used to ultimately (fully) cure the resistor material. In one example, the temperature range can be from about 18 〇t to Approximately 38 〇. The lamination pressure in the range of 2 psi (Ps"·) to 2500 psi can be successfully used as part of the lamination. However, it should be understood that the material 21 can be positioned at layer 23. Before

Completely cured, for example, heated to a higher temperature than used to increase it to &quot;B stage&quot; as described above. The invention thus accommodates both possibilities and increases the versatility of the method described herein. In one example, layer 23 is four mils thick in the case where layer 17 is not used, layer 23 will actually serve as the dielectric layer. Although layer 23 is used as shown in Figures 4-7, layer 17 may The term "intermediate" is an electrical layer, meaning that it is between the initial dielectric layer and the dielectric layer 23 used to cover the resistor material. Further, in Fig. 5, a plurality of conductors 29 are required to be formed on the layer 23, and the operation requirements of the products are determined as signal lines or linings. Conductor 2 9 forms a circuit pattern on layer 23 that may or may not be part of the circuitry associated with the resistors formed as defined by 131317.doc.40-200908828 herein. The circuit pattern is shown here to illustrate the need to add this circuit capability at this point in the process. In the example, the circuit is formed from the layer to the copper of layer 23 and is subsequently subjected to conventional photolithography as used above. Other methods are of course possible 'including the dead key, and it is considered here that no further description is needed. In this example the 'per-conductor has a thickness of about K5 mils and is formed of copper or a copper alloy. For ease of description, the conductors may also be referred to herein as bodies. - In Fig. 6, another dielectric layer 3 is formed on the conductor 29 and formed on the upper surface of the layer η. Layer 30 is preferably the &quot;FR4&quot; material described above, but may be any of the dielectric materials referred to above&apos; including photoimageable materials. In the case of &quot;FR4&quot; material, layer 30 is deposited as a single layer and bonded to the proper location using conventional lamination. In the example - the pressure in the range of 2 ah / square leaf (psi) to 25 〇〇 ^ and about 18 (TC to about Bay temperature can be used as part of the lamination process. Notably, these high temperatures In the case of an unfavorable material, (4) may be four mils thick. After successful bonding of the layer 31, '帛 related to the first electrical conductor 13', the electrical conductor is formed on the layer 3〇. It is preferred to form the conductor using conventional photolithographic processing after the conductor of a single sheet (preferably a copper or copper smear layer). It will of course be appreciated that a plurality of such conductors 31 and other conductive elements (such as signals) may be formed. Wire or pad) 'all of which are used to form part of a single layer circuit at this location in the present invention. Conductor 31 can be (10) ear thick and as shown on the resistor; material 21. Although two dielectric layers 23 and 30 Described as being positioned on resistor material 21, 131317.doc 41 200908828

In a broader aspect of the invention, however, only one dielectric layer needs to be positioned. In addition, it is now also possible to describe the combined layers as an integral layer because layers 23 and 30 may be "combined" along their opposite edges due to the relatively high heat and force associated with the lamination process. It is also possible to omit layer 23 in the present invention and instead use layer 30 alone as the second dielectric layer (i.e., the layer on which the second conductor of the present invention is present). In this regard, layer 23 can act as a "second" dielectric layer in which one of conductors 29 forming the second conductor and layer 30 (and conductor 31) are omitted altogether. Finally, as also mentioned above, if used, the dielectric layer 17 is also referred to as an intermediate dielectric layer which is formed after the formation of the conductor 13 (including its opening 15) and prior to positioning the dielectric layer 23. The structure of Figure 6 is now subjected to a drilling operation in which at least one opening 35 is formed as shown. The opening 35 can be formed using mechanical or laser drilling, one of which uses an Ng-YAG laser. In one embodiment, the opening 35 may have a diameter of eight mils and the entire thickness of the structure through Figure 6 (and now Figure 7). The opening passes through the top conductor 31 and passes through the opening 15 in the initial conductor turns 3, thereby not directly contacting the inner wall of the conductor 13. Significantly, the opening directly passes through (and thus engages) the resistor material 21. After drilling, the inner wall of the opening is preferably metallized using conventional plating operations for electroplating PCB vias. A preferred electroplating method for forming a known PTH can be used herein where the coating of the first-thin layer, followed by the application of a thin layer of electrodeless copper and finally the thicker layer of electrolytic copper, results in formation on the inner wall of the opening A thin layer 37 (e.g., about 5 mils thick). As noted, other metallurgy and thicknesses are possible. The conductive material is thus provided from the top conductor 31 down through the substrate to the resistor material Μ, and thus to the electron path of the other conductor I3 opening and plating the conductive material thereby 131317.doc -42 - 200908828 cup in Figure 7 The full thickness of the through structure is used in the examples. The base road control therefore includes a resistor as part of it. As will be appreciated, the invention as defined by the invention can result in the formation of a number of such circuits, and this early circuit is early-resistor. In fact, if the present invention is provided, more than one resistor can be provided for each circuit. The circuit path (and structure) has particular advantages, especially when focusing on the performance degradation due to the discontinuity of the signal path of the over-circuit (described above) as a circuit that always focuses on the high-density circuit pattern as taught herein. Also #者. In the circuit of Fig. 7, there is a use of a material (a resistor material has the advantage that the material has a right-handed, lower dielectric valley than the dielectric material (layer 17) it replaces) thereby reducing the conductor p2 ·|々Ba, etc. The capacitance in the circuit between the bodies 13 and 31. In an example, the capacitance of the household (indicated by the size in Figure 7) c&quot; is measured as low as about 〇.〇5 picofarad (picofarad) to about 微22 picofarads. This design also reduces: the signal energy reflected by the open end of the via 2 (the other end of the dielectric layer u). Significantly 'and as defined by the examples below It has been shown that the resistance value is carefully chosen to extract very little energy from the signal passing through the circuit. For example, a 50 ohm impedance signal line (path) is not affected by parallel 〇〇, 〇〇〇 ohms influence 'but because The through hole is open at the lower end, so the improper energy along the through hole is affected by an additional 10 〇, and the 〇〇〇 ohm is strongly affected. Therefore, most of the signal energy in the line foot (the last part) passes through the resistor. Material instead of "opening back" from the open end. Therefore, by adding The addition of a resistor material and making it part of the circuit of the present invention reduces performance degradation. Therefore, data transfer is faster in a circuitized substrate than in a similar structure without a resistor. In addition to operation to achieve accurate deposition, careful and precise selection of the resistance values of this circuit is enhanced by the use of 131317.doc -43-200908828 including nanoparticle and/or microparticles as part of the resistor material. These advantages may arise in the absence of significant additional cost to the process of creating the invention. The teachings herein further understand that internal (or embedded) resistors formed within the substrate are particularly capable of being in various circuit combinations. 'Or such resistance is provided only in a single circuit. It is to be understood that the examples described and illustrated herein are not intended to limit the invention, as there are many other possibilities and are well-known to those skilled in the art. Further, the present invention thus represents a significant advancement in the art. Figure 8 shows an example of the structure defined above 'by digitization The total amount of the test becomes the wafer carrier' and the total number represented by the numeral 47 becomes pcB. Each can include - or a plurality of internal resistors of the above defined type as part of the PCB and the wafer carrier assembly. Produced and sold by the assignee of the present invention. In the embodiment (assembly) of Figure 8, a plurality of solder balls 51 (preferably a conventional tin-lead composition) are used to mount the wafer carrier on and In conjunction with its electrical coupling, the wafer carrier 45 in turn has a semiconductor wafer 49 positioned thereon and electrically coupled to the carrier using a second plurality of solder balls 53 (also preferably known as tin, compositions). The two electron assemblies shown in Figure 8 are the carrier-wafer assembly and the other is the coffee carrier assembly (the basin inherently includes the wafer 49). The structure of FIG. 8 may also include heat sinks as described in the art, such as the use of a conductive paste and wafer 49, and which define (4) (4) 45 by a suitable gap (not shown using a sealant material (not shown)) It is also within the scope of those skilled in the art to substantially coat the wafer and if the use of the sealant material may eliminate the need for heat sinks. The closure material may also surround a lower plurality of closures. Solder balls 51 and 53. Even additionally, it is within the scope of the invention to use conventional wire bond coupling wafers 49 in which a plurality of thin wires (not shown) are corresponding conductor linings on the wafer conductor sites and the underlying substrate. The solder balls 53 are used between the pads, and the interconnect contact sites (not shown) on the underside of the wafer are interconnected with corresponding pads 61 on the carrier 45. Similarly, the solder balls 51 make the carrier The liner 63 on the lower side is interconnected with a liner 65 on the upper surface of the PCB 47. The liners are typically copper or copper alloys and are known in the art. In the particular example shown in Figure 8, One or more of the upper pads 61 may be coupled to the corresponding one of the lower pads 63 Forming individual circuit paths therebetween. One or more of the circuit paths may include one or more of the resistors as taught herein. An electronic assembly including a circuitized substrate of the type formed herein may be used in This technology is called &quot;Information Processing System,&quot; (defined above). Examples of such systems include personal computers, host computers, and computer servos.

Device. Other types of f-processing systems known in the art of this type may also utilize the teachings of the present invention. "A circuitized substrate, as formed in accordance with the teachings herein, including one or more internal resistors as taught above, may be used, for example, in the form of a "motherboard" or in the form of one or more individual pCBs. Various combinations of materials and methods of forming a resistor H for forming resistors in accordance with various aspects of the present invention are provided. These are to be understood as merely examples and not limiting the scope of the invention. As is apparent from the examples, The teachings herein achieve a relatively wide range of resistance values. Example 5 provides a resistor for microparticles and 13 and 7 provides resistors based on nanoparticle. Example 1 will be fifty grams ( Gm) cycloaliphatic epoxy resin (for example, under the product name &quot;ERL-421I&quot; sold by Union Carbide Corporation, Danbury, CT) with about 50 gm hexahydro-4-methylphthalic anhydride and 0.4 grn n,N-dimethylbenzylamine is mixed. The mixed solution is stirred for about ten minutes to ensure uniform mixing. It will be available from Degussa Corporation (enterprise location at 379 Interpace Parkway, Parsippany, NJ) 50 Gm silver powder was added to the 7.5 gm mixed solution and formed into a printable paste. The silver powder included particles having an average size of about five microns. A layer of the paste material was then printed onto the copper substrate. The layer was then placed at about 19 degrees Celsius ( t) The electrical resistance of the curing resistor (3 Å long and 0.003 吋 cross-sectional area) after curing for about two hours is measured to be about 1 20 milliohms. 50 gm, ERL.4211, cycloaliphatic epoxy The resin is mixed with about 5 〇 (tetra) hexanitro- 4-methylphthalic acid liver and 〇.4 gmN, N-dimethyl amide. The mixture is mixed for about ten minutes to ensure uniform mixing. (4) (4) Adding powder to .5 The gm is mixed and formed into a printable paste. Steel powder package = granules. A layer of the paste material is printed onto the copper base. "The 5 kel layer is cured at about (10) for about two hours. The resistance of the curing resistor (3 leaf length and 〇〇〇3 square megameter called ... cross-sectional area) is measured to be about 120. Example 3 131317.doc -46- 200908828 50 gm &quot;ERL-4211&quot; cycloaliphatic epoxy The resin was mixed with about 5 g of hexahydro-4-methyl phthalic anhydride and 0.4 gm of N,N-dimethylbenzylamine. The mixed solution was stirred for about ten minutes to ensure uniform mixing. 38 gm of copper and 12 § 111 silver powder were added to the 7.5 gm mixed solution and formed into a printable paste. The average particle size of the copper and silver powder ranges from about four to about five microns in diameter. A layer of the paste material is printed onto the copper substrate. The layer was then placed at approximately 19 Torr. 〇下 f

Cured for about two hours. The resistance of the curing resistor (3 Å long and 〇〇〇 3 吋 吋 cross-sectional area) was measured to be about 70 MΩ (ΜΩ). Example 4 50 gm of 'ERL-4211&quot; cycloaliphatic epoxy resin was mixed with about 5 〇 hexahydro-4-methylphthalic anhydride and 〇.4 gm N,N dimethylbenzylamine. The mixed solution was stirred for about ten minutes to ensure uniform mixing. 5 (tetra) copper and Μ W silver powder were added to the 7.5 gm mixed solution and formed into a printable paste. The average particle size of the copper and silver powder ranges from about four to about five microns in diameter. A layer of the f* agent (4) is printed onto the copper substrate. The layer was then cured under about two hours. The resistance of the curing resistor (4) and the Q (10) square to cross-sectional area is measured to be about 4 〇〇 milliohms (ΙηΩ). 50 gm,, ERL-4211, cycloaliphatic epoxy tree was mixed with about six gas _ heart methyl phthalic acid anhydride and 〇 4 gm N, N dimethyl amide. The mixed solution was mixed for about ten minutes to ensure uniform mixing. (4) (4) Copper coins (4) Silver powder is added to a 7.5 gm mixed solution and formed into a printable paste. Copper and silver powder: The average particle size is in the range of from about four to about five microns in diameter. A layer of the paste material is printed onto the copper substrate. The layer was then cured for approximately two hours at approximately 131317.doc 47·200908828. The resistance of the curing resistor (3 吋 long and 〇〇〇 3 吋 吋 cross-sectional area) was measured to be about 25 ohms (4)). Example 6 A 50 gm "ERL_4211" cycloaliphatic epoxy resin was mixed with about 5 〇 gm hexahydro-4_f phthalic anhydride and 〇·4 gm N,N dimethylbenzylamine. The mixed solution was mixed for about ten minutes to ensure uniform mixing. Will be able to talk about self-grouping,

Ward HiU, Massachusetts 4 fluorinated graphite and available from NanoTech, Inc., North IndustHal j (4) Only 5.4 gm silver nanopowder (with a D9 〇 particle size of 7 μm) is added to the Lugua mixed solution and formed into Printable paste. A layer of the paste material is printed onto the copper substrate. The layer was then cured at about 2 Torr (rc for about two hours. The resistance of the curing resistor (3 yoke and 〇 (10) 3 忖 cross-sectional area) was measured to be about 90 ohms (Q). Example 7 50 gm "ERL_42u&quot; cycloaliphatic epoxy resin is mixed with about "gm hexahydro-4-(J-methylphthalic anhydride and G.4(tetra)n,n-dimethylammonium. Mix the mixed solution for about ten minutes. To ensure uniform mixing. Add fluorinated graphite from Alfa A (4) and 4 gm silver nanopowder (with D9 〇 particle size of 0.07 μm) available from Cima Nan〇Tech, Inc. to the 7 5 morphine solution. Formed as a printable paste. A layer of the paste material is printed onto the copper substrate. The layer is then cured at about 2 Å for about two hours. The curing resistor (3 f long and G.GG3 square 忖 cross-sectional area) The resistance of the ) is measured as approximately dead ohms (ΜΩ). The following table summarizes examples of some metals used in combination with the same amount of polymer material to form resistors of the type I31317.doc -48- 200908828, and read Take the resulting resistance across the resistors. Table - Resistance as a function of silver/copper ratio. Metal polymer resistor size resistance 50 gm silver 7.5 gm 3 inch length and 0.003 square inch cross-sectional area 120 ηιΩ 45 gm silver + 5 gm Cu 7.5 gm 3 inch length and 0.003 square inch cross-sectional area 400 ιηΩ 30 gm silver + 20 Gm Cu 7.5 gm 3吋 length and 0.003 square inch cross-sectional area 25 Ω 12 gm silver + 38 gm Cu 7.5 gm 3吋 length and 0.003 square inch cross-sectional area 70 ΜΩ 50 gm Cu 7.5 gm 3吋 long and 0.003 square 吋 horizontal The cross-sectional area is 120 ΜΩ f, and thus a circuitized substrate having one or more internal resistors as part of it has been shown and described, which can be formed using many conventional PCB methods to thereby reduce the cost associated with its fabrication. The substrate is readily adaptable for use in an electronic assembly in which one or more electronic components, such as semiconductor wafers, can be positioned and coupled thereto. Several examples of resistor materials have also been defined that can be positioned between two adjacent conductors. Between the portions of the circuit line to form the circuits of the substrates. Most notably, as shown by the above examples, the present invention provides for changing the conductor between the conductors by varying the resistor material composition. Opportunity of Resistance. This latitude greatly assists the circuit designer in meeting the changing operational requirements. While the presently described preferred embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that Various changes and modifications are possible in the context of the scope of the invention as defined by the scope of the invention. The invention as defined herein is capable of transmitting conventional and high speed (.frequency) signals, the latter being in the order of about one billion bits per second to about A rate of 10 billion bits per second while substantially preventing impedance cracking. It can also be produced using many conventional PCB methods 131317.doc -49. 200908828 to ensure cost reduction and ease of manufacture. Perhaps more significantly, the present invention is capable of ensuring miniaturization of circuit patterns that are considered to be extremely important as for many current design requirements. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1-7 is a greatly enlarged side elevational view illustrating the basic steps of fabricating a circuitized substrate including at least one internal resistor in accordance with an embodiment of the present invention; and FIG. 8 is a view of the present invention. A partial perspective view of an electronic assembly of one embodiment in partial cross-section, the assembly being suitable for use with one or more circuitized substrates of the present invention. [Key Symbol Description] 11 13 15 17 19 21 23 27 29 30 31 35 37 131317.doc Dielectric material layer Conductor/conductor opening Second dielectric layer Opening resistor material/Resistor composition Third dielectric layer Conductor Dielectric layer Second conductor/conductor/layer opening thin Layer-50-

Through Hole Wafer Carrier PCB Semiconductor Wafer Solder Ball Solder Ball Upper Liner Lower Liner Pad Size -51 -

Claims (1)

200908828 X. Patent Application Range: 1. A circuitized substrate comprising: a first dielectric layer; a first electrical conductor necessarily located on the first dielectric layer, the first electrical conductor including an opening therein; a certain amount of resistor material within the opening in the first electrical conductor; a second dielectric layer on the plurality of resistor materials generally positioned within the opening in the first conductive body; a second electrical conductor that is located on the second dielectric layer; Electrical connection between the two electrical conductors and the first electrical conductor, the certain number of electrical resistance devices in the opening of the first electrical conductor to substantially reduce the first electrical conductor and the second electrical conductor The capacitance between the bodies increases the high frequency resistance in the electrical connection between the first electrical conductor and the second electrical conductor. 2. The circuitized substrate of claim 1, wherein the first dielectric layer comprises a fiberglass reinforced epoxy resin, polytetrafluoroethylene, polyimine, polyamine, cyanate resin, polyphenylene ether. An organic dielectric material of a group of polymeric materials consisting of a resin, a photoimageable material, and combinations thereof. 3. The circuitized substrate of claim 3, wherein the first electrical conductor and the second electrical conductor each comprise a copper or copper alloy material. 4. The circuitized substrate of claimant, further comprising an intermediate dielectric on the first electrical body; wherein 兮_坌 includes a second:; the electrical conductor having the opening &quot; opening The number of resistor materials also set you 131317.doc 200908828 in the second opening in the intermediate dielectric layer, the second dielectric layer is directly positioned on the intermediate dielectric layer and located in the certain number of resistor materials on. 5) The circuitized substrate of claim 1, wherein the quantity of electrical resistance material comprises nanoparticle. 6. The circuitized substrate of claim 1 wherein the quantity of electrical resistance material comprises microparticles. 7. The circuitized substrate of claim 1, wherein the electrical connection between the second electrical conductor and the first electrical conductor comprises a through hole. 8. The circuitized substrate of claim 1, wherein the quantity of electrical resistance material comprises an epoxy material and a quantity of metal particles therein. 9. The circuitized substrate of claim 8, wherein the metal particles are copper and/or silver. 10. The circuitized substrate of claim 8, wherein the particles are nanoparticle. 11. The circuitized substrate of claim 8, wherein the particles are microparticles. An electronic assembly comprising: a circuitized substrate comprising a first dielectric layer, a first electrical conductor necessarily located on the first dielectric layer, the first electrical conductor including an opening therein, a certain amount of resistor material in the opening in the first conductive body, a second dielectric layer on the certain amount of resistor material necessarily located in the opening in the first conductive body, necessarily located in the second a second electrical conductor on the dielectric layer and an electrical connection between the second electrical conductor and the first electrical conductor, the certain amount of resistor material in the opening in the first conductive body is used Generally reducing the capacitance between the first electrical conductor and the electrical conductor of the first 131317.doc -2 - 200908828 and increasing the high frequency resistance in the electrical connection between the first electrical conductor and the second electrical conductor And at least one electronic component positioned on the electrical circuit substrate and electrically coupled thereto. 13. The electronic assembly of claim 12, wherein the at least one electronic component comprises a semiconductor wafer and the circuitized substrate comprises a wafer carrier substrate. 14. The electronic assembly of claim 12, wherein the circuitized substrate comprises a printed circuit board. 131317.doc