JPS60130854A - 半導体集積回路 - Google Patents

半導体集積回路

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Publication number
JPS60130854A
JPS60130854A JP58238794A JP23879483A JPS60130854A JP S60130854 A JPS60130854 A JP S60130854A JP 58238794 A JP58238794 A JP 58238794A JP 23879483 A JP23879483 A JP 23879483A JP S60130854 A JPS60130854 A JP S60130854A
Authority
JP
Japan
Prior art keywords
layer
wiring
integrated circuit
layers
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58238794A
Other languages
English (en)
Inventor
Kunio Hoe
邦夫 保江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58238794A priority Critical patent/JPS60130854A/ja
Publication of JPS60130854A publication Critical patent/JPS60130854A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は多層積Ｉ一構造状に半導体回路を構成する３次
元半導体集積回路｛二関する。
〔従来技術とその間照点〕
従来の半導体乗積回路は半導体基板表面仁処理をほどこ
し各種のトランジスター素子等を平面状に設置、配線す
ることにより形成される。従ってこのような平面状、即
ちｚｖｃ元構造を持つ回路（二あっては、その回路規模
が増大した場合チップ向積を増大すること６二より対処
するわけであるが。
これ１二よりウェハーあたりのチップ数が減少しぶどま
りの感化をまねく。またζのような大面積チップ上ｉ二
大規模回路を実現するＣニあたり、分割領域ζユわけて
設計するため分割領域間の配線のための領域がチップ内
でしめる割合が増大する。従来の半導体集積回＃＆署＝
あってはこのような問題があった。
このような半導体集積回路の従来構造の持つ問照点を改
良する目的で多層積層構造を有する３次元半導体集積回
路が提案されている。即ち半導体基板表面上に形成され
た回路構造の上（＝絶縁層を介して半導体層を設け、そ
の表面上に第２層目の回路な具備し、さらにこの第２Ｎ
目の回路の上Ｃニ回様（＝絶縁層を介してｇ５３層目の
回路を設置し、以下同様に所望の、す数の回路を設置し
た立体構造の半導体集積回路である。
しかし橙から、このような従来の３次元半導体集積回路
（−あっては異なる層間の配線は各層にある回路Ｃニ垂
直な方向に絶縁層をつらぬいて設置されるため、あらか
じめ処理の段階において垂直配線部も回路パターンの中
に取り入れてｉ）かねばならない。下た何層もへだてる
よう表離れた層間の配線は非常に困ｔＩｔとなる。製作
処理技術の点からも、このような形式による異なる層間
の垂直配線σ困非をともない、信頼性が低下す゛るとい
った問題があった。さらに従来技術では外部Ｉ１０用ポ
ンディングパッドを最上層の半導体層に設けるため外部
からのショック等で破損されやすいという問題があった
。
〔発明の目的〕
本発明は上記の点（−鑑み異なる眉間の垂直配線を絶縁
層をつら怜いて設置することなく従って困難の大きい高
度な製作処理技術を使うことなく層間配線を設置するこ
とを可能（ニする多層積層立体構造を有する３次元半導
体集積回路を提供することを目的とする。さらには現行
の集積回路製作処理技術の筒中において製品（二製作し
得る構造を有する半導体集積回路を提供することをも目
的とするＯ 〔発明の概要〕 本発明（二おいては、上部の層にある回路は下部の層Ｃ
ニある回路より小さい規模となる如く、全体として四角
錐台の構成となるように各回路層を半導体基板上（二所
望の数だけ積層する。四角錐台に限ることはなく、一般
の多角錐台１円錐台等であってよい。そして異なる層間
の配線はこの層間にある他の膚や絶縁層を貫通すること
なく、各層（ヱおいて回路外周辺部Ｃニ設置された端子
位置ぽでその層内で配線し、端子間の配線は四角錐台構
造の側壁面にあたる部位に配線をほどこすととＣ：より
実現される。従って異なる層間の配線は全ての層内での
回路パターンの製作処理が終った後に金属配線等を側壁
面にある端子間に設置することにより得られる。また外
部Ｉ１０用ポンディングパッドを最下層の半導体基板上
に設けるため、外部からの力学的ショックに強い構造と
なる。
〔発明の効果〕
本発明によれば異なる層間を貫ぬく垂直配線を設けず、
四角錐台状の多層回路の側壁面上に設置された端子間の
配線接続を側壁面上で行うためその製作処理技術が製品
であり、また何層（二もわたる配線であっても製品に設
置され信頼性の低下もない。また外部Ｉ１０用ポンディ
ングパッドを最下層の半導体基板上Ｃニ設けるため強度
上信頼性の高いボンディングを得る。従って現行の半導
体集積回路製作処理技術と、半導体素子上に絶縁層を介
して半導体結晶層を構成する技術のみ（二より容易４二
実現可能な半導体集積回路の構造を得ることが出来る。
〔発明の実施例〕
以下、第１．２．３図を用いて本発明の一実施例につい
て説明する。第３図は４つの層に回路を設置し周辺部端
子を通して側壁面（二層間配線を設けた本発明の一実施
例である半導体集積回路の構造を表わす図である。第１
図は５層からなる同様の半導体集積回路の側壁面にほど
こされた異なる層の回路間の配線を示すパターン図であ
る。第２図はその断面図である。
本実流側シニよれば異なる眉間の配線が各層の内部を垂
直（二つらぬいて設置することなく、各層外周辺部の端
子を界し全体回路の側壁面にあたる部位に設けられる。
このため各／！＃における回路部は従来の処理技術（二
より製作される。低位の層の表面（二このようＣニ形成
された回路上に一様（ユ多結晶シリコンを設置しアニー
ルすることにより単結晶層を形成する技術のみがそれに
加わるわけでありそれは容易である。またこの構造の半
導体集積回路（＝あってはその構成からして何層（二も
わたる長い層間配線であっても高信頼性を保ちつつ製品
に設直し得る。
本発明は上記実施例Ｃニ限られない。例えは全体回路の
形状は四角錐台でなくても任意の多角錐台等の錐台であ
ればよい。
【図面の簡単な説明】
ｉｓ　１図は本発明の一実施例につきその側壁面（二は
どこされた異なる層間の配線を示す斜視図。 第２図はその断面図。 第３図はその一部を拡大した斜視図である。 図（二おいて、 １１・・・チップ領域（半導体基板）、１・・・第１層
目回路周辺部、 ２・・・第２層目回路周辺部、 ３・・・η′６３層目回路周辺部、 ４・・・第４層目回路周辺部、 ５・・・第５層目回路周辺部。 ６・・・配線。 ７・・・人出力（Ｉｌｏ）パッド。 代理人　弁理士　側近Ｖｌ＆（他１名）第　１　図

Claims (3)

    【特許請求の範囲】
  1. （１）　所望の論理機能を実現する半導体集積回路を３
    次元多層構造（；より構成する（＝あたり、上層は下層
    より小さい規模になる四角錐台の構成を有し、異なるノ
    ー化ある回路間の配線は各層の外周辺部Ｃニ設晶゛され
    た端子までその層内で配線し各層外周辺部の端子間を四
    角錐台の側壁面Ｃニあたる部位に配線をほどこすことに
    より結線することを特徴とする千導体集積回路。
  2. （２）前記半導体集積回路において、構成は四角錐、多
    角錐台９円錐９円錐台となるである事を特徴とする特許 集積回路。
  3. （３）外部１／０用ボンデイングパツドを最下層の半嚢
    体基板上《二設置し、上層部にある素子から上記外部１
    ／Ｏボンデイ／グパッ．ドまでの配線を上記の側壁面に
    ほどこすことを特徴とする前Ｒｔ２特許請求の範囲第１
    項記載の半導体集積回路。
JP58238794A 1983-12-20 1983-12-20 半導体集積回路 Pending JPS60130854A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58238794A JPS60130854A (ja) 1983-12-20 1983-12-20 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58238794A JPS60130854A (ja) 1983-12-20 1983-12-20 半導体集積回路

Publications (1)

Publication Number Publication Date
JPS60130854A true JPS60130854A (ja) 1985-07-12

Family

ID=17035376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58238794A Pending JPS60130854A (ja) 1983-12-20 1983-12-20 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS60130854A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522518A2 (en) * 1991-07-09 1993-01-13 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
EP1635387A1 (en) * 2004-09-09 2006-03-15 Seiko Epson Corporation Electronic device with a chip on a pedestal and method of manufacturing the same
US7023079B2 (en) * 2001-03-01 2006-04-04 Advanced Semiconductor Engineering, Inc. Stacked semiconductor chip package
SG125213A1 (en) * 2005-02-25 2006-09-29 Seiko Epson Corp Manufacturing method for electronic device
US7595222B2 (en) 2001-07-04 2009-09-29 Panasonic Corporation Semiconductor device and manufacturing method thereof
WO2011089670A1 (ja) * 2010-01-22 2011-07-28 シャープ株式会社 半導体装置及びその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522518A2 (en) * 1991-07-09 1993-01-13 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
EP0522518A3 (en) * 1991-07-09 1994-11-30 Hughes Aircraft Co Stacked chip assembly and manufacturing method therefor
US7023079B2 (en) * 2001-03-01 2006-04-04 Advanced Semiconductor Engineering, Inc. Stacked semiconductor chip package
US7595222B2 (en) 2001-07-04 2009-09-29 Panasonic Corporation Semiconductor device and manufacturing method thereof
EP1635387A1 (en) * 2004-09-09 2006-03-15 Seiko Epson Corporation Electronic device with a chip on a pedestal and method of manufacturing the same
SG125213A1 (en) * 2005-02-25 2006-09-29 Seiko Epson Corp Manufacturing method for electronic device
WO2011089670A1 (ja) * 2010-01-22 2011-07-28 シャープ株式会社 半導体装置及びその製造方法
JP5416790B2 (ja) * 2010-01-22 2014-02-12 シャープ株式会社 半導体装置及びその製造方法

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