JPS60125011A - マスタ−スレ−ブ型フリップフロップ回路 - Google Patents

マスタ−スレ−ブ型フリップフロップ回路

Info

Publication number
JPS60125011A
JPS60125011A JP58233987A JP23398783A JPS60125011A JP S60125011 A JPS60125011 A JP S60125011A JP 58233987 A JP58233987 A JP 58233987A JP 23398783 A JP23398783 A JP 23398783A JP S60125011 A JPS60125011 A JP S60125011A
Authority
JP
Japan
Prior art keywords
clock signal
data
circuit
input
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58233987A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0232809B2 (enExample
Inventor
Toshio Tanahashi
棚橋　俊夫
Tatsuo Sato
達夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58233987A priority Critical patent/JPS60125011A/ja
Publication of JPS60125011A publication Critical patent/JPS60125011A/ja
Publication of JPH0232809B2 publication Critical patent/JPH0232809B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type

Landscapes

  • Shift Register Type Memory (AREA)
JP58233987A 1983-12-12 1983-12-12 マスタ−スレ−ブ型フリップフロップ回路 Granted JPS60125011A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58233987A JPS60125011A (ja) 1983-12-12 1983-12-12 マスタ−スレ−ブ型フリップフロップ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58233987A JPS60125011A (ja) 1983-12-12 1983-12-12 マスタ−スレ−ブ型フリップフロップ回路

Publications (2)

Publication Number Publication Date
JPS60125011A true JPS60125011A (ja) 1985-07-04
JPH0232809B2 JPH0232809B2 (enExample) 1990-07-24

Family

ID=16963763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58233987A Granted JPS60125011A (ja) 1983-12-12 1983-12-12 マスタ−スレ−ブ型フリップフロップ回路

Country Status (1)

Country Link
JP (1) JPS60125011A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63214017A (ja) * 1987-03-02 1988-09-06 Oki Electric Ind Co Ltd フリツプフロツプ回路用クロツク制御回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63214017A (ja) * 1987-03-02 1988-09-06 Oki Electric Ind Co Ltd フリツプフロツプ回路用クロツク制御回路

Also Published As

Publication number Publication date
JPH0232809B2 (enExample) 1990-07-24

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