JPS60123799U - 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ - Google Patents

非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Info

Publication number
JPS60123799U
JPS60123799U JP13947584U JP13947584U JPS60123799U JP S60123799 U JPS60123799 U JP S60123799U JP 13947584 U JP13947584 U JP 13947584U JP 13947584 U JP13947584 U JP 13947584U JP S60123799 U JPS60123799 U JP S60123799U
Authority
JP
Japan
Prior art keywords
low
gate
transistor
driver
voltage state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13947584U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6125117Y2 (enExample
Inventor
プレブステイング，ラバト、ジエイ
Original Assignee
マステク、コ−パレイシヤン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by マステク、コ−パレイシヤン filed Critical マステク、コ−パレイシヤン
Priority to JP13947584U priority Critical patent/JPS60123799U/ja
Publication of JPS60123799U publication Critical patent/JPS60123799U/ja
Application granted granted Critical
Publication of JPS6125117Y2 publication Critical patent/JPS6125117Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
JP13947584U 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ Granted JPS60123799U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13947584U JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13947584U JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Publications (2)

Publication Number Publication Date
JPS60123799U true JPS60123799U (ja) 1985-08-21
JPS6125117Y2 JPS6125117Y2 (enExample) 1986-07-28

Family

ID=30697851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13947584U Granted JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Country Status (1)

Country Link
JP (1) JPS60123799U (enExample)

Also Published As

Publication number Publication date
JPS6125117Y2 (enExample) 1986-07-28

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