JPS6125117Y2 - - Google Patents

Info

Publication number
JPS6125117Y2
JPS6125117Y2 JP13947584U JP13947584U JPS6125117Y2 JP S6125117 Y2 JPS6125117 Y2 JP S6125117Y2 JP 13947584 U JP13947584 U JP 13947584U JP 13947584 U JP13947584 U JP 13947584U JP S6125117 Y2 JPS6125117 Y2 JP S6125117Y2
Authority
JP
Japan
Prior art keywords
transistor
signal
low
row
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13947584U
Other languages
English (en)
Japanese (ja)
Other versions
JPS60123799U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13947584U priority Critical patent/JPS60123799U/ja
Publication of JPS60123799U publication Critical patent/JPS60123799U/ja
Application granted granted Critical
Publication of JPS6125117Y2 publication Critical patent/JPS6125117Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
JP13947584U 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ Granted JPS60123799U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13947584U JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13947584U JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Publications (2)

Publication Number Publication Date
JPS60123799U JPS60123799U (ja) 1985-08-21
JPS6125117Y2 true JPS6125117Y2 (enExample) 1986-07-28

Family

ID=30697851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13947584U Granted JPS60123799U (ja) 1984-09-17 1984-09-17 非選択ロ−・ラインをホ−ルドダウンする半導体メモリデコ−ダ

Country Status (1)

Country Link
JP (1) JPS60123799U (enExample)

Also Published As

Publication number Publication date
JPS60123799U (ja) 1985-08-21

Similar Documents

Publication Publication Date Title
CN100390896C (zh) 用于静态随机存取存储器的存储器阵列
JPS6141198Y2 (enExample)
US4471240A (en) Power-saving decoder for memories
EP0142376B1 (en) Dynamic random access memory
US4618784A (en) High-performance, high-density CMOS decoder/driver circuit
US5646902A (en) Static random access memory device with low power dissipation
US4259731A (en) Quiet row selection circuitry
US6490189B1 (en) Boost voltage generating circuit for nonvolatile ferroelectric memory device and method for generating boost voltage
EP0190823A2 (en) Precharge circuit
US4338679A (en) Row driver circuit for semiconductor memory
KR900000052B1 (ko) 반도체 메모리 장치
JP2000113691A (ja) 半導体記憶装置のブースト回路と該回路を用いたＲｏｗデコーダ電源電位の昇圧方法
US6021069A (en) Bit latch scheme for parallel program verify in floating gate memory device
US4491936A (en) Dynamic random access memory cell with increased signal margin
US4360902A (en) Semiconductor memory decoder with nonselected row line hold down
US4878201A (en) Semiconductor memory device having an improved timing signal generator for the column selection circuit
US5894434A (en) MOS static memory array
EP0321847B1 (en) Semiconductor memory capable of improving data rewrite speed
US5404325A (en) Dynamic random access memory device with precharging unit preventing counter electrodes of storage capacitors from voltage fluctuation
US4360901A (en) Decoder circuit for semiconductor memory
US5418748A (en) Bit line load circuit for semiconductor static RAM
JPS6125117Y2 (enExample)
US6643200B2 (en) Sense amplifier having integrated y multiplexor and method therefor
US20040042249A1 (en) Random access memory device and method for driving a plate line segment therein
WO1981003569A1 (en) Semiconductor memory decoder with nonselected row line hold down