JPS6010735A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6010735A
JPS6010735A JP58119329A JP11932983A JPS6010735A JP S6010735 A JPS6010735 A JP S6010735A JP 58119329 A JP58119329 A JP 58119329A JP 11932983 A JP11932983 A JP 11932983A JP S6010735 A JPS6010735 A JP S6010735A
Authority
JP
Japan
Prior art keywords
conductor pattern
semiconductor device
conductor
transparent
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58119329A
Other languages
Japanese (ja)
Other versions
JPH0469428B2 (en
Inventor
Tamio Saito
斎藤　民雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58119329A priority Critical patent/JPS6010735A/en
Publication of JPS6010735A publication Critical patent/JPS6010735A/en
Publication of JPH0469428B2 publication Critical patent/JPH0469428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions

Abstract

PURPOSE:To facilitate positioning of a semiconductor element and a conductor pattern when face down bonding is to be performed, and to contrive to enhance mass producibility of a semiconductor device by a method wherein both an insulating substrate of wiring substrate and the conductor pattern to be adhered thereon are formed of transparent materials. CONSTITUTION:An insulating substrate 2 is formed of a transparent ceramic material such as polymer glass, plastics, a sapphire, etc., and conductor patterns 3, 5 are formed of a transparently good conductor such as ITO, SnO2, etc. Moreover insulating layers 4 are also formed of a transparently insulating material consisting of acrylic resin, epoxy resin, silicon, etc. A flip chip semiconductor element 6, an IC chip for example, having electrode terminals 7 forming solder bumps is eonnected to be fixed on a laminar conductor pattern 15 facing the electrode terminals 7 formed surface to the wiring substrate 1 side, namely according to face down bonding. At this case, because the connecting places can be confirmed according to the naked eye, etc., for example, through the substrate 2, the conductor pattern 3, the insulating layer 4 and the conductor pattern 5, positioning thereof is easy.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、フェイスダウンメンディングを用いた半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using face-down mending.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体素子を搭載し、素子相互間を接続する方法の一つ
として、フリツプテッグヴンデイングに代表すれるフェ
イスダウンボンディングが知られている。これは素子の
電極端子を半田バングを用いて配線基板上の導体パター
ンに直接接続する方法であシ、ワイヤボンディング等に
比べ電極端子と導体パターンとの間がワイヤの如き熱圧
着接続ではなく、半田の溶解によ多接続されるため、信
頼性にすぐれ、また一つの素子と配線基板上の導体パタ
ーンとの接続が電極端子の数に関係なく一度でできる等
の特長がある。Face-down bonding, represented by flip-tag bonding, is known as one of the methods for mounting semiconductor elements and connecting the elements to each other. This is a method in which the electrode terminals of the element are directly connected to the conductor pattern on the wiring board using solder bangs, and unlike wire bonding, the connection between the electrode terminal and the conductor pattern is not a wire-like thermocompression connection. Since multiple connections are made by melting solder, it has excellent reliability, and has the advantage of being able to connect one element to a conductor pattern on a wiring board in one go, regardless of the number of electrode terminals.

しかしながら、フェイスダウンボンディングではざンデ
イング時に素子の電極端子形成面か基板側を向くだめ、
電極端子およびこれが接続される導体、ノリーン上の接
続部がよく見、えない。However, in face-down bonding, the electrode terminal formation side of the element or the substrate side must be faced when sanding.
The electrode terminals, the conductors to which they are connected, and the connections on the Noreen are clearly visible.

そこで従来では半透鏡番用いて接続部を確認しながら、
素子と導体パタニンとの位置合せを行なっていた。従っ
て位置合せを含めたがンデイング工程に長時間を、要す
るという問題があった。Therefore, conventionally, while checking the connection part using a semi-transparent mirror number,
The element and conductor pattern were aligned. Therefore, there is a problem in that the binding process including alignment takes a long time.

〔発明の目的〕[Purpose of the invention]

との発明の目的は、フェイスダウンダンディングに際し
２半導体累子と配線基板上の導体パターンとの位置合せ
が容易で、　ｉ：産性にすぐれた半導体装置を提供する
ことにある。An object of the invention is to provide a semiconductor device which allows easy alignment of two semiconductor stackers and a conductor pattern on a wiring board during face-down dumping, and which has excellent productivity.

〔発明の４ａ要〕 この発明は、配線基板の絶縁性基体お□よびその上に被
着形成される導体パターンをいずれも透明材料によ多形
成することによって、基板の裏面側から半導体素子の電
極端子と導体パターンとの接続部が確しできるようにし
たものでおる。[Summary 4a of the Invention] This invention provides a method for forming semiconductor elements from the back side of the substrate by forming both the insulating substrate of the wiring board and the conductor pattern formed thereon using a transparent material. It is designed to ensure the connection between the electrode terminal and the conductor pattern.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、半導体素子と配線基板上の導体パタ
ーンとの位置合せを半透鏡等を用いるこ、となく極めて
容易、確実に行なうことかでキル。従ってフェイスダウ
ンボンディング本来の和長と相まって、非常に量産性が
よく製造コストの低い半導体装置を提供することが可能
である。According to this invention, alignment between a semiconductor element and a conductor pattern on a wiring board can be performed extremely easily and reliably without using a semi-transparent mirror or the like. Therefore, in combination with the inherent length of face-down bonding, it is possible to provide a semiconductor device that is highly mass-producible and has low manufacturing costs.

〔発明の実施例〕[Embodiments of the invention]

第１図はこの発明の一丈島例に係る半導体装置−の断面
図である。FIG. 1 is a sectional view of a semiconductor device according to the Ichijojima example of the present invention.

図において、配線基板Ｊはこの例では絶縁性基体２土に
第１層導体パターン３．絶縁体層４および第２層嗜体パ
ターン５を順次形成した２層の配線基板である。第１層
１ｗ、２層の導体パターン３．５は、絶縁体層４に形成
したスルーホールを通して適宜接続されている。ここで
。In the figure, in this example, the wiring board J includes an insulating substrate 2 and a first layer conductor pattern 3. This is a two-layer wiring board in which an insulating layer 4 and a second layer pattern 5 are sequentially formed. The first layer 1w and the second layer conductor patterns 3.5 are appropriately connected through through holes formed in the insulating layer 4. here.

絶縁性基体２はポリマーガラス、ゲラステック。The insulating substrate 2 is made of polymer glass and gelastec.

サファイヤ等の透明セラミック材料によって形成されて
いる。また、導体ノ４’ターン３　＊　５　Ｆｉ　’Ｉ
ＩＴＯ，ＳｎＯ，等の透明良導体によ多形成されている
。さらに、絶縁体層４もアクリル、エポキシ、シリコン
等からなる透明絶縁材料から形成されている。It is made of transparent ceramic material such as sapphire. Also, conductor no 4' turn 3 * 5 Fi 'I
It is made of a transparent good conductor such as ITO, SnO, etc. Furthermore, the insulator layer 4 is also formed from a transparent insulating material such as acrylic, epoxy, silicon, or the like.

そして、第２層導体・母ターン１５上に、半田バングを
形成した電極端子７を有するフリップテップ半導体素子
６１例えばＩＣテップが電極端子７の形成面を配線基板
１側に向けて、すなワチフエイスダウンボンデイングに
より　ｔｉ続固定されている。この場合、半導体素子６
は電極端子７が導体パターン５の所定位置に接続される
ように、導体ノｆターン５に対し正確に位置合せする必
要があるが、電極端子７と導体ノ４ターン５との接続個
所を基体２．導体ノＪ？ターン３゜絶縁体層４および導
体パターン５を通して例えば肉眼等で確認できるため、
この位置合せは容易である。Then, on the second layer conductor/mother turn 15, a flip-tep semiconductor element 61 having an electrode terminal 7 formed with a solder bang, for example, an IC chip, is placed so that the surface on which the electrode terminal 7 is formed faces the wiring board 1 side. Ti connection is fixed by face down bonding. In this case, the semiconductor element 6
It is necessary to accurately align the electrode terminal 7 with the conductor turn 5 so that the electrode terminal 7 is connected to a predetermined position of the conductor pattern 5, but the connection point between the electrode terminal 7 and the conductor turn 5 must be 2. Conductor no J? The turn 3° can be confirmed with the naked eye through the insulator layer 4 and conductor pattern 5, so
This alignment is easy.

なお、第２層導体パターン５上の電極端子７の接続部に
は、必要に応じて％：電極端子の接続を良好にするだめ
のメタライズが施される。具体的には、Ｃｒ、Ｔｉ、Ｗ
等からなる接着層。Note that the connection portions of the electrode terminals 7 on the second layer conductor pattern 5 are provided with metallization to improve the connection of the electrode terminals, if necessary. Specifically, Cr, Ti, W
Adhesive layer consisting of etc.

Ｐｄ、Ｎｉ等からなる拡散防止層、熱圧着のためのＣｕ
　、　Ａｕ　、　Ａ１等の層、耐ハンタ性の良好なＮｌ
　、Ｃｕ等の層およびＡｕ等の酸化防止層を適宜形成す
る。Diffusion prevention layer made of Pd, Ni, etc., Cu for thermocompression bonding
, Au, A1 layer, Nl with good hunter resistance
, a layer of Cu, etc., and an anti-oxidation layer of Au, etc. are formed as appropriate.

また、第１図には示していないが、配線基板Ｊ上に必要
に応じ保護層がモールドされる。第２層導体パターン５
上の半導体素子６の接続部以外の表面を予めアクＩＪ　
ｘ　、エポキシ等からなる透明絶縁材料で被覆すること
も可能である。Although not shown in FIG. 1, a protective layer is molded on the wiring board J as required. Second layer conductor pattern 5
The surface of the upper semiconductor element 6 other than the connection part is preliminarily exposed to the IJ.
It is also possible to coat with a transparent insulating material such as x, epoxy or the like.

次ＶＣ，配線基板１の製造工程の一例を第２図を参照し
て説明する。Next, an example of the manufacturing process of the VC and wiring board 1 will be explained with reference to FIG.

まず、印、２図（酊に示すように透明絶縁性基体２、例
えばガラス基板上に、ポジ型フォトレジスト１１を塗布
し乾燥させた後、第１層透明導体パターン３と反転関係
にある不透明・母ターン１２を選択的に形成したガラス
マスクＪ３を用いて露光を行ない１次いで第２図（ｂ＋
のように現像する。次に第２図（ＣＯＸ示すようｖｃ、
透明導体膜１４．例えばＩＴＯ膜を低温スパッタによシ
１μ程度着膜し、その後卯２図（ｄ＋に示すようにフォ
トレジスト１１上の透明導体をリフトオフにより除去し
て、第１層の透明導体パターン３を形成する。配線基板
が単層のものの場合は。First, as shown in Figure 2, a positive photoresist 11 is coated on a transparent insulating substrate 2, for example, a glass substrate, and after drying, an opaque photoresist 11 is applied in an inverted relationship with the first layer transparent conductor pattern 3.・Exposure is carried out using the glass mask J3 in which the mother turns 12 are selectively formed, and as shown in FIG.
Develop as shown. Next, as shown in Figure 2 (COX, vc,
Transparent conductor film 14. For example, an ITO film of about 1 μm is deposited by low-temperature sputtering, and then, as shown in Figure 2 (d+), the transparent conductor on the photoresist 11 is removed by lift-off to form the first layer of transparent conductor pattern 3. .If the wiring board is a single layer one.

とわで基板製造工程は終了し、以後は半導体素子のボン
ディング工程へと進むことになる。At this point, the substrate manufacturing process is completed, and the next step is to proceed to the bonding process for semiconductor elements.

次に、卯、２図（ｅＪｖｃ示すように透明絶縁体層１５
、例えば紫外線硬化型樹脂（アクリル、工？キシ等）を
スクリーン印刷、スピンコード等によシ塗布し、スルー
ホールに対応する不透明パターン１６を選択的に形成し
たガラスマスク１７ｆ介して紫外線によりｉ光、現像す
る。これによシ第２図（ｆ）に示すように、所定位置に
スルーホール１８を有する透明絶縁体層４が形成される
。Next, as shown in Figure 2 (eJvc), the transparent insulator layer 15
For example, ultraviolet curable resin (acrylic, polyester, etc.) is applied by screen printing, spin cord, etc., and ultraviolet light is applied through a glass mask 17f in which an opaque pattern 16 corresponding to the through hole is selectively formed. ,develop. As a result, as shown in FIG. 2(f), a transparent insulating layer 4 having through holes 18 at predetermined positions is formed.

そして１次にＮＩ２図（ｇ）　ＶＣ示すように再びポジ
型フォトレジスト１９を塗布し乾燥させ、第２層の透明
導体パターン５と反転関係ｖｃある不透明パターン２０
ｆ選択的に形成したガラスマスク２１を用いて露光した
後、第２図（ｂＪ〜（ｄｌと同様の工程を経て、第２図
（ｈＪに示すように第２層の透明導体パターン５を形成
する。こうして第１図中に示しだ２層の配線基板Ｊが得
られる。Next, as shown in Figure NI2 (g) VC, a positive photoresist 19 is applied again and dried, forming an opaque pattern 20 that has an inverted relationship VC with the transparent conductor pattern 5 of the second layer.
After exposure using a selectively formed glass mask 21, a second layer of transparent conductor pattern 5 is formed as shown in FIG. In this way, a two-layer wiring board J shown in FIG. 1 is obtained.

なお、第２図（ａ＋〜（ｄｌの工程ではりフトオフを用
いたが、まず透明導体層を形成し、その後フォトレジス
トを形成し、露光、現像後、エツチングを行なって透明
導体ノ臂ターン３を形成し。Incidentally, although a beam lift-off was used in the steps of FIG. form.

フォトレジストを除去してもよい。The photoresist may be removed.

また、上記実施例では配線基板として２層のものを示し
たが、単層、あるいは３層以上の場合でもこの発明は有
効である。Furthermore, although the above embodiments have shown a two-layer wiring board, the present invention is also effective in the case of a single layer or three or more layers.

この発明に係る半導体装置において、配線基板上に搭載
する半導体素子は何でもよいが、特に発光または受光素
子の場合、基板側に発光またけ受光面を向けることがで
きる利点がある。In the semiconductor device according to the present invention, any semiconductor element may be mounted on the wiring board, but especially in the case of a light-emitting or light-receiving element, there is an advantage that the light-emitting and light-receiving surfaces can face the substrate side.

すなわち、従来では発光まだは受光素子はフリップテッ
プ等の７ヱイスダウンざンデイングは不可能とされてい
たが、この発明によればそれが可ｊ能となる。That is, although conventionally it has been considered impossible to perform 7-inch down-sizing such as flip-step on a light-receiving element while it is not emitting light, this invention makes it possible.

４図面の簡単な説明　］ ！！、１図はこの発明の一実施例に係る半導体装置の断
面図、第２図（ａ＋〜（ｈ＋はこの発明で用いる配線基
板の製造工程を示す図である。4. Brief explanation of the drawings]! ! , 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 (a+ to (h+) are diagrams showing manufacturing steps of a wiring board used in the present invention.

１・・・配線基板、２・・・透明絶縁性基体、３．５・
・・透明導体／母ターン、４・・・透明絶縁体層、６・
・・半導体素子、７・・・電極端子。1... Wiring board, 2... Transparent insulating substrate, 3.5.
...Transparent conductor/mother turn, 4...Transparent insulator layer, 6.
... Semiconductor element, 7... Electrode terminal.

Claims (1)

【特許請求の範囲】 （１１配線基板上の導体パターンｖｃ、半導体素子の電
極端子をその電極端子形成面を配線基板側に向けて接続
してなる半導体装置において。 前記配線基板は透明絶縁性基体上に透明導体パターンを
被着形成して構成されていることを特徴とする半導体装
置。 （２）　配線基板は透明絶縁性基体上に複数層の透明導
体パターンを層間に透明絶縁体層を介して積層形成した
ものであることを特徴とする特許請求の範囲第１項記載
の半導体装置。 （３）　透明導体パターンの半導体素子接続部に。 半導体素子の電極端子を接続するためのメタライズが施
されていることを特徴とする特許請求の範囲第１項記載
の半導体装置。 （４）半導体素子が発光または受光素子であることを特
徴とする特許請求の範囲第１項記載の半導体装置。[Scope of Claims] (11) A semiconductor device comprising a conductor pattern VC on a wiring board and electrode terminals of a semiconductor element connected with the electrode terminal forming surface thereof facing the wiring board side. The wiring board is a transparent insulating substrate. A semiconductor device characterized in that it is constructed by depositing a transparent conductor pattern thereon. (2) The wiring board is a transparent insulating substrate with a plurality of layers of transparent conductor patterns interposed between the layers, with a transparent insulating layer interposed between the layers. The semiconductor device according to claim 1, characterized in that the semiconductor device is formed by laminating layers. (3) At the semiconductor element connecting portion of the transparent conductor pattern. Metallized for connecting the electrode terminal of the semiconductor element. (4) The semiconductor device according to claim 1, wherein the semiconductor element is a light emitting or light receiving element.
JP58119329A 1983-06-30 1983-06-30 Semiconductor device Granted JPS6010735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58119329A JPS6010735A (en) 1983-06-30 1983-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119329A JPS6010735A (en) 1983-06-30 1983-06-30 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5254357A Division JP2597809B2 (en) 1993-10-12 1993-10-12 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6010735A true JPS6010735A (en) 1985-01-19
JPH0469428B2 JPH0469428B2 (en) 1992-11-06

Family

ID=14758775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58119329A Granted JPS6010735A (en) 1983-06-30 1983-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6010735A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005202382A (en) * 2003-12-18 2005-07-28 Sumitomo Bakelite Co Ltd Optical printed circuit board, surface mounting type semiconductor package, and mother board
JP2006504257A (en) * 2002-10-23 2006-02-02 ゴールドパワー リミテッド Contact formation on a semiconductor substrate

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269646A (en) * 1975-12-08 1977-06-09 Seiko Epson Corp Liquid crystal display device
JPS5273693A (en) * 1975-12-16 1977-06-20 Seiko Epson Corp Display device
JPS5276051A (en) * 1975-12-22 1977-06-25 Seiko Epson Corp Liquid crystal indicating device
JPS5276877A (en) * 1975-12-22 1977-06-28 Seiko Epson Corp Semiconductor device
JPS5359398A (en) * 1976-11-09 1978-05-29 Seiko Epson Corp Liquid crystal display panel
JPS53104198A (en) * 1977-02-23 1978-09-11 Takagi Kogyo Kk Liquid crystal panel
JPS5552229A (en) * 1978-10-11 1980-04-16 Nec Corp Manufacture of semiconductor device
JPS5691491A (en) * 1979-12-25 1981-07-24 Alps Electric Co Ltd Method of manufacturing transparent laminated circuit board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269646A (en) * 1975-12-08 1977-06-09 Seiko Epson Corp Liquid crystal display device
JPS5273693A (en) * 1975-12-16 1977-06-20 Seiko Epson Corp Display device
JPS5276051A (en) * 1975-12-22 1977-06-25 Seiko Epson Corp Liquid crystal indicating device
JPS5276877A (en) * 1975-12-22 1977-06-28 Seiko Epson Corp Semiconductor device
JPS5359398A (en) * 1976-11-09 1978-05-29 Seiko Epson Corp Liquid crystal display panel
JPS53104198A (en) * 1977-02-23 1978-09-11 Takagi Kogyo Kk Liquid crystal panel
JPS5552229A (en) * 1978-10-11 1980-04-16 Nec Corp Manufacture of semiconductor device
JPS5691491A (en) * 1979-12-25 1981-07-24 Alps Electric Co Ltd Method of manufacturing transparent laminated circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006504257A (en) * 2002-10-23 2006-02-02 ゴールドパワー リミテッド Contact formation on a semiconductor substrate
USRE43948E1 (en) 2002-10-23 2013-01-29 Siemens Aktiengesellschaft Formation of contacts on semiconductor substrates
JP2005202382A (en) * 2003-12-18 2005-07-28 Sumitomo Bakelite Co Ltd Optical printed circuit board, surface mounting type semiconductor package, and mother board

Also Published As

Publication number Publication date
JPH0469428B2 (en) 1992-11-06

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