JPH03273655A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH03273655A
JPH03273655A JP2075048A JP7504890A JPH03273655A JP H03273655 A JPH03273655 A JP H03273655A JP 2075048 A JP2075048 A JP 2075048A JP 7504890 A JP7504890 A JP 7504890A JP H03273655 A JPH03273655 A JP H03273655A
Authority
JP
Japan
Prior art keywords
circuit board
thermocompression
bonded
semiconductor element
columnar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2075048A
Other languages
Japanese (ja)
Inventor
Yuji Kajiwara
梶原 勇次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2075048A priority Critical patent/JPH03273655A/en
Publication of JPH03273655A publication Critical patent/JPH03273655A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent

Abstract

PURPOSE:To enable wireless bonding with high density easily even when a normal Al electrode is used as a terminal electrode in the semiconductor element substrate of an IC, an LSI, etc., by forming a conductor projection on the wiring electrode side of a circuit board and connecting the circuit board and a semiconductor element. CONSTITUTION:A circuit board 12, on which a plurality of wiring electrodes 11 are formed, is fixed to a support table heated at 150 deg.C, tip spherical Au wires having 30mumphi are thermocompression-bonded successively onto the wiring electrodes 11, and columnar thermocompression-bonded Au projections 13 are formed. Thermocompression bonding is executed by applying ultrasonic vibrations to the tip spherical Au wires in the direction parallel with the surface of the circuit board and applying pressure to the tip spherical Au wires in the vertical direction, and the columnar thermocompression-bonded Au projections 3 can easily and continuously be formed. Semiconductor element substrates 15, on which Al terminal electrodes 14 are shaped, are placed onto the circuit board 12, in which the columnar thermocompression-bonded Au projections 13 are formed onto the wiring electrodes 11, and connecting sections, on which the columnar thermocompression-bonded Au projections 13 and the Al terminal electrodes 14 are put oppositely, are bonded through thermocompression bonding.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、回路基板上にIC,LSIなどの半導体素子
基板が実装された混成集積回路装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device in which a semiconductor element substrate such as an IC or an LSI is mounted on a circuit board.

〔従来の技術〕[Conventional technology]

近年、一基板上に多くの半導体素子を搭載するマルチチ
ップ化混成集積回路や、極めて薄く形成された小型化回
路基板の開発が進められ、中でもファクシミリ装置に使
われるサーマルヘッドやイメージセンサ、LCD、El
デイスプレィ、ICカードなどが実用化されている。こ
れらは半導体技術の進展に伴ない、低コスト、高性能化
の要求に対応するもので、半導体素子と回路基板上に形
成される微細配線電極との接続がそのデバイスの大きさ
、性能を決定している。
In recent years, the development of multi-chip hybrid integrated circuits that mount many semiconductor elements on one substrate and miniaturized circuit boards that are formed extremely thin has progressed, and among them, thermal heads used in facsimile machines, image sensors, LCDs, El
Displays, IC cards, etc. have been put into practical use. These devices meet the demands for lower cost and higher performance as semiconductor technology progresses, and the connection between the semiconductor element and the fine wiring electrodes formed on the circuit board determines the size and performance of the device. are doing.

従来主として用いられる混成集積回路装置では〜あるい
は細線を使用したワイヤボンディングによって半導体素
子と回路基板とが接続されている。
In hybrid integrated circuit devices mainly used in the past, semiconductor elements and circuit boards are connected by wire bonding using thin wires.

しかし、さらに端子数が増加し、またデバイス全体を薄
型化するには限界がある。これに対し半導体素子の端子
電極に金属バンブを形成して実装するフリップチップ方
式やTAB方式が注目され、有効な手段として使用され
ている。これらは、回路基板あるいはフィルムテープ上
に複数個の半導体素子を連続して搭載することが可能で
端子接続後の特性検査が容易になることと、薄型化デバ
イスを実現するには有利な点が多いからである。
However, the number of terminals increases further, and there is a limit to how thin the entire device can be made. On the other hand, the flip-chip method and the TAB method, in which metal bumps are formed and mounted on the terminal electrodes of semiconductor elements, have attracted attention and are being used as effective means. These have the advantage of being able to mount multiple semiconductor elements in succession on a circuit board or film tape, making it easier to inspect the characteristics after connecting terminals, and realizing thinner devices. This is because there are many.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、これに用いる半導体素子の端子電極は、
アルミ材の上にTi −Pt、 Ti−W 、 Ti 
−Cu。
However, the terminal electrodes of the semiconductor elements used for this,
Ti-Pt, Ti-W, Ti on aluminum material
-Cu.

Cr−cn、 Cr−mなどのバリアメタルの蒸着工程
Vapor deposition process of barrier metals such as Cr-cn and Cr-m.

感光性樹脂によるパターン化の7オトリソエ程。Seven steps of patterning using photosensitive resin.

バンプを形成するためのAuメツキ工程およびエツチン
グ工程など複雑な工程が付加されるため、さらに特殊な
製造設備が必要で、このような工程がほぼ完成された半
導体ウェハに実装されるため、歩留りが低下し、半導体
素子チップの総合コストが非常に高くなるという欠点が
ある。
Because complex processes such as Au plating and etching processes are added to form bumps, special manufacturing equipment is required, and since these processes are mounted on almost completed semiconductor wafers, yields are low. This has the disadvantage that the total cost of the semiconductor element chip becomes very high.

本発明の目的は、上記のような問題点を解消すめために
なされたもので、低コストの混成集積回路@直を提供す
ることにある。
An object of the present invention is to solve the above-mentioned problems, and to provide a low-cost hybrid integrated circuit.

(!Iliを解決するための手段〕 本発明の混成集積回路装置は、 複数儂の配線電極が形成された回路基板と、前記配線電
極上に先端球状細線を順次圧着して形成された1つ以上
の円柱状圧着導体突起と、該圧着導体突起と同等の位置
に端子電極をもち、該端子電極が該圧着導体突起とvA
wされて、前記回路基板と対向する半導体素子基板とを
有する。
(Means for Solving !Ili) The hybrid integrated circuit device of the present invention includes a circuit board on which a plurality of wiring electrodes are formed, and one circuit board formed by sequentially crimping thin wires with spherical tips on the wiring electrodes. The above cylindrical crimp conductor projection has a terminal electrode at the same position as the crimp conductor projection, and the terminal electrode is connected to the crimp conductor projection at vA.
and a semiconductor element substrate facing the circuit board.

〔作用〕[Effect]

回路基板の配線電極側にPJ単な導体突起を形成して、
回路基板と導体素子を接続するため、低コストの混成集
積回路装置が得られる。
By forming a PJ simple conductor protrusion on the wiring electrode side of the circuit board,
Since the circuit board and the conductive element are connected, a low-cost hybrid integrated circuit device is obtained.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例の混成集積回路装置を示
す概略断面図である。
FIG. 1 is a schematic sectional view showing a hybrid integrated circuit device according to a first embodiment of the present invention.

本実施例の混成集積回路装置は、複数個の配線電極11
が形成された回路基板12と、配線電極11上に先端球
状ん線を順次熱圧着した形成された円柱状熱圧WALI
突起13と、該熱圧着突起13と同等の位置にM端子電
極14をもち、該M端子電極14が熱圧着ん突起と固着
されて回路基板12と対向する半導体素子基板15とか
らなっている。
The hybrid integrated circuit device of this embodiment has a plurality of wiring electrodes 11
The circuit board 12 on which is formed, and the cylindrical thermo-pressure WALI formed by sequentially thermo-compressing the spherical wire at the tip onto the wiring electrode 11.
It consists of a protrusion 13 and a semiconductor element substrate 15 having an M terminal electrode 14 at the same position as the thermocompression protrusion 13, the M terminal electrode 14 being fixed to the thermocompression protrusion and facing the circuit board 12. .

次に、本実施例の混成集積回路装置の1M3![方法を
説明する。
Next, 1M3! of the hybrid integrated circuit device of this embodiment! [Explain the method.]

複数の配線電極11が形成された回路基板12を例えば
150℃に加熱した支持テーブルに固定し、配線電極1
1上に301j11φの先端球状細線を順次熱圧着し、
円柱状熱圧@〜突起13を形成する。熱圧着は回路”基
板面と平行方向に超音波振動、垂直方向に圧力を先端球
状ALIIIに印加すればよく、連続して容易に円柱状
熱圧@ん突起13を形成することができる。さらに、配
線電極11に円柱状熱圧IAu突起13が形成された回
路基板12上に、A11fi子電極14が形成された半
導体素子基板15を載雪し、円柱状熱圧着船突起13と
M端子電極14とが相対して配置されたl!統部を熱圧
着によって接続する。
The circuit board 12 on which a plurality of wiring electrodes 11 are formed is fixed to a support table heated to, for example, 150°C, and the wiring electrodes 1
Thin wires with a spherical tip of 301j11φ were sequentially bonded by thermocompression onto 1.
A cylindrical hot pressure protrusion 13 is formed. For thermocompression bonding, it is sufficient to apply ultrasonic vibration in a direction parallel to the surface of the circuit board and pressure in a vertical direction to the spherical tip ALIII, and the cylindrical thermocompression protrusion 13 can be easily formed in a continuous manner. , the semiconductor element substrate 15 on which the A11fi element electrode 14 is formed is placed on the circuit board 12 on which the cylindrical thermocompression IAu protrusion 13 is formed on the wiring electrode 11, and the cylindrical thermocompression bonded protrusion 13 and the M terminal electrode are placed. 14 are placed facing each other and are connected by thermocompression bonding.

このような構造の混成集積回路装置は、使用した半導体
素子基板15の端子電極には複雑な工程によってバンブ
を作る必要が無く、通常汎用的に使用されているM端子
電極のままで良い。したがって、半導体素子基板15は
ウェハ時で検査した良質だけを使用できる。さらに、回
路基板12への円柱状熱圧着〜突起13の形成も不良回
路基板には選択して実行しなくとも良くなるので、無駄
も無くなる。総合的に極めて低価格で超薄型の混成集積
回路装置を得ることができる。
In the hybrid integrated circuit device having such a structure, there is no need to create bumps in the terminal electrodes of the semiconductor element substrate 15 through a complicated process, and the M terminal electrodes that are normally used for general purposes can be used as they are. Therefore, only good quality semiconductor element substrates 15 that are inspected at the time of wafer processing can be used. Furthermore, it is no longer necessary to selectively perform the cylindrical thermocompression bonding to the formation of the protrusions 13 on the circuit board 12 for defective circuit boards, so there is no waste. Overall, an ultra-thin hybrid integrated circuit device can be obtained at an extremely low cost.

なお、上記実施例では〜細線を30鳩φ、a!度を15
0℃に設定して行ったが、これに限定されることなく円
板状熱圧着〜突起13の形状、ピッチ、回路基板材など
との適合性により、自由に選択して良い。また、この細
線の材料も他の材料、例えばCu、 Mなど配線電極に
圧着できるものであればよい。
In addition, in the above example, ~30 pigeons φ, a! degree 15
Although the temperature was set at 0° C., the temperature is not limited to this, and may be freely selected depending on the shape, pitch, compatibility with the circuit board material, etc. of the disc-shaped thermocompression bonding. Further, the material of this thin wire may be any other material, such as Cu or M, as long as it can be bonded to the wiring electrode.

ワイヤボンドによる接続の際にはM端子電極14の配置
は半導体素子基板15の周辺部に限られていたが、M端
子電極14を半導体素子15の中央部にも設置できるの
で高!5度に多くの端子電極の接続が可能となる。
When connecting by wire bonding, the arrangement of the M terminal electrode 14 is limited to the periphery of the semiconductor element substrate 15, but since the M terminal electrode 14 can also be placed in the center of the semiconductor element 15, it is more convenient. Many terminal electrodes can be connected in 5 degrees.

第2図は本発明の第2の実施例混成111積回路装雪を
示す概略断面図である。
FIG. 2 is a schematic cross-sectional view showing a hybrid 111 integrated circuit snow system according to a second embodiment of the present invention.

回路基板12上の配線電極11に熱圧着によって円柱状
熱圧着ん突起13が形成された構造は第1の実施例に示
した構造と同等である。本実施例ではこの円柱状熱圧着
〜突起13の上にざらに^Oペーストのような導電性接
着剤16を塗布している。これは転写あるいはデイスペ
ンサなどにより容易に可能である。その後、半導体素子
基板15をAi喘丁子電極14円柱状熱圧着ん突起13
とを相対させ載置し、導電性接着剤16を加熱硬化させ
接続させている。
The structure in which the cylindrical thermocompression protrusion 13 is formed on the wiring electrode 11 on the circuit board 12 by thermocompression bonding is the same as the structure shown in the first embodiment. In this embodiment, a conductive adhesive 16 such as ^O paste is roughly applied onto the cylindrical thermocompression bonding protrusion 13. This can easily be done by transfer or dispenser. Thereafter, the semiconductor element substrate 15 is attached to the Ai strip electrode 14 and the cylindrical thermocompression protrusion 13.
are placed facing each other, and the conductive adhesive 16 is heated and cured to connect them.

このような構造によれば第1の実施例に示した効果は同
様に得られる他、円柱状熱圧着ん突起13とM端子電極
14との固着の際、極端に大きな押圧力を必要としない
。このため、とかく、双方の端子部を押圧した際に発生
する半導体素子基板15のマイク[」クラックによる損
傷が無くなり、安定した接続が高密度で可能になる。
According to such a structure, the effects shown in the first embodiment can be obtained in the same way, and an extremely large pressing force is not required when the cylindrical thermocompression bonding protrusion 13 and the M terminal electrode 14 are fixed together. . Therefore, damage caused by microphone cracks on the semiconductor element substrate 15 that occurs when both terminal portions are pressed is eliminated, and stable connection can be achieved at high density.

なお、以上の説明では、半導体素子基板の端子電極はM
端子電極のものを111だけを使用したが、多数似でも
よくまた高価になるが半田バンプ、Auバンプが形成さ
れているものでも同様に適用できることはその構成から
明らかであり、特に本発明を限定するものではない。
In addition, in the above explanation, the terminal electrode of the semiconductor element substrate is M
Although only the terminal electrode 111 was used, it is clear from the structure that it can be applied to a terminal electrode having solder bumps or Au bumps formed thereon, although it is possible to use many similar ones and it will be expensive. It's not something you do.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、回路基板の配線電極側に
導体突起を形成して、回路基板と半導体素子を接続する
ことにより、IC,LSIなどの半導体素子基板は端子
電極に通常のMl!極を用いても容易にワイヤレス接続
が高密度で可能になるので、このような構成をフィルム
キャリア実装によるTAB方式やあるいはフリップチッ
プ方式などの機能デバイスに実装すれば、装置デバイス
の小型、iI型化、高性能化、低価格化が実現される効
果がある。
As explained above, the present invention connects the circuit board and the semiconductor element by forming conductor protrusions on the wiring electrode side of the circuit board, so that semiconductor element boards such as ICs and LSIs can be connected to the terminal electrodes of ordinary Ml! High-density wireless connections are easily possible even when using wires, so if such a configuration is implemented in a functional device such as the TAB method using film carrier mounting or the flip chip method, it will be possible to reduce the size of equipment devices, iI type, etc. This has the effect of realizing higher performance, higher performance, and lower cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の一実施例の混成集積回路
装置を示す概略断面図である。 11・・・配線電極、   12・・・回路基板、13
・・・円柱状熱圧@〜突起、 14・・・M端子電極、  15・・・半導体素子基板
、16・・・導電性接着剤。
1 and 2 are schematic sectional views showing a hybrid integrated circuit device according to an embodiment of the present invention. 11... Wiring electrode, 12... Circuit board, 13
. . . Cylindrical hot pressure @ ~ protrusion, 14 . . M terminal electrode, 15 . . . semiconductor element substrate, 16 . . . conductive adhesive.

Claims (1)

【特許請求の範囲】[Claims] 1、複数個の配線電極が形成された回路基板と、前記配
線電極上に先端球状細線を順次圧着して形成された1つ
以上の円柱状圧着導体突起と、該圧着導体突起と同等の
位置に端子電極をもち、該端子電極が該圧着導体突起と
固着されて、前記回路基板と対向する半導体素子基板と
を有する混成集積回路装置。
1. A circuit board on which a plurality of wiring electrodes are formed, one or more cylindrical crimped conductor protrusions formed by successively crimping spherical thin wires on the wiring electrodes, and positions equivalent to the crimped conductor protrusions. 1. A hybrid integrated circuit device comprising: a semiconductor element substrate facing the circuit board; the terminal electrode being fixed to the crimp conductor protrusion;
JP2075048A 1990-03-22 1990-03-22 Hybrid integrated circuit device Pending JPH03273655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2075048A JPH03273655A (en) 1990-03-22 1990-03-22 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2075048A JPH03273655A (en) 1990-03-22 1990-03-22 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03273655A true JPH03273655A (en) 1991-12-04

Family

ID=13564930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2075048A Pending JPH03273655A (en) 1990-03-22 1990-03-22 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03273655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077725A (en) * 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077725A (en) * 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules

Similar Documents

Publication Publication Date Title
JP3186941B2 (en) Semiconductor chips and multi-chip semiconductor modules
US4693770A (en) Method of bonding semiconductor devices together
JPH0332914B2 (en)
US6717252B2 (en) Semiconductor device
JP2001068621A (en) Semiconductor device and its manufacture
WO1999034436A1 (en) Semiconductor device
US20080111230A1 (en) Wiring film having wire, semiconductor package including the wiring film, and method of fabricating the semiconductor package
JP2001250836A (en) Semiconductor device and its manufacturing method
US20050269680A1 (en) System-in-package (SIP) structure and fabrication thereof
US6528343B1 (en) Semiconductor device its manufacturing method and electronic device
JPH0432541B2 (en)
JPH03273655A (en) Hybrid integrated circuit device
JP2002231765A (en) Semiconductor device
JP3500378B2 (en) Semiconductor device and manufacturing method thereof
JP2004288815A (en) Semiconductor device and its manufacturing method
JP3770321B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
KR100310037B1 (en) Method for fabricating flexible printed circuit boad with a plurality of chip
JPH04242939A (en) Packaging structure of semiconductor device and its manufacture
JP4465884B2 (en) Semiconductor device and manufacturing method thereof
JPH07254632A (en) Semiconductor device and manufacture thereof
JPS5824014B2 (en) Manufacturing method of mounting body
JP2841822B2 (en) Manufacturing method of hybrid integrated circuit
JP2004214373A (en) Semiconductor device with bumps and its packaging method
JPS6091656A (en) Manufacture of semiconductor device
JPH1022329A (en) Semiconductor device