JPS60106174A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS60106174A JPS60106174A JP21532683A JP21532683A JPS60106174A JP S60106174 A JPS60106174 A JP S60106174A JP 21532683 A JP21532683 A JP 21532683A JP 21532683 A JP21532683 A JP 21532683A JP S60106174 A JPS60106174 A JP S60106174A
- Authority
- JP
- Japan
- Prior art keywords
- type
- source
- regions
- forming
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000001569 carbon dioxide Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- 235000011089 carbon dioxide Nutrition 0.000 abstract 3
- 230000004913 activation Effects 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 229910020489 SiO3 Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- -1 1-phosphorus (P) Chemical class 0.000 description 1
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はMO8形半導体装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing an MO8 type semiconductor device.
第1図(A)〜(D)は従来のMO8形半導体装置の製
造方法の一例の主要段階の状態を示す断面図である0
まず、第1図(A)に示すように、p形シリコン(Si
)基板(1)の主面部のMO8形半導体素子を形成すべ
き部分以外の部分に素子間分離用の酸化シリコン(81
02)膜(2)を形成したのちに、p形S1基板(1)
の主面部のS iO2膜(2)によって取り囲まれた部
分の所要部分上に200〜500人程度の厚さのゲート
絶縁膜(3)を介して多結晶Siゲート層(4)を形成
する。次いで、SiO2膜(2)および多結晶8iゲ一
ト層(4)をマスクにした図示矢印の方向からのヒ素(
第8)1リン(P)などのn形不純物のイオンの注入に
よって、p形Si基板(1)の主面部の多結晶Siゲー
ト層(4)の両側の露出部分にそれぞれn形ソース領域
形成用のn形イオン注入領域(5)およびn形ドレイン
領域形成用のn形イオン注入領域(6)を形成する。次
に1第1図(B)に示すように、SiO3膜(2)、多
結晶S1ゲ一ト層(4)およびn形イオン注入領域(5
) 、 ’(6)の各表面上にわたって、700℃程度
の低温の化学的気相蒸着(CVD)法によって表面保護
用の8102膜(7)を形成する。次に、第1図(C)
に示すように、n形イオン注入領域<5)、 (6)に
注入されているn形イオンを活性化するために1000
℃程度の高温炉内における熱処理を行うと、n形イオン
注入領域(5)およびn形イオン注入領域(6)内のn
形不純物の拡散によってn形ソース領域(5a)および
n形ドレイン領域(6a)が形成される。このとき、n
形のソース・ドレイン領域(5a’)、(6a)はn形
イオン注入領域(5) # (6)のn形不純物の横方
向拡散によってゲート絶縁膜(3)の端縁部の下へ拡が
9その拡がりdだけ横方向に広くなり、これらの領域(
5a)、(6a)の拡散深さDは深さ方向のn形不純物
の拡散によってn形イオン注入領域(5) 、 (6)
の深さよシ深くなる。FIGS. 1(A) to (D) are cross-sectional views showing the main stages of an example of a conventional MO8 type semiconductor device manufacturing method. First, as shown in FIG. 1(A), p-type silicon (Si
) Silicon oxide (81
02) After forming the film (2), p-type S1 substrate (1)
A polycrystalline Si gate layer (4) is formed on a required portion of the main surface portion surrounded by the SiO2 film (2) with a gate insulating film (3) having a thickness of about 200 to 500 layers interposed therebetween. Next, arsenic (
8) By implanting n-type impurity ions such as 1-phosphorus (P), n-type source regions are formed in the exposed portions on both sides of the polycrystalline Si gate layer (4) on the main surface of the p-type Si substrate (1). An n-type ion implantation region (5) for forming the n-type drain region and an n-type ion implantation region (6) for forming the n-type drain region are formed. Next, as shown in FIG. 1(B), a SiO3 film (2), a polycrystalline S1 gate layer (4) and an n-type ion implantation region (5) are formed.
), '(6), an 8102 film (7) for surface protection is formed by chemical vapor deposition (CVD) at a low temperature of about 700°C. Next, Figure 1 (C)
As shown in (6), the n-type ion implantation region < 5), (6) 1000
When heat treatment is performed in a high-temperature furnace at about ℃, the n-type ion implantation region (5) and the n-type ion implantation region (6)
An n-type source region (5a) and an n-type drain region (6a) are formed by diffusion of type impurities. At this time, n
The shaped source/drain regions (5a') and (6a) are formed under the edge of the gate insulating film (3) by lateral diffusion of n-type impurities in the n-type ion-implanted regions (5) # (6). 9 becomes wider laterally by its extension d, and these regions (
The diffusion depth D of 5a) and (6a) is determined by the diffusion of n-type impurities in the depth direction of the n-type ion implanted regions (5) and (6).
It gets deeper and deeper.
最後に、第1図(D) K示すように、SiO□膜(7
)のn形ソース領域(5a) 、 n形ドレイン領域(
6a)および多結晶S1ゲ一ト層(4)上の部分にこれ
らの部分を貫通してn形ソース領域(5a)、n形ドレ
イン領域(6a)および多結晶Siゲート層(4)にそ
れぞれオーミックコンタクトされたソース電極(8)、
ドレイン電極(9)およびゲート電極(10を形成する
と、この従来例の方法の作業が完了する。Finally, as shown in Figure 1 (D) K, a SiO□ film (7
) n-type source region (5a), n-type drain region (
6a) and on the polycrystalline S1 gate layer (4) through these parts to form the n-type source region (5a), the n-type drain region (6a) and the polycrystalline Si gate layer (4), respectively. Ohmic-contacted source electrode (8),
Forming the drain electrode (9) and the gate electrode (10) completes the operation of this prior art method.
ところで、この従来例の方法では、n形のソース・ドレ
イン領域(5a)、(6a)の拡散深さDが0.3μm
程度であれば、拡がシdが0.2μm程度になる。これ
によって、0.5μm程度のゲート長〔多結晶S1ゲ一
ト層(3)の幅〕の短グー)MO8形半導体素子では、
実効ゲート長〔n形のソース・ドレイン領域(5a)
、 (aa)の間の間隔〕が0.1μm程度になるので
・設計値より大幅にずれることKなシ、時にはn形のソ
ース・ドレイン領域(5a)、(6a)の間に短絡が生
ずることがある。しかも、高温炉を使用する熱処理では
、n形のソース・ドレイン領域(5a)、(6a)の1
μm以下のサブミクロンの拡散深さDを精度よく制御す
ることが極めて困難であるので、サブミクロンのゲート
長のMO8形半導体装置の製造が容易ではないという問
題があった。By the way, in this conventional method, the diffusion depth D of the n-type source/drain regions (5a) and (6a) is 0.3 μm.
If it is about 0.2 μm, the expansion width d will be about 0.2 μm. As a result, in an MO8 type semiconductor device with a gate length of about 0.5 μm (width of polycrystalline S1 gate layer (3)),
Effective gate length [n-type source/drain region (5a)
, (aa)] is about 0.1 μm, so it does not deviate significantly from the design value, and sometimes a short circuit occurs between the n-type source/drain regions (5a) and (6a). Sometimes. Moreover, in heat treatment using a high-temperature furnace, one of the n-type source/drain regions (5a) and (6a)
Since it is extremely difficult to accurately control the submicron diffusion depth D of μm or less, there has been a problem in that it is not easy to manufacture MO8 type semiconductor devices with submicron gate lengths.
この発明は、上述の問題点を解消する目的でなされたも
ので、多結晶Siゲート層をマスクにしたイオン注入法
によって多結晶Siゲート層の両側にそれぞれ形成され
たソース−ドレイン領域形成用のイオン注入領域の表面
上に表面保護用の8102膜を形成し、このS iO2
膜の全面に炭酸ガスレーザのレーザ光を短時間走査・照
射しイオン注入領域をアニールしてこの領域に注入され
ている不純物イオンの活性化を行うようにすることによ
って、サブミクロンのゲート長のMO8形半導体装置の
新規な製造方法を提供するものである。This invention was made with the aim of solving the above-mentioned problems.The present invention was made with the aim of solving the above-mentioned problems. An 8102 film for surface protection is formed on the surface of the ion implantation region, and this SiO2
By scanning and irradiating the entire surface of the film with a carbon dioxide gas laser beam for a short time to anneal the ion-implanted region and activate the impurity ions implanted in this region, MO8 with a submicron gate length can be achieved. The present invention provides a novel method for manufacturing shaped semiconductor devices.
〔発明の実施例」
第2図(A)〜(C)はこの発明の一実施例のMO8形
半導体装置の製造方法の主要段階あ状態を示す断面図で
ある。[Embodiment of the Invention] FIGS. 2(A) to 2(C) are sectional views showing main stages of a method for manufacturing an MO8 type semiconductor device according to an embodiment of the present invention.
図において、第1図に示した従来例の符号と同一符号は
同等部分を示す。In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate equivalent parts.
まず、第2図(A)に示すように、従来例の第1図(B
)に示した段階の状態と同様の状態に形成する。First, as shown in FIG. 2(A), the conventional example shown in FIG.
) to the same state as the stage shown in ).
次に、第2図(B)に示すように、5i02膜(7)の
全面に、図示矢印の方向から炭酸ガス(CO□)レーザ
の細く絞ったレーザ光を走査して照射する。このco2
ガスレーザのレーザ光は10μm程度の波長の遠赤外光
であり、この遠赤外光の10μm程度の波長域K Si
O□膜の大きな吸収ピークがあるので、co2ガスレー
ザのレーザ光の走査・照射によって5102膜(7)が
加熱される。一方、遠赤外光の10μm程度の波長域に
81基板の吸収ピークがないので、co2ガスレーザの
レーザ光の走査・照射によってこの実施例での第1導電
形の81基板であるp形S1基板(1)が加熱されない
。従って、CO2ガスレーザのレーザ光の走査・照射に
よって5iO7膜(7)のみが選択的に加熱され、p形
S1基板(1)がS i Oz脱(7)からの熱伝導に
よって加熱される。例えば、10μ!n程度の波長の0
02ガスレーザのレーザ光′!f−80μm程度の直径
に絞り数ミIJ秒間S iO2膜(7)の全面に走査し
照射すると、SiO3膜(7)の温度は1500′C程
度になるが、p形S1基板(1)の温度は1000′C
程度である。これによって、p形S1基板(1)の主面
部のこの実施例での第2導電形のソース・ドレイン領域
形成用イオン注入領域であるn形イオン注入領域(5)
、 (6)が形成されS x O2膜(7)と接する
部分に1000℃程度の高温の熱処理が&ミIJ秒間施
されたことになり、n形イオン注入領域(5) 、 (
0)に注入され−Cいるn形不純物イオンが活性化され
てこの実施例の第2導電形のソース・ドレイン領域であ
るn形のソース・ドレイン領域(5a)、(6a)が形
成される。このとき、n形イオン注入領域(5)、(6
)内のn形不純物の拡散は、これらのn形イオン注入領
域(5) 、 (6)に施される熱処理時の温度と時間
との関数であるが、レーザ光の走査Φ照射時間を数ミリ
秒程度の短時間にすることができるので、このような短
時間の走査・照射では不純物の拡散がほとんど行われず
、n形のソース・ドレイン領域(5a)。Next, as shown in FIG. 2(B), the entire surface of the 5i02 film (7) is scanned and irradiated with narrowly focused laser light from a carbon dioxide (CO□) laser from the direction of the arrow in the figure. This co2
The laser light of the gas laser is far-infrared light with a wavelength of about 10 μm, and the wavelength range of this far-infrared light is about 10 μm.
Since the O□ film has a large absorption peak, the 5102 film (7) is heated by scanning and irradiation with the laser light of the CO2 gas laser. On the other hand, since there is no absorption peak of the 81 substrate in the wavelength range of about 10 μm of far-infrared light, the p-type S1 substrate, which is the 81 substrate of the first conductivity type in this example, is scanned and irradiated with the laser light of the CO2 gas laser. (1) is not heated. Therefore, only the 5iO7 film (7) is selectively heated by scanning and irradiation with the laser light of the CO2 gas laser, and the p-type S1 substrate (1) is heated by heat conduction from the SiOz desorption (7). For example, 10μ! 0 of wavelength of about n
02 Gas laser laser beam'! When the entire surface of the SiO2 film (7) is scanned and irradiated to a diameter of about f-80 μm for several milliJ seconds, the temperature of the SiO3 film (7) becomes about 1500'C, but the temperature of the p-type S1 substrate (1) increases. The temperature is 1000'C
That's about it. As a result, an n-type ion implantation region (5), which is an ion implantation region for forming a source/drain region of the second conductivity type in this embodiment, is formed on the main surface of the p-type S1 substrate (1).
, (6) was formed and the part in contact with the S x O2 film (7) was subjected to high-temperature heat treatment of about 1000°C for &miIJ seconds, resulting in the n-type ion implantation region (5), (
The -C n-type impurity ions implanted in 0) are activated to form n-type source/drain regions (5a) and (6a), which are the second conductivity type source/drain regions of this embodiment. . At this time, n-type ion implantation regions (5), (6
) is a function of the temperature and time during the heat treatment applied to these n-type ion-implanted regions (5) and (6). Since the scanning and irradiation can be performed for a short period of time on the order of milliseconds, impurities are hardly diffused in the n-type source/drain region (5a).
□
(6a)の拡散深さはn形イオン注入領域(5) 、
(6)の深さとほとんど同一であり、横方向拡散による
拡がりもほとんどない。□ The diffusion depth of (6a) is the n-type ion implantation region (5),
The depth is almost the same as (6), and there is almost no spread due to lateral diffusion.
最後に、第2図(C)に示すように、従来例の第1図(
D)に示した段階と同様に、n形ソース領域(5a)。Finally, as shown in Figure 2 (C), the conventional example shown in Figure 1 (
n-type source region (5a), similar to the stage shown in D).
n形ドレイン領域(6a)および多結晶S1ゲ一ト層(
4)にそれぞれオーミックコンタクトされたソース%i
極f8) 、ドレイン電極(9)およびゲート電極(
10を形成すると、この実施例の方法の作業が完了する
。n-type drain region (6a) and polycrystalline S1 gate layer (
4) Sources %i in ohmic contact with each
pole f8), drain electrode (9) and gate electrode (
10 completes the operation of the method of this example.
このように、この実施例の方法では、CO。ガスレーザ
のレーザ光をSiO□膜(7)の全面に数ミリ秒程度の
短時間走査し照射することによってn形イオン注入領域
(5) 、 ((i)をアニールしこれらの領域(5)
。Thus, in the method of this example, CO. By scanning and irradiating the entire surface of the SiO□ film (7) with a laser beam from a gas laser for a short period of several milliseconds, the n-type ion implanted regions (5) and ((i) are annealed and these regions (5)
.
(6)に注入されているn形不純物イオンの活性化を行
うことができるので、n形イオン注入領域(5)。Since the n-type impurity ions implanted in (6) can be activated, the n-type ion implantation region (5).
(6)内のn形不純物の深さ方向および横方向の拡散を
ほとんどないようにすることができる。従って、ゲート
長を多結晶シリコンゲート層(4)の幅とII lr同
一にすることができるので、サブミクロンのゲート長を
容易に作成することができる。Diffusion of the n-type impurity in (6) in the depth direction and the lateral direction can be almost eliminated. Therefore, since the gate length can be made the same as the width of the polycrystalline silicon gate layer (4), a submicron gate length can be easily created.
なお、この実施例の第2図(B)に示した段階において
p形Si基板(1)を水などの冷却剤を用いて冷却する
ようにしてもよい。この場合には、p形S1基板(1)
を所要温度以上にならないようにすることができる。Note that the p-type Si substrate (1) may be cooled using a coolant such as water at the stage shown in FIG. 2(B) of this embodiment. In this case, p-type S1 substrate (1)
It is possible to prevent the temperature from rising above the required temperature.
また、この実施例では、p形Si基板(1)を用いる場
合について述べたが、この発明はこれに限らず、n形S
1基板を用いる場合にも適用することができる。この場
合には、この実施例におけるp影領域をn影領域にし、
n影領域をp影領域にすればよい。Further, in this embodiment, a case has been described in which a p-type Si substrate (1) is used, but the present invention is not limited to this, and the n-type Si substrate (1) is used.
It can also be applied when using one substrate. In this case, the p shadow area in this example is changed to an n shadow area,
The n shadow area may be changed to the p shadow area.
以上、説明したように、この発明のλqos形半導体装
置の製造方法では、多結晶Siゲート層をマスクにした
イオン注入法によって多結晶S1ゲ一ト層の両側にそれ
ぞれ形成されたソース・ドレイン領域形成用のイオン注
入領域の表面上に表面保護用のSiO□膜を形成し、こ
の8i0□膜の全面に炭酸ガスレーザのレーザ光を短時
間走査・照射しイオン注入領域をアニールしてこの領域
に注入されている不純物イオンの活性化を行うので、イ
オン注入領域内の不純物の深さ方向および横方向の拡散
をほとんどないようにすることができる。従って、ゲー
ト長を多結晶Siゲート層の幅とほぼ同一にすることが
できるので、サブミクロンのゲート長を容易に作成する
ことができる。As described above, in the method for manufacturing a λqos type semiconductor device of the present invention, source and drain regions are formed on both sides of a polycrystalline S1 gate layer by ion implantation using a polycrystalline Si gate layer as a mask. A SiO□ film for surface protection is formed on the surface of the ion-implanted region for formation, and the entire surface of this 8i0□ film is scanned and irradiated with a carbon dioxide gas laser beam for a short time to anneal the ion-implanted region. Since the implanted impurity ions are activated, diffusion of the impurities in the depth direction and the lateral direction within the ion implantation region can be almost prevented. Therefore, since the gate length can be made almost the same as the width of the polycrystalline Si gate layer, a submicron gate length can be easily created.
第1図は従来のMO8形半導体装置の製造方法の一例の
主要段階の状態を順次示す断面図、第2図はこの発明の
一実施例のMO8形半導体装置の製造方法の主要段階の
状態を順次示す断面図である。
図において、(1)はp形シリコン基板(第1導電形の
シリコン基板)、(2)は素子間分離用酸化シリコン膜
、(3)はゲート絶縁膜、(4)は多結晶シリコンゲー
ト層、(5)および(6)はそれぞれn形ソース領域形
成用のn形イオン注入領域およびn形ドレイン領域形成
用のn形イオン注入領域(第2導電形のソース・ドレイ
ン領域形成用イオン注入領域)、(5a)および(6a
)はそれぞれn形ソース領域およびn形ドレイン領域(
第2導電形のソース・ドレイン領域) 、(7)は表面
保獲用酸化シリコン膜であるO
なお、図中同一符号はそれぞれ同−咬たは相当部分を示
す。
代理人 大 岩 増 ノ、11゜
第1図
第2図
(A)
(B)
(e)FIG. 1 is a cross-sectional view sequentially showing the state of the main stages of an example of a conventional method for manufacturing an MO8 type semiconductor device, and FIG. 2 shows the state of the main stages of a method for manufacturing an MO8 type semiconductor device according to an embodiment of the present invention It is sectional drawing shown sequentially. In the figure, (1) is a p-type silicon substrate (first conductivity type silicon substrate), (2) is a silicon oxide film for element isolation, (3) is a gate insulating film, and (4) is a polycrystalline silicon gate layer. , (5) and (6) are respectively an n-type ion implantation region for forming an n-type source region and an n-type ion implantation region for forming an n-type drain region (an ion implantation region for forming a second conductivity type source/drain region). ), (5a) and (6a
) are the n-type source region and n-type drain region (
Source/drain regions of the second conductivity type) and (7) are silicon oxide films for surface preservation. In the drawings, the same reference numerals indicate the same or corresponding parts, respectively. Agent Masu Oiwa, 11゜Figure 1Figure 2 (A) (B) (e)
Claims (2)
導体素子を形成すべき部分以外の部分に素子間分離用酸
化シリコン膜を形成する工程、上記シリコン基板の主面
部の上記素子間分離用酸化シリコン膜によって取り囲ま
れた部分の所要部分上にゲート絶縁膜を介して多結晶シ
リコンゲート層を形成する工程、上記素子間分離用シリ
コン膜および上記多結晶シリコンゲート層をマスクにし
て上記シリコン基板の主面部に第2導電形の不純物イオ
ンを注入して第2導電形のソース・ドレイン領域形成用
イオン注入領域を形成する工程、上記素子間分離用酸化
シリコン膜、上記多結晶シリコンゲート層および上記ソ
ース・ドレイン領域形成用イオン注入領域の表面上にわ
たって表面保獲用酸化シリコン膜を形成する工程、並び
に上記表面保護用酸化シリコン膜の全面に炭酸ガスレー
ザのレーザ光を走査・照射して上記ソース・ドレイン領
域形成用イオン注入領域をアニールしこの領域に注入さ
れている不純物イオンを活性化して第2導電形のソース
・ドレイン領域を形成する工程を備えたMO8形半導体
装置の製造方法。(1) A step of forming a silicon oxide film for element isolation on a main surface portion of a first conductivity type silicon substrate other than a portion where an MO8 type semiconductor element is to be formed; a step of forming a polycrystalline silicon gate layer via a gate insulating film on a required portion of the portion surrounded by the silicon oxide film, using the silicon film for element isolation and the polycrystalline silicon gate layer as a mask; a step of implanting impurity ions of a second conductivity type into the main surface of the substrate to form ion implantation regions for forming source/drain regions of the second conductivity type, the silicon oxide film for element isolation, and the polycrystalline silicon gate layer. and a step of forming a silicon oxide film for surface protection over the surface of the ion implantation region for forming source/drain regions, and scanning and irradiating the entire surface of the silicon oxide film for surface protection with a laser beam of a carbon dioxide laser. A method for manufacturing an MO8 type semiconductor device, comprising the steps of annealing an ion implantation region for forming a source/drain region and activating impurity ions implanted in this region to form a source/drain region of a second conductivity type.
、シリコン基板を冷却することを特徴とする特許請求の
範囲第1項記載のMO8形半導体装置の製造方法。(2) The method for manufacturing an MO8 type semiconductor device according to claim 1, wherein the silicon substrate is cooled in the step of forming the source/drain regions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21532683A JPS60106174A (en) | 1983-11-14 | 1983-11-14 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21532683A JPS60106174A (en) | 1983-11-14 | 1983-11-14 | Manufacture of mos semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60106174A true JPS60106174A (en) | 1985-06-11 |
Family
ID=16670443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21532683A Pending JPS60106174A (en) | 1983-11-14 | 1983-11-14 | Manufacture of mos semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60106174A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0699213A (en) * | 1992-09-21 | 1994-04-12 | Kotobuki Sangyo Kk | Roller guide |
-
1983
- 1983-11-14 JP JP21532683A patent/JPS60106174A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0699213A (en) * | 1992-09-21 | 1994-04-12 | Kotobuki Sangyo Kk | Roller guide |
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