JPH0653157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with high packing density, in which shallow junctions are formed, gate-drain breakdown strength is prevented from degradation, and gate leakage current is decreased. CONSTITUTION:A method of manufacturing a semiconductor device comprises the step carrying out furnace annealing or rapid thermal annealing after formation of isolation regions 2, gate electrode regions 8, and lightly doped regions 9 and the step of carrying out pulsed laser annealing after formation of source and drain regions 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing various semiconductor devices such as field effect transistors and bipolar transistors.

[0002]

2. Description of the Related Art In the manufacturing process of semiconductor devices in various LSIs (Large Scale Integrated Circuits), that is, semiconductor devices in which a plurality of semiconductor elements are formed on the same semiconductor substrate, various types of semiconductor elements are used to separate or connect the semiconductor elements. High temperature heat treatment is performed. Further, in a semiconductor device such as a MOSFET (metal-oxide film-semiconductor field effect transistor), an LDD (Lightly Doped Drain) structure and a source / drain region are formed, and in a semiconductor device such as a bipolar transistor, a base region, an emitter. Ion implantation is performed to form regions and the like, and after the ion implantation, annealing treatment (hereinafter referred to as “annealing treatment”) is performed to recover the crystallinity of the semiconductor substrate and electrically activate the implanted acceptor ions and donor ions. It is necessary to carry out an activation annealing treatment).

Furthermore, in order to reduce the contact resistance, a high temperature heat treatment of a silicide layer which is a compound layer of Si with a metal such as refractory metal (W, Mo, Ti, etc.) or Pt, Pd is required. Is. Conventionally, furnace annealing and rapid thermal annealing (RTA) have been adopted as the activation annealing treatment and the high temperature heat treatment.

On the other hand, as the integration of semiconductor devices progresses, individual semiconductor elements are reduced in size, and shallow junctions are required in the source / drain regions or the emitter regions.
When the furnace annealing or the activation annealing treatment by the RTA described above is performed, the diffusion layer becomes deep and the junction between the source / drain region and the emitter region is made shallow to satisfy the requirement that the semiconductor element is miniaturized and highly integrated. I can't. Therefore, an activation annealing method by pulsed laser irradiation has been proposed as one of methods for forming a shallow junction.

[0005]

Since the energy of the pulsed laser is absorbed on the very surface (about 20 nm) of the semiconductor substrate, the depth at which the annealing can be performed by the pulsed laser takes into consideration the thermal diffusion. It becomes about 100 nm or less. Therefore, the annealing process by the pulse laser is shallow L
It is suitable for the activation annealing treatment when forming the DD structure emitter region or the source / drain region.

However, when the LDD concentration profile has a steep abrupt distribution, there is a problem that the gate leakage current of the transistor increases as compared with a gentle Gaussian distribution (for example, "Next Generation VLSI Process Technology (edited by M. Takase, Hirose). , Realize Co., Ltd.) ”, pp. 69-70).
Such a problem seems to be the same also in the junction between the base region and the collector region in a bipolar transistor, for example.

In order to solve this problem, it is conceivable to increase the laser power to deeply diffuse the acceptor ions and donor ions in the LDD region and the base region, but the junctions in the source / drain region and the base region become deeper. There is a problem. Further, when the laser power is low, only the very surface of the semiconductor substrate is melted, and then the surface of the semiconductor substrate becomes flat immediately. However, when the power of the laser is large, the semiconductor substrate is melted to a considerably deep portion, so that there is a problem that the flatness of the surface of the semiconductor substrate is significantly impaired.

An object of the present invention is to provide a semiconductor device manufacturing method capable of forming a shallow junction in a fine semiconductor device and reducing the gate leak current or the base-collector leak current of a transistor.

[0009]

A method of manufacturing a semiconductor device according to the present invention includes a device isolation region 2, a gate electrode region 8 and a low concentration impurity implantation region 9 as shown in FIGS. That is, after forming a so-called LDD structure, a step of performing furnace annealing or RTA (rapid thermal annealing), and after forming the source / drain regions 12,
And a step of performing a pulse laser annealing process.

Further, as shown in FIGS. 2A to 2E and FIGS. 3A to 3D, manufacturing process diagrams of an example of a method for manufacturing a semiconductor device of the present invention are
Element isolation region 29, collector region 31, and base region 3
3 is formed, furnace annealing or RTA is performed, and after the emitter region 36 is formed, pulse laser annealing is performed.

[0011]

According to the present invention described above, as shown in FIGS. 1A to 1C, after the element isolation region 2 and the gate electrode region 8 are formed, the low concentration impurity implantation region 9 is formed, and a so-called LDD structure is formed. By performing furnace annealing or RTA, the conductive layer and the underlayer formed in these regions having a relatively large thickness are electrically activated, and the impurity distribution in the low-concentration impurity implantation region 9 is made relatively gentle. Gaussian distribution can be obtained, deterioration of breakdown voltage between the gate electrode and the substrate can be suppressed, and leak current can be reduced. Further, a uniform low resistance silicide layer can be formed on the gate electrode region 8.

According to another aspect of the present invention, as shown in FIGS. 2A to 2E and 3A to 3D, after forming the element isolation region 29, the collector region 31 and the base region 33, furnace annealing or RTA is performed. As a result, the impurity distribution in the base region 33 can be set to a relatively gentle Gaussian distribution, and the deterioration of the breakdown voltage between the base and the collector can be suppressed.
Leakage current can be reduced.

Further, in the present invention, the activation treatment of the source / drain region 12 or the emitter region 36 is performed by pulse laser annealing, and the semiconductor is controlled by controlling the energy density, the number of pulses and the irradiation time. It is possible to maintain a shallow junction having a depth of, for example, 100 nm or less from the surface of the substrate, and it is possible to manufacture a fine semiconductor device.

[0014]

EXAMPLE 1 In this example, the present invention is applied to manufacture of a MOSFET. The important point here is that the LDD region is formed before the step of pulsed laser irradiation for activation in the source / drain regions, and furnace anneal or RTA is performed to make the impurity distribution of the LDD region a Gaussian distribution. Is.

Then, the heat treatment after the pulse laser irradiation step for activation in the source / drain regions is performed 60 times.
It is to be 0 ° C or lower. That is, if the heat treatment at more than 600 ° C. is performed, the junction in the LDD structure or the source / drain region becomes deep. As a case where a heat treatment is required in a later step, there is a sintering process when forming an Al wiring layer, and the processing temperature at this time is about 450 ° C to 600 ° C.

An example of a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the drawings. First, as shown in FIG. 1A, an element isolation region 2 is formed on a semiconductor substrate 1 made of Si or the like by selective thermal oxidation or the like. A channel stop ion implantation layer 3 is formed below the element isolation region 2. Next, after forming the gate oxide film 4, the threshold voltage adjusting ion implantation layer 5 is formed. Then, after covering the gate oxide film 4 with the gate polysilicon layer 6, a silicide layer 7 is formed, and the silicide layer 7, the gate polysilicon layer 6 and the gate oxide film 4 are etched to form a gate electrode region 8. .

After that, impurities are implanted at a low concentration over the entire surface to form a low concentration impurity implantation region 9 so-called LDD structure as shown in FIG. 1B. Then, a furnace annealing process or an RTA process for activating each layer, reducing the resistance of the silicide layer 6, and forming a Gaussian distribution of impurities in the low-concentration impurity implantation region 9 is performed. In this embodiment, RT
A treatment was performed and the condition was 1050 ° C. and 10 seconds.

Further, an insulating layer of SiO ₂ or the like is entirely deposited on the entire surface, and anisotropic etching such as RIE (reactive ion etching) is performed to form an insulating layer, as shown in FIG. 1C. Sidewalls 1 on both sides of the gate electrode region 8
1 is formed, and ion implantation is performed using the gate electrode region 8 and the side wall 11 as a mask to form a source / drain region (S / D region) 12. Thereafter, if necessary, an oxide film 13 having a thickness of about 50 nm is formed as a reflection preventing film by a CVD (chemical vapor deposition) method or the like, and a pulse laser is entirely irradiated as indicated by an arrow L to thereby form the source / drain regions. The ions implanted in 12 are activated. The conditions of the activation annealing treatment by the pulse laser are
For example, a XeCl laser was used, the irradiation energy density was 700 mJ / cm ² , and the pulse width was 44 ns.

The conditions for the furnace anneal are a temperature of 850 ° C. and 1
It is desirable that the temperature is 150 ° C., more preferably 950 ° C. to 1050 ° C., and the treatment time is 10 to 30 minutes. Alternatively, it is desirable that the RTA condition is a temperature of 850 ° C. to 1150 ° C., more preferably 1000 ° C. to 1150 ° C., and a treatment time of 2 to 10 seconds.

In the pulse laser annealing, ruby laser (wavelength: 694 nm), XeF (wavelength: 351n)
m), XeCl (wavelength: 308 nm), KrF (wavelength:
Lasers such as 249 nm) and ArF (wavelength: 193 nm) can be used. For example, as shown in FIG. 4 showing the wavelength dependence of the absorption coefficient of Si, XeF laser, XeC laser, etc.
In the wavelength region of the 1 laser, the absorption coefficient of the Si single crystal shown by the solid line a and that of the Si single crystal ion-implanted with boron B shown by the broken line b are almost equal. Therefore, when B is injected as an impurity, a XeF laser or XeCl laser is used. It is desirable to use a laser.

The irradiation energy at the pulse laser annealing is 650 mJ / cm ^{2 to} 1100 mJ / cm ² , more preferably 700 mJ / cm ^{2 to} 900 mJ / cm ^2.
Is desirable. Pulse width is 20ns-100n
s is preferable, and the pulse irradiation interval can be arbitrarily selected.

After that, the interlayer insulating layer,
By forming a wiring layer or the like, the impurity concentration distribution in the low-concentration impurity implantation region 9 has a gentle Gaussian distribution to suppress deterioration of the breakdown voltage between the gate electrode and the substrate, and at the same time reduce the leakage current. , Source / drain region 1
In 2, it is possible to form a MOSFET semiconductor device in which a shallow junction is maintained and miniaturization is possible. When the wiring layer is sintered, the heat treatment is performed at 600 ° C.
It is important to do the following:

Example 2 In this example, the present invention is applied to the manufacture of a bipolar transistor. Also in this case, the important point is that the base region is formed before the step of pulsed laser irradiation for activation in the emitter region and furnace annealing or RTA is performed to make the impurity distribution of the base region Gaussian. Further, the heat treatment after the pulse laser irradiation step for activation in the emitter region is set to 600 ° C. or lower in order to keep the junction shallow.

An example of the method of manufacturing the semiconductor device of the present invention will be described in detail below with reference to the drawings. First, as shown in FIG. 2A, an oxide film 22 is formed on the surface of, for example, a p-type semiconductor substrate 21 made of Si or the like, an opening is provided in a predetermined region by applying photolithography or the like, and the oxide film 22 is used as a mask. For example, n-type impurities are implanted at a high concentration to form the collector buried region 23. As the impurity, Sb or As having a small diffusion constant is used so that the impurity does not spread much in the subsequent heat treatment.

Then, as shown in FIG. 2B, after the oxide film 22 is removed, epitaxial growth is performed to form an n-type silicon single crystal layer 24 with a total thickness of, for example, several μm, and the surface is further thinned. An insulating layer 25 of SiO ₂ or the like is entirely formed by oxidation or the like, and an insulating layer 26 of Si ₃ N ₄ or the like serving as a mask for selective oxidation is entirely formed by a CVD method or the like.

Next, as shown in FIG. 2C, patterning is performed to form a so-called element isolation region by selective oxidation, and the Si ₃ N ₄ insulating layer 26, the SiO ₂ insulating layer 25 and the silicon single crystal layer 24 are etched. The recess 27 is formed in the element isolation region forming portion.

Then, in order to ensure the separation, p of B etc.
A type impurity is implanted at a high concentration and annealing for preventing defect generation is performed to form a channel prevention region 28 as shown in FIG. 2D, and then selective oxidation is performed to form an element isolation region 29.

After that, Si ₃ N used as a mask for selective oxidation
_{4 The} insulating layer 26 is removed, and using the resist 30 formed by application of photolithography or the like as a mask, n-type impurities such as phosphorus P are selectively implanted into the collector region 31 as shown by an arrow A to diffuse, Aim to reduce collector resistance.

Next, as shown in FIG. 3A, with the resist 32 formed by application of photolithography or the like as a mask, a p-type impurity such as B is selectively implanted at a high concentration as shown by an arrow B to form a base. A region 33 is formed. After this,
By RTA or furnace anneal, eg RTA in this case
The activation process is performed by.

Then, as shown in FIG. 3B, the resist 32
Then, an insulating layer 35 such as PSG (phosphorus silicate glass) is deposited over the entire surface, and then an emitter region 36 is formed.
Is selectively implanted with a high concentration of p-type impurities such as As. After this, an antireflection film 37 such as SiO _{2 is formed on the} entire surface.
Is formed to have a thickness of about 50 nm and pulsed laser is irradiated on the entire surface as indicated by an arrow E to activate the ions implanted in the emitter region 36.

Then, as shown in FIG. 3C, a resist 38 is patterned by applying photolithography or the like, and each collector region 31,
An opening is formed on the base region 33 and the emitter region 37.

Then, for example, Al is vapor-deposited on the entire surface, and electrodes and wiring are processed by applying photolithography or the like to form a collector electrode 40, an emitter electrode 41 and a base electrode 42, respectively. It is important to set the heat treatment temperature to 600 ° C. or lower in the subsequent steps such as sintering of the electrode.

Even in this case, the furnace annealing condition is that the temperature is 850 ° C. to 1150 ° C., more preferably 95 ° C.
It is desirable that the temperature be 0 ° C. to 1050 ° C. and the treatment time be 10 to 30 minutes. Alternatively, RTA conditions of 850 ° C to 11
A temperature of 50 ° C., more preferably 1000 ° C. to 1150 ° C., and a treatment time of 2 to 10 seconds are desirable.

For pulse laser annealing, lasers such as ruby laser, XeF, XeCl, KrF and ArF can be used. The irradiation energy during pulse laser annealing is 650 mJ / cm ^{2 to} 1100 mJ.
/ Cm ² , more preferably 700 mJ / cm ^{2 to} 900
It is desirable to set it to mJ / cm ² . Pulse width is 20n
It is preferably about s to 100 ns, and the pulse irradiation interval can be arbitrarily selected.

By doing so, the impurity distribution in the base region can be made a gentle Gaussian distribution, the electric field concentration between the base region and the collector region is relaxed, the breakdown voltage is suppressed from being deteriorated, and the leak current is reduced. Can be converted. Further, in this case, since the emitter region is activated by the pulse laser treatment, a shallow junction can be maintained, and particularly in a fine bipolar transistor semiconductor device having a junction depth of 0.2 μm or less for high frequency (high speed), It is possible to obtain the effects such as the breakdown voltage deterioration and the low leakage current.

It is needless to say that the present invention is not limited to the above-described embodiments, but various modifications and changes can be made, for example, the conductivity type thereof is opposite to that shown in the drawing.

[0037]

According to the present invention described above, in the field effect transistor, the impurity distribution of the low-concentration impurity-implanted region 9 forming the LDD structure can be set to a relatively gentle Gaussian distribution, and the gate electrode-substrate structure can be obtained. It is possible to suppress the deterioration of the breakdown voltage and reduce the leak current. Also,
A uniform low-resistance silicide layer can be formed on the gate electrode region 8.

According to another aspect of the present invention, in the bipolar transistor, the impurity distribution in the base region 33 can be set to a relatively gentle Gaussian distribution, the breakdown voltage between the base and the collector can be prevented from deteriorating, and the leakage current can be suppressed. Can be reduced.

Further, in the present invention, the activation treatment of the source / drain region 12 or the emitter region 36 is performed by pulse laser annealing, and the semiconductor is controlled by controlling the energy density, the number of pulses and the irradiation time. For example, a shallow junction having a depth of about 100 nm or less can be reliably formed from the surface of the base body, and an ultrahigh-speed integrated circuit including minute transistors can be formed.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a manufacturing process diagram of an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram of an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a diagram showing wavelength dependence of a light absorption coefficient of silicon.

[Explanation of symbols]

 1 semiconductor substrate 2 element isolation region 3 channel stop ion implantation layer 4 gate oxide film 5 threshold voltage adjusting ion implantation layer 6 gate polysilicon layer 7 gate silicide layer 8 gate electrode region 9 low concentration impurity implantation region 12 source / drain region 13 Antireflection Film 21 Semiconductor Substrate 23 Collector Embedded Region 28 Channel Prevention Region 29 Element Separation Region 31 Collector Region 33 Base Region 36 Emitter Region 40 Collector Electrode 41 Emitter Electrode 42 Base Electrode

Claims (2)

[Claims] 1. A step of performing furnace annealing or rapid thermal annealing after forming an element isolation region, a gate electrode region and a low-concentration impurity implantation region, and a step of performing pulse laser annealing treatment after forming source / drain regions. A method of manufacturing a semiconductor device, comprising: 2. A step of performing furnace annealing or rapid thermal annealing after forming the element isolation region, the collector region and the base region, and a step of performing pulse laser annealing treatment after forming the emitter region. And a method for manufacturing a semiconductor device.