JPH0815215B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION [Outline] In a method of manufacturing a short channel MIS semiconductor device in which a shallow p-type region is formed by a combination of boron difluoride (BF ₂ ) ion implantation and lamp annealing, BF ₂ ions are used. Implantation is performed shallowly through a thermal oxide film formed on a silicon substrate so as not to damage the substrate surface, and after removing the thermal oxide film, the ion implantation region is subjected to a high-temperature lamp annealing treatment for a short time. Activated without segregation of fluorine molecules on the surface, shallow p with small surface leakage current
Form a mold region.

[Industrial applications]

The present invention relates to a semiconductor device manufacturing method, and more particularly to an improvement in a shallow p-type region forming method.

In MISIC, the channel length is being gradually reduced in order to prevent the decrease in operating speed due to high integration, and the source / drain is formed as shallow as possible in order to prevent the short channel effect caused by this. Will be needed.

Therefore, as a method of forming shallow source / drain regions, a shallow impurity-implanted region is formed by ion-implanting impurities into the semiconductor substrate surface through an insulating film, and only the substrate surface is rapidly heated to high temperature by infrared irradiation from a lamp. The lamp annealing method described above provides a method of suppressing the expansion of the impurity-implanted region and activating it.

However, when boron (B) which is usually used as a p-type impurity in the above method is used, the range of boron (B) in ion implantation is significantly longer than that of arsenic (As) which is an n-type impurity. As a result, a shallow ion-implanted region similar to arsenic cannot be formed, which makes it difficult to form a shallow p-type source / drain region similar to the n-type source / drain region.

Therefore, shallow p-type source / drain regions are formed by using boron difluoride (BF ₂ ) molecules, which have a mass closer to arsenic (As) than boron (B), as p-type impurities. However, in this case, there is a tendency for surface leakage to occur at the junction and the device characteristics to deteriorate, and improvement is desired.

[Conventional technology]

When shallow p-type source / drain regions are formed by the combination of the above BF ₂ ion implantation and the lamp annealing method,
Conventionally, the following method has been performed.

That is, as shown in FIG. 3A, the n ⁻ -type silicon (Si) substrate 1 is separately exposed by the field oxide film 2 and the n-type channel stopper 3 under the field oxide film 2 which are formed by a normal method. A thickness of 200 on the element formation region 4 due to the thermal oxidation method.
A gate oxide film 5 of about 300 Å is formed, a polycrystalline silicon (poly-Si) layer is grown on the substrate, impurities are applied to the poly-Si layer at a high concentration to impart conductivity, and a resist is used as usual. The poly-Si layer is patterned using the pattern 6 as a mask to form a Si gate electrode 7.

Then, as shown in FIG. 3 (b), the resist pattern 6 and the field oxide film 2 are used as a mask to remove 40 to 50 Ke
N ⁻ type S through the gate oxide film 5 with implantation energy of about V
BF ₂ ⁺ is selectively ion-implanted into the surface of the i substrate. The position of the peak concentration of BF ₂ ⁺ injected here is formed at a depth of about 500Å. In addition, 108 and 109 indicate BF ₂ ⁺ implantation regions.

Then, after removing the resist pattern 6, the surface of the element forming region 4 is subjected to a lamp annealing technique performed by irradiating the substrate surface with high-energy infrared rays (IR) obtained by collecting infrared rays emitted from an infrared lamp. 900 to 1000
The BF ₂ ⁺ implantation regions 108 and 109 are heated without being enlarged and heated to about ℃ for several seconds to form shallow p ⁺ type source regions 8 and p ⁺ type drain regions 9 as shown in FIG. 3C. Was the way to do it.

However, according to the conventional method, BF ₂ ⁺ implantation regions 108 and 109 are formed.
At the time of activation, the thermal oxide film formed on the BF ₂ ⁺ implantation region 108, that is, the gate oxide film 5 and the fluoride ion (F ⁺ ) have an extremely high affinity, so that the inside of the BF ₂ ⁺ implantation regions 108 and 109 is The position of the peak concentration in the F ⁺ concentration profile included in is moved by being pulled to the surface portion of the Si substrate 1, that is, the source 8 and the drain region 9.

The movement state of the F ⁺ concentration profile is shown in FIG. 4, the curve S is the initial concentration profile immediately after implantation, and the curve B is the concentration profile after lamp annealing. In the figure, SiO ₂ corresponds to a thermal oxide film, that is, a gate oxide film, a Si substrate corresponds to the source and drain regions, and a surface with a depth of 0 is the Si.
The surface of the substrate is shown.

As shown in this figure, the F ⁺ on the surface is absorbed in the thermal oxide film (gate oxide film), and the peak concentration position (▲ C ^max _max ▼) of the F ⁺ concentration profile is determined by lamp annealing. That is, it moves to the vicinity of the surface of the source and drain regions. This figure is drawn from the results of Sims analysis.

The increase in the surface concentration of F ⁺ increases the surface level on the source and drain regions, which causes
There is a problem that surface leakage occurs in the drain junction and the performance of the short channel MIS semiconductor device is impaired.

[Problems to be solved by the invention]

The problem to be solved by the present invention is that the above-mentioned conventional ▲ BF
² ₂ ▼ Shallow p by ion implantation and lamp annealing means
In a short channel MIS semiconductor device using the method of forming the mold region, the high concentration of the high concentration existing on the surface of the p-type region
This is because the increase in the interface state due to F ⁺ increased the surface leak of the p-type region junction and caused the performance deterioration.

[Means for solving problems]

The problem is that a thermal oxide film is formed on an n-type silicon substrate, boron difluoride is ion-implanted into the silicon substrate through the thermal oxide film, and then the thermal oxide film is removed. A method of manufacturing a semiconductor device according to the present invention includes a step of activating a region into which boron difluoride is ion-implanted by light irradiation heating to form a p-type region.

[Work]

That is, in the method of the present invention, a lamp annealing treatment for activating the ion-implanted region of the BF ₂ ^+, (for transmission) through the time of BF ₂ ⁺ implantation on BF ₂ ⁺ implantation region used as oxide film By removing the oxide film and exposing the BF ₂ ⁺ implantation region surface, the F ⁺ concentration distribution in the BF ₂ ⁺ implantation region is prevented from moving toward the surface due to activation,
The F ⁺ concentration on the surface of the formed p-type region is significantly reduced as compared with the conventional case.

As a result, the surface level due to F ⁺ in the shallow p-type region formed by the above BF ₂ ⁺ ion implantation and lamp annealing means is greatly reduced as compared with the conventional one, and the surface leak of the p-type region is greatly reduced. The performance of the short-channel p-channel MIS semiconductor device formed using the p-type region is improved.

〔Example〕

Hereinafter, the present invention will be specifically described with reference to the drawings and embodiments.

1 (a) to 1 (e) are process cross-sectional views showing one embodiment of the method of the present invention, and FIG. 2 is a profile diagram of F ⁺ concentration in the same embodiment.

 The same object is denoted by the same reference numeral throughout the drawings.

See FIG. 1 (a). Short channel type p channel by the method of the present invention.
When forming the MIS transistor, as in the conventional case, the thickness of the n ⁻ type Si substrate 1 is separated and exposed by the thermal oxidation method by the field oxide film 2 and the n type channel stopper 3 thereunder. Form a gate oxide film 5 having a thickness of about 200 to 300Å, grow a poly-Si layer on the substrate, and introduce impurities into the poly-Si layer at a high concentration to impart conductivity.
The polySi layer is patterned using the resist pattern 6 as a mask to form a polySi gate electrode 7.

See FIG. 1 (b). Then, using the resist pattern 6 and the field oxide film 2 as a mask, the gate oxide film 5 is passed through 40 to 50 Ke.
Boron difluoride (BF ₂ ⁺ ) with a dose amount of about 2 × 10 ¹⁵ is selectively ion-implanted into the surface of the substrate 1 in the element formation region 4 with an implantation energy of about V 2. The peak concentration position in the concentration profile of the BF ₂ ⁺ implantation regions 108 and 109 formed by this ion implantation is formed at a depth of about 500 Å from the surface of the substrate 1.

At this time, the concentration profile of free fluorine ions (F ⁺ ) contained in the BF ₂ ⁺ implantation regions 108 and 109 is also the same as that of BF ₂ ⁺ .

1C, after removing the resist pattern 6, the gate oxide film 5 on the BF ₂ ⁺ implantation regions 108 and 109 is removed by a normal wet etching method using a mixed solution of hydrofluoric acid and nitric acid.
The upper surfaces of the BF ₂ ⁺ implantation regions 108 and 109 are exposed.

See FIG. 1 (d). Then, the BF ₂ ⁺ implantation regions 108 and 109 are heated to 900 to 1000 ° C. by the lamp annealing method in which infrared rays of high illuminance are irradiated as in the conventional case.
It is heated for about a few seconds and activated to a depth of about 1000Å
A p ⁺ type source region 8 and a p ⁺ type drain region 9 are formed.

As shown in FIG. 1 (e), an impurity blocking oxide film 10 is formed as usual, and an interlayer insulating film 11 made of phosphosilicate glass (PSG) or the like is formed.
A contact window to the source region 8 and the drain region 9 is formed, and a source wiring 12 and a drain wiring 13 made of aluminum or the like are formed to form a short channel type p channel.
The MIS transistor is completed.

In the method of the above embodiment, that is, the method of performing the lamp annealing of the ion implantation area after removing the gate oxide film 5 on the ion implantation area, the BF ₂ ⁺ implantation areas 108 and 109 are subjected to the lamp annealing means under the same conditions as the conventional one. P ⁺ type source region 8 and drain region 9 formed when heated and activated
The concentration profile of F ⁺ inside is the second from the result of Sims analysis.
As shown, before annealing, i.e. becomes BF ₂ ⁺ ion implantation shape with respect to the curve S shown the profile immediately and the surface of the F ⁺ concentrations shown in the curve A which hardly changes shape, F ⁺ of The surface concentration is greatly reduced compared to the conventional one. In the figure, the surface with a depth of 0 indicates the surface of the Si substrate, that is, the surface of the ion implantation region.

Therefore, the surface level formed on the surface of the source region 8 and the drain region 9 by F ⁺ existing on the surface of the source region 8 and the drain region 9 is significantly reduced as compared with the conventional one, and the shallow p ⁺ -type source The surface leak on the junction between the region 8 and the p ⁺ type drain region 9 is greatly reduced as compared with the conventional case.

The method of the present invention is also applicable to the manufacture of bipolar semiconductor devices.

〔The invention's effect〕

As described above, according to the present invention, a combination of boron difluoride ion implantation and lamp annealing is used to obtain a shallow p
In forming a short channel p-channel MIS transistor that forms the source and drain regions of the
Since the surface level due to fluorine ions is greatly reduced, the surface leak at the source and drain junctions is greatly reduced, and the performance of the short channel p-channel MIS transistor can be improved.

[Brief description of drawings]

1 (a) to (e) are process sectional views showing one embodiment of the method of the present invention, FIG. 2 is a profile diagram of F ⁺ concentration in the same embodiment, and FIGS. 3 (a) to (c). Is a process sectional view of the conventional method, and FIG. 4 is a profile diagram of F ⁺ concentration in the conventional method. In the figure, 1 is an n ⁻ type Si substrate, 2 is a field oxide film, 3 is an n type channel stopper, 4 is an element formation region, 5 is a gate oxide film, 6 is a resist pattern, 7 is a poly Si gate electrode, and 8 is p ⁺ type source region, 9 p ⁺ type drain region, 10 impurity oxide film for impurity block, 11 interlayer insulating film, 12 source line, 13 drain line, 108 and 109 BF ₂ ⁺ implantation region, .

Claims (1)

[Claims] 1. A thermal oxide film is formed on an n-type silicon substrate, boron difluoride is ion-implanted into the silicon substrate through the thermal oxide film, and then the thermal oxide film is removed. A method of manufacturing a semiconductor device, comprising: a step of activating a region into which boron difluoride is ion-implanted by heating by irradiation with light to form a p-type region.