JP3154139B2 - Method of manufacturing complementary MOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a complementary MOS (CMOS) semiconductor device, and more particularly to a method for forming a p-MOS junction and an n-type semiconductor using excimer laser doping (annealing).
The present invention relates to a method for manufacturing a CMOS semiconductor device capable of simultaneously processing MOS activation.

[0002]

2. Description of the Related Art Along with the high integration of LSI, MOSFET
In order to reduce the size, shallow junctions (Shallow Ju
nction) is needed.

Conventionally, such a shallow junction is formed mainly by a furnace annealing after ion implantation (II).

FIG. 2 is a sectional view showing a process for manufacturing a conventional CMOS transistor. First, as shown in FIG. 2A, an nMOS transistor and gate electrodes 5a and 5b to be pMOS transistors are formed on a p-type silicon substrate 1 having an n-well 3 and using a LOCOS oxide film 2 as an element isolation film. ing. A gate oxide film (SiO ₂ ) 4 is formed below the gate electrodes 5a and 5b.

A resist film 10a is applied on the pMOS transistor side (the side on which the n-well 3 is formed), and arsenic ions (As ⁺ ) are ion-implanted over the entire surface to form n ⁺ ion-implanted regions 6a, 6a.
b is formed.

Next, as shown in FIG. 2B, after the resist film 10a is removed, annealing is performed in a furnace to activate the ion-implanted region to thereby make the n ⁺ source (S) region 7a and the n ⁺ drain (D ) Form a region 7b.

Next, as shown in FIG.
A resist film 10b is applied on the transistor side, and boron ions (B ⁺ ) are implanted into the entire surface to form a p ⁺ ion implanted region 6.
c, 6d are formed.

Next, as shown in FIG. 2D, after removing the resist film 10b, annealing is performed to activate the ion-implanted region, thereby to form the p ⁺ source (S) region 7c and the p ⁺ drain (D). The region 7d is formed.

In this manner, the nMOS transistor and the pMOS transistor are formed on the same silicon substrate in a complementary manner.

[0010]

In the above-described conventional CMOS forming method, the masks of the resist films are respectively used as shown in FIG.
This step is required twice, that is, the step of FIG. 2C and the step of FIG. 2C. This mask step of the resist film is very complicated in the process and the productivity is low. Moreover, in the above-mentioned conventional method, in particular, the step shown in FIG.
The p ⁺ source and drain regions 7c and 7d in the step of FIG.
In the formation, it is difficult to form a high-concentration and shallow junction due to channeling of B (boron) atoms during ion implantation.

Therefore, the present invention provides a complementary MO capable of forming a shallow junction and reducing the number of times a resist mask is used.
An object of the present invention is to provide a method for manufacturing an S semiconductor device.

[0012]

SUMMARY OF THE INVENTION According to the present invention, there is provided a complementary MOS semiconductor device in which a MOS transistor of one conductivity type and a MOS transistor of opposite conductivity type are formed on the same substrate. One conductivity type MOS
A step of ion-implanting the impurity of the corresponding conductivity type into one of the element formation regions of the transistor and the MOS transistor of the opposite conductivity type, a step of forming a translucent insulating film on the ion-implanted region, and When excimer laser doping is performed on the entire surface using the light-transmitting insulating film as a mask, an impurity of a conductivity type opposite to the conductivity type of the impurity ions is implanted into another element formation region in a self-aligned manner, and annealing is performed. Simultaneously, a step of annealing the impurity ion implanted region via the light-transmitting insulating film is provided.

[0013]

According to the present invention, as shown in FIG.
Arsenic ions (As ⁺ ), which are n-type impurities, are implanted into the S transistor formation region, and then the As ⁺ ion implantation region is covered with a light-transmitting insulating film mask 11 such as SiO ₂ , and excimer laser doping is performed on the entire surface. ing. In this excimer laser doping step, p-type impurity ions (B ₂ H ₆ , or B ⁺ in which B ₂ F ₆ gas is dissociated) have a pM
Ions are implanted into the OS formation region, activated by annealing, and at the same time, As ⁺ under the light-transmitting insulating film mask 11.
The ion implantation regions (6a, 6b) are also annealed and activated by the laser transmitted through the mask.

Therefore, according to the present invention, the activation annealing step of the impurity implantation region of the nMOS region is performed simultaneously with the impurity implantation of the pMOS region and the activation annealing step thereof. The efficiency is improved. Moreover, because of excimer laser doping, it is possible to form a MOS having an ultra-shallow junction for both p and n.

The wavelength of the laser (XeCl laser) is 3
08 nm, the absorption coefficient for Si is α−10 ⁶ / cm
When energy of about 1 J / cm ² is applied, most of the energy is absorbed at a depth of about 100 nm from the Si surface and converted into heat, and heat is transmitted in the depth direction by heat conduction. At this time, the vicinity of the outermost surface is melted for about 100 tens of nanoseconds. Therefore, only a shallow region into which impurities are implanted by low-acceleration ion implantation can be melted for an extremely short time, and activated in a state in which redistribution of impurities is suppressed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing an embodiment of a CMOS transistor according to the present invention.

First, the CMOS according to the present invention will be described with reference to FIG.
As shown in FIG. 1, a LOCOS oxide film (SiO ₂ ) 2 is formed as an element isolation film on a p-type silicon substrate 1 by a normal process, and an n-well (Well) 3 and a gate oxide film (Si) are formed.
O ₂ ) 4 and a gate electrode 5 are formed.
The resist film 10 is formed in the element formation region (pMOS formation side)
And arsenic ions (As ⁺ ), which is an n-type impurity, with a dose of 2 × 10 ¹⁵ / c using the resist film 10 as a mask.
By ion implantation at m ² and implantation energy of 20 KeV, ion implantation regions 6a and 6b are formed.

Until this As ⁺ ion implantation, the source (S) / drain (D) junction and the gate have not been activated yet.

Then, as shown in FIG. 1B, the resist film 10 shown in FIG. 1A is removed, and X-rays having a wavelength of 308 nm are formed only on the nMOS formation side of the p-type silicon substrate.
eCl ultraviolet excimer laser to form the light-transmissive insulating mask _{(SiO 2, SiO 1 -x N} x, Si x N 1-x) or SOG (spin on glass) 11 that transmits.

Next, ultraviolet light (for example, XeCl excimer laser light) is applied from above to the doping gas B ₂ H ₆ gas for 4 hours.
Excimer laser doping (ELD) was performed by irradiating several times with a uniform light irradiation energy density of 00 mJ / cm ² .

As the doping gas B ₂ H ₆ gas,
A solution obtained by diluting B ₂ H ₆ to 5% in N ₂ gas has a partial pressure of 5 To.
Used at about rr.

The above ELD (pMOS side) or ELA
By (excimer laser annealing), doping and annealing of B are performed on the pMOS side, and active regions of p ⁺ source (S) / drain (D) regions 8a and 8b are formed. At the same time, n ⁺ ions on the nMOS side are formed. Injection region 6
a, 6b are annealed in a self-aligned manner. N ⁺ source (S) / drain (D) regions 7a and 7b are also formed.
In the ELD and ELA processes, the absorption coefficient of the insulating film mask 11 with respect to the excimer laser is set so that the energy of the excimer laser after passing through the insulating film is effective for ELA.
to optimize the additive composition ratio or in a SOG of N in _x N _1-x.

Next, since the light-transmitting insulating film mask 11 shown in FIG. 1B is not a resist, a normal passivation film (PSG) is formed on the entire surface by a CVD method, and then the PSG is dry-etched. Then, a contact hole (junction hole) was formed, and aluminum (Al) was further applied by vacuum evaporation and patterned to form an Al wiring.

Although the above embodiment shows a bulk type CMOS transistor, the present invention can be applied to a TFT (thin film transistor).

[0026]

As described above, according to the present invention,
The conventional CMOS manufacturing process reduces the number of mask forming processes by one, thereby improving the production efficiency and is suitably used for cleanliness in the manufacturing process.

Moreover, in the present invention, it is possible to form an ultra-shallow junction MOS or an ultra-thin TFT in the p and n impurity diffusion regions (source / drain regions).

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing one embodiment of a process for manufacturing a CMOS transistor of the present invention.

FIG. 2 is a cross-sectional view showing a main part of a conventional CMOS transistor manufacturing process.

[Explanation of symbols]

Reference Signs List 1 p-type silicon substrate 2 LOCOS oxide film (SiO ₂ ) 3 n well 4 gate oxide film (SiO ₂ ) 5 a, 5 b gate electrode 6 a, 6 b n ⁺ ion implantation region 7 an ⁺ source (S) region 7 b n ⁺ drain ( D) region 8a p ⁺ source (S) region 8b p ⁺ drain (D) region 10, 10a, 10b resist film 11 porous insulating film mask

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-14836 (JP, A) JP-A-6-104196 (JP, A) JP-A-5-283631 (JP, A) G. FIG. CAREY et al. 'Ultra-Shallow High-Concentration Bor on Profiles For CM OS Processing', IEEE ELECTRON DEVICE LETTERS, JUNE 1985, VOL. EDL-6, No. 6, pages 291 to 293 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 21/22 H01L 21/265 602 H01L 27/092 H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] 1. A complementary M transistor in which a MOS transistor of one conductivity type and a MOS transistor of opposite conductivity type are formed on the same substrate.
A step of ion-implanting the impurity of the corresponding conductivity type into one of the element formation regions of the one-conductivity-type MOS transistor and the opposite-conductivity-type MOS transistor that are isolated when the OS semiconductor device is manufactured; Forming a light-transmitting insulating film on the formed region, and performing excimer laser doping on the entire surface using the light-transmitting insulating film as a mask, and opposing the conductivity type of the impurity ions in the other element formation region. Self-aligned ion implantation of a conductive type impurity and annealing, and simultaneously annealing the impurity ion implanted region via the light-transmitting insulating film. Production method.