JPS60224271A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To implement the junction depth of 0.1mum or less of a source and drain junction even for a P-channel MIS type FET, by forming at least a part of a source and drain region by the ion implantation of indium or potassium. CONSTITUTION:A thick oxide film 102 for isolating elements is grown on the surface of a semiconductor substrate 101 by a selective oxidation method. After a gate insulating film 103 is grown, a polycrystal silicon layer 104 is grown on the insulating film 103 in a overlapped manner. Then a photoresist film 105 is applied and gate patterning is performed. With the photoresist as a mask, the polycrystal silicon layer 104 and the oxide film 103 are etched in this order, and a gate 10 is formed. With the gate 106 as a mask, indium ions are implanted, and an indium implanted layer 107 is formed. Then light of a halogen lamp, whose output results in the substrate temperature of about 1,000 deg.C, is projected, and the indium implanted layer is made active.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a semiconductor device and a method for manufacturing the same.

In particular, the present invention relates to a semiconductor device having a P-channel MIS type FE'l' and a method for manufacturing the same.

(Conventional technology) In recent years, with the increase in the density of semiconductor integrated circuits.

As the MIS type FB'l' is reduced in size, it becomes necessary to make the junction between the source and drain impurity layers shallower in order to reduce the bunch-through current. , in the conventional n-channel MIS type FIT.

Shallow impurity layers have been realized by ion-implanting elements such as arsenic or phosphorus, which have a small range in silicon crystals.

However, in the p-channel MI81JFBT, boron has traditionally been used as the implanted impurity, and it is difficult to realize a shallow source-drain impurity region due to the large range of boron in the silicon crystal. Ta. Furthermore, in the case of realizing a boron ion implantation layer with a practically necessary concentration in an MIa type FBT, the junction depth is 0.2μ.
It is reported in the Proceedings of the 44th Autumn 1982 Society of Applied Physics Society, P407 Lecture 28a, -M-10 that the limit is approximately m.

Therefore, when manufacturing a p-channel MI8WFET, if the source and drain are implanted with boron ions, it is very difficult to reduce the junction depth to 0.1 μTrL or less, and it is difficult to reduce the junction depth to 0.1μTrL or less. This is a major obstacle to raising the bar.

(Effects of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to reduce the junction depth of the source and drain to 0.1 even in p-channel MISmFET.
The object of the present invention is to provide a highly densely integrated semiconductor device that realizes micrometers or less.

(Structure of the Invention) A semiconductor device according to a first aspect of the present invention is a semiconductor device in which a p-channel MIS type FIT is formed on the whole surface of an n-type silicon substrate, in which at least a part of the source/drain region of the FET is formed. The region is formed by implanting indium (or gallium) ions.

A semiconductor device according to a second aspect of the present invention is a semiconductor device in which a p-channel MISJFE'l' is formed on the whole surface of an n-type silicon substrate, in which at least a part of the source and drain regions of the FET is made of indium (or gallium). ) formed by ion implantation, and a source/drain region formed by ion implantation of indium (or gallium), away from the channel side end directly under the gate of the PBT, and in contact with the source/drain region formed by ion implantation of indium (or gallium). The structure includes a boron ion-implanted layer.

A semiconductor device according to a third aspect of the present invention is a semiconductor device in which a p-channel MIS type FE'l' is formed on the entire surface of an n-type silicon substrate, in which the FET has at least a part of its source/drain region made of indium ( At least part of the surface of the source/drain region formed by ion implantation of indium (or gallium) and the source/drain region formed by ion implantation of indium (or gallium) is spaced apart from the channel side end of the FB'l'. and a silicide layer formed.

A method for manufacturing a semiconductor device according to a fourth aspect of the present invention is a method for manufacturing a semiconductor device in which a p-channel MIS type FET is formed on the entire surface of an n-type silicon substrate. A process of forming an oxide film, a gate oxide film, and a gate polycrystalline silicon, a process of ion-implanting indium (or gallium) to form an indium (or gallium) injection layer, and a substrate temperature of 900°C to 1200°C.
The method includes a step of performing a short heat treatment at a temperature of 1 minute or less.

A method for manufacturing a semiconductor device according to a fifth aspect of the present invention.

Full-face Kp channel MIS type FB of n-type silicon substrate
In a method of manufacturing a semiconductor device in which 'l' is formed, n
A step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of a type semiconductor substrate, and a step of ion-implanting indium (or gallium) to form an indium (or gallium) implantation layer. , substrate temperature 900
The process includes a step of performing heat treatment for a short time within 1 minute at a temperature of 1200°C to 1200°C, and a step of performing heat treatment for 1 minute or more at a temperature of 750°C to 900°C.

A method for manufacturing a semiconductor device according to a sixth aspect of the present invention.

P channel MIa type F on the whole surface of n type silicon substrate
In a method of manufacturing a semiconductor device in which F'l' is formed,
A step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of an n-type semiconductor substrate, and a step of ion-implanting indium (or gallium) to form an indium (or gallium) implantation layer. , a step of depositing a CVD oxide film on the entire surface, and anisotropic etching.
A process of etching the oxide film and leaving the CVD oxide film only on the side surfaces of the gate electrode, a process of implanting boron ions to form a boron ion implantation layer at a distance of the thickness of the oxide film from the gate sidewalls, and a heat treatment process. It consists of:

A method for manufacturing a semiconductor device according to a seventh aspect of the present invention.

P-channel MI8fJI on the entire surface of the n-type silicon substrate
FB'f is formed in 9% in semiconductor device manufacturing method.
a step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of a nm semiconductor substrate; a step of ion-implanting indium (or gallium) to form an indium (or gallium) implantation layer; CVD all over
IcV by the process of depositing an oxide film and anisotropic etching
Etch the D oxide film and apply CVD only to the sides of the gate electrode.
A process of leaving an oxide film, a process of depositing a high melting point metal layer that forms silicide on the entire surface, a process of heat treatment to anneal the ion implantation layer and siliciding the high melting point metal on silicon, and a process of high melting point metal layer that does not become silicide. The method includes a step of removing metal.

(Principle and operation of the invention) The range of indium and gallium in silicon crystal is the same as or less than that of arsenic, and furthermore, since the thermal diffusion coefficient is small, bonding of 0.1 μm or less can be easily formed. It can be realized. However, the solid solubility of indium and gallium in silicon crystal is 3×1, respectively.c
The value is about two orders of magnitude lower than that of IIL-3 and 3×101·0fK-” boron. Therefore, when using the device according to the present invention in an integrated circuit, the layer resistance of the source and drain is limited due to circuit design constraints. If it is necessary to lower the resistance even further, the layer resistance can be reduced by implanting high-concentration boron ions into the necessary areas or by forming a silicide layer on the source/drain.However, if the high-concentration boron The ion-implanted layer or silicide layer should be provided with a gap between it and the gate on the plane, and the impurity layer of the source and drain should be made shallow so as not to impair the effect of reducing the punch-through current. No.

In addition, the diffusion coefficients of indium and gallium in silicon crystal are smaller than boron, but compared to arsenic, they are 2 to 3
twice as big. Therefore, activation of the ion-implanted layer must be performed in a short time of one minute or less. This purpose can be achieved by irradiation with halogen lamp light, xenon lamp light, laser light, and thermal radiation.

In addition, in the short time high temperature heat treatment, the heat treatment time.

The pn junction leakage current increases depending on the temperature.

Therefore, in such a case, the leakage current can be reduced to a level that does not pose a practical problem by performing heat treatment at a substrate temperature of 750 DEG C. to 900 DEG C. for 1 minute or more.

Moreover, the implanted impurities are not re-diffused by this heat treatment at 750° C. to 900° C.

(Example) Hereinafter, an example of the present invention will be described with reference to one drawing.

FIGS. 1(a) to 1(C) are cross-sectional views shown in the order of steps to explain the first embodiment of the present invention and its manufacturing method.

First, as shown in FIG. 1(a), a thick oxide film 102 for element isolation is grown on the surface of a semiconductor substrate 101 to a thickness of several thousand angstroms by selective oxidation.

Next, as shown in FIG. 1(b), the gate insulating film 103
After growing hundreds of large crystals, polycrystalline silicon 1 is layered on top of it.
04 to several thousand λ. Next, a photoresist 105 is applied and gate patterned. Then, as shown in FIG. 1C, the polycrystalline silicon 104 and the oxide film 103 are etched in this order using the photoresist as a mask to form a gate 106.

Next, using the gate 106 as a mask, apply 30% indium.
Ions are implanted at KeV so that the peak of the concentration distribution is about 10"cIc" to form an indium implanted layer 107. Further, even if gallium is used instead of indium, a gallium-implanted layer with similar effects can be obtained.

Next, the indium implanted layer is activated by irradiating the substrate with halogen lamp light having an output such that the substrate temperature reaches about 1000° C. for about 10 seconds.

As described above, a semiconductor device is obtained in which at least a part of the source/drain region of fiFB'l' has a region 107 formed by indium (or gallium) ion implantation.

Furthermore, the semiconductor device obtained above was heated at a substrate temperature of 800°C for 3
By heat-treating in a furnace for about 0 minutes, the pn junction leakage current at the source e-drain can be further reduced.
The mechanical properties of the element can be further improved. Note that the heat treatment for activation is 900℃~12℃ due to manufacturing technology.
The heat treatment for improving characteristics can be carried out at 750°C to 900°C as described above.

Figures 2 (a) to (d) are cross-sectional views shown in order of steps to explain the second embodiment of the present invention and its manufacturing method.

First, as shown in Figure 2(a), the phosphorus concentration is 10I4cR.
Acid for element isolation is applied to the n-type silicon substrate 201 of about s -
The thermal oxide film 202 is grown by a selective oxidation method to several thousand thick, and then a thermal oxide film 20B is grown to several hundred thick as a gate insulating film, and polycrystalline silicon is grown on the entire surface.

A gate 204 is formed by patterning the gate by photolithography and etching the polycrystalline silicon and gate oxide film. Next, add 30 indium to all
The indium implanted layer 205 is formed by implanting KeV ions to a concentration distribution peak of about 10"m-". At this time, even if gallium is used instead of indium as the implanted ions, a gallium implanted layer with similar effects can be obtained.

Next, as shown in Figure 2(b), for example, low voltage C is applied to the entire surface.
A silicon oxide film 206 is grown to a thickness of several thousand amps by the VD method.

Next, as shown in FIG. 2C, the oxide film 206 is etched by anisotropic etching, leaving the oxide film 206 only on the side surfaces of the gate 204.

Next, as shown in Figure 2(d), 30% boron was applied to the entire surface.
Key, ions are implanted to a surface concentration of about 10 CF. In this case, a boron ion implantation layer 207 is formed at a distance equal to the thickness of the oxide film 206 from the side surface of the gate.

Next, halogen lamp light is irradiated to raise the substrate temperature to 1000°C.
After about 10 seconds of annealing, a real or terrible semiconductor device can be obtained.

In the PET included in the semiconductor device of this embodiment, at least a part of the source/drain region has an impurity region 205 formed by ion implantation of indium (or gallium).
It is formed to include a boron ion-implanted layer 1207 formed away from the channel side end immediately below the gate and in contact with the source/drain 205 formed by the indium (or gallium) ion implantation. Since this embodiment is curved, a shallow junction of 0.1 μm or less can be easily realized. In addition, since the layer 207 is formed of highly concentrated boron to cope with the fact that the layer resistance is higher than that of conventional sources and drains formed of boron, the layer resistance can be lowered. Another advantage of this structure is that it can be formed in a self-aligned manner.

FIGS. 3(a) and 3(b) show a third embodiment of the present invention.
FIG. 3 is a cross-sectional view shown in order of steps to explain the manufacturing method thereof.

First, as shown in FIG. 3(a),
Source/drain impurity layers 305 and sidewalls 306 in which indium (or gallium) is implanted are formed using the same European process as shown in FIG.

Next, several hundred molybdenum 308 molecules are grown on the entire surface.

Next, as shown in FIG. 3(b), the impurity layer 30 in which indium (or gallium) was implanted was irradiated with halogen lamp light for about 10 seconds at an output that brought the substrate temperature to about 100°C.
At the same time as performing the heat treatment in step 5, a silicide layer 307 is formed. At this time, the molybdenum 308 attached to the sidewall 306 does not become silicide, so the molybdenum 308
If only 08 is selectively removed by etching, the semiconductor device of this example is obtained.

Furthermore, by performing furnace annealing at a substrate temperature of 800° C. for about 30 minutes, it is possible to significantly reduce the pn junction leakage current at the source and drain, thereby improving the electrical characteristics of the device. .

FBfl contained in the semiconductor device obtained in this example
l-J, source φ At least 4 portions of the drain region include an impurity layer 305 formed by ion implantation of indium (or gallium), and at least a portion of the surface of the region 305 has an impurity layer 305 on the channel side end of F]3T. The film is formed by a silicide layer 307 formed separately from the silicide layer 307. Therefore, as in the second embodiment, shallow junction source/drain regions can be easily formed, and the somewhat high layer resistance can be lowered by forming silicide on a part of the surface of the source/drain regions. Nari nine.

Although molybdenum was used as the high melting point metal for forming the silicide layer in this embodiment, the same effect can be obtained by using a high melting point metal such as platinum or tungsten.

In addition, in the first to third embodiments, the heat treatment for 1 minute or less at 900"L above the substrate temperature was performed by irradiation with halogen lamp light, but xenon lamp light, laser light irradiation, electron beam irradiation, The same process can be carried out using a short-time heat treatment method such as annealing or thermal radiation.

(Effects of the Invention) As explained above, according to the present invention, the source/drain impurity layer can be made shallow without degrading the characteristics.
It has become possible to significantly improve the degree of integration of semiconductor integrated circuits.

[Brief explanation of the drawing]

Figure 1 (a) to (C), Figure 2 (a) to (d), Figure 3
Figures (al and b) are sectional views shown in order of steps to explain the embodiment of the present invention and its manufacturing method. 101.201...Silicon substrate, 102.10
3゜202, 203.206.306...Oxide film, 104.106゜204...Polycrystalline silicon, 105...Photoresist, 107.20
5.207.305... Impurity layer. 307...Cryside layer% 308...
·molybdenum. A kri lθri Kr hard jg figure 2Iri gr fig.5

Claims (7)

[Claims] (1) P-channel MIS on the whole surface of the n-type silicon substrate
In the semiconductor device in which the type FE'l' is formed, the I
i' A semiconductor device characterized in that at least a part of the source/drain region of the ICT is a region formed by indium (or gallium) ion implantation. (2) P-channel MI on the entire surface of the n-type silicon substrate
In the semiconductor device in which an 8-type F 13 T is formed, the FET has at least a part of the source/drain region formed by indium (or gallium) ion implantation, and a channel side end directly under the gate of the PET. A semiconductor device comprising: a boron ion-implanted layer formed separately from the source/drain/region formed by indium (or gallium) ion implantation. (3) P-channel/channel MMI on the entire surface of the n-type silicon substrate
8! ! ! ! In a semiconductor device in which an FBT is formed, the FET has a region in which at least a part of the source/drain region is formed by ion implantation of indium (or gallium), and a region formed by ion implantation of the indium (or gallium). A semiconductor device comprising a silicide layer formed on at least a part of the surface of the source/drain region separated from the channel side end of the FE'l'. (4) P-channel MI on the entire surface of the n-type silicon substrate
A method for manufacturing a semiconductor device in which an 811FET is formed includes a step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of an n-type semiconductor substrate, and a step of ion-implanting indium (or gallium) to remove indium. (
or gallium) and the substrate temperature 9.
1. A method of manufacturing a semiconductor device, comprising the step of performing short-time heat treatment at 00° C. to 1200° C. for less than 1 minute. (5) P-channel MIS on the entire surface of the n-type silicon substrate
A method for manufacturing a semiconductor device in which type FE'l' is formed includes a step of forming an oxide film for element isolation, a gate oxide film, and gate polycrystalline silicon on the surface of an n-type semiconductor substrate, and a step of forming an oxide film for element isolation, a gate oxide film, and gate polycrystalline silicon on the surface of an n-type semiconductor substrate, and Ion implanted indium (
or gallium) and the substrate temperature 9.
1. A method for manufacturing a semiconductor device, comprising the steps of performing short-time heat treatment at 00° C. to 1200° C. for one minute or less, and subsequently performing heat treatment at a substrate temperature of 750° C. to 900° C. for one minute or more. (6) P-channel MIS on the entire surface of the n-type silicon substrate
In a method of manufacturing a semiconductor device in which a type FET is formed,
A step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of an n-type semiconductor substrate, and a step of ion-implanting indium (or gallium) to form an indium (or gallium) implantation layer. , a step of depositing a CVD oxide film on the entire surface and anisotropic etching
D oxide film is etched and CVD is applied only to the sides of the gate electrode.
Manufacturing a semiconductor device comprising: leaving an oxide film; implanting boron ions to form a boron ion-implanted layer at a distance from the gate sidewall by the thickness of the oxide film; and heat-treating. Method. (7) P-channel MI on the entire surface of the n-type silicon substrate
In a method of manufacturing a semiconductor device in which an S-type FF1iT is formed, a step of forming an oxide film for element isolation, a gate oxide film, and a gate polycrystalline silicon on the surface of an n-type semiconductor substrate;
J) Processing the CVD oxide film by ion-implanting indium (or gallium) to form an indium (or gallium) injection layer, depositing a CVD oxide film on the entire surface, and anisotropic etching, A process of etching and leaving a CVD oxide film only on the side surfaces of the gate electrode, a process of depositing a high melting point metal layer to form silicide on the entire surface, and a heat treatment to anneal the ion implantation layer and silicide the high melting point metal on the silicon. 1. A method for manufacturing a semiconductor device, comprising: a step of removing a high-melting point metal that does not become a silicide.