JPS60101749U - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS60101749U
JPS60101749U JP19378583U JP19378583U JPS60101749U JP S60101749 U JPS60101749 U JP S60101749U JP 19378583 U JP19378583 U JP 19378583U JP 19378583 U JP19378583 U JP 19378583U JP S60101749 U JPS60101749 U JP S60101749U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
recorded
utility
mounting base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19378583U
Other languages
English (en)
Inventor
富岡　秀宏
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP19378583U priority Critical patent/JPS60101749U/ja
Publication of JPS60101749U publication Critical patent/JPS60101749U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、従来のチップマウントのパッケージ断面図、
ａはセラミックパッケージの断面図、ｂはベースリボン
を用いたプラスチックモールドパッケージの断面図であ
り、第２図は、基体の表裏両面にチップをマウントした
本考案の断面図、ａはセラミックパッケージの断面図、
ｂはベースリボンを用いたプラスチックールドパッケー
ジの断面図である。 １・・・集積回路チップ、２・・・基体（セラミック）
１，２’・・・基体（ベースリボン）、３・・・キャッ
プ、４・・・リード、５・・・ボンディングワイヤ、６
・・・プラスチックモールド。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体集積回路チップをマウント用基体の表側と裏側に
    夫々マウントしたことを特徴とする集積回路装置。
JP19378583U 1983-12-16 1983-12-16 集積回路装置 Pending JPS60101749U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19378583U JPS60101749U (ja) 1983-12-16 1983-12-16 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19378583U JPS60101749U (ja) 1983-12-16 1983-12-16 集積回路装置

Publications (1)

Publication Number Publication Date
JPS60101749U true JPS60101749U (ja) 1985-07-11

Family

ID=30416707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19378583U Pending JPS60101749U (ja) 1983-12-16 1983-12-16 集積回路装置

Country Status (1)

Country Link
JP (1) JPS60101749U (ja)

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