JPS598908B2 - バブル・メモリ・チツプの製造方法 - Google Patents

バブル・メモリ・チツプの製造方法

Info

Publication number
JPS598908B2
JPS598908B2 JP314380A JP314380A JPS598908B2 JP S598908 B2 JPS598908 B2 JP S598908B2 JP 314380 A JP314380 A JP 314380A JP 314380 A JP314380 A JP 314380A JP S598908 B2 JPS598908 B2 JP S598908B2
Authority
JP
Japan
Prior art keywords
layer
dielectric insulator
resist
pattern
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP314380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55132588A (en
Inventor
ジ−ン・パトリツク・ボニ−
スチ−ブン・コンラン・シヤウスタ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Publication of JPS55132588A publication Critical patent/JPS55132588A/ja
Publication of JPS598908B2 publication Critical patent/JPS598908B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/32Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
    • H01F41/34Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Magnetic Films (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP314380A 1979-03-27 1980-01-17 バブル・メモリ・チツプの製造方法 Expired JPS598908B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2399579A 1979-03-27 1979-03-27
US23995 1979-03-27

Publications (2)

Publication Number Publication Date
JPS55132588A JPS55132588A (en) 1980-10-15
JPS598908B2 true JPS598908B2 (ja) 1984-02-28

Family

ID=21818297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP314380A Expired JPS598908B2 (ja) 1979-03-27 1980-01-17 バブル・メモリ・チツプの製造方法

Country Status (6)

Country Link
JP (1) JPS598908B2 (de)
AU (1) AU532007B2 (de)
CA (1) CA1135852A (de)
DE (1) DE2947952C2 (de)
FR (1) FR2452762A1 (de)
GB (1) GB2046040B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539556B1 (fr) * 1983-01-13 1986-03-28 Commissariat Energie Atomique Procede de fabrication de conducteurs pour circuits integres, en technologie planar

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4178635A (en) * 1976-06-14 1979-12-11 Hewlett-Packard Company Planar and near planar magnetic bubble circuits
US4088490A (en) * 1976-06-14 1978-05-09 International Business Machines Corporation Single level masking process with two positive photoresist layers
US4092442A (en) * 1976-12-30 1978-05-30 International Business Machines Corporation Method of depositing thin films utilizing a polyimide mask

Also Published As

Publication number Publication date
DE2947952A1 (de) 1980-10-09
GB2046040A (en) 1980-11-05
AU5501180A (en) 1980-10-02
JPS55132588A (en) 1980-10-15
GB2046040B (en) 1983-03-16
CA1135852A (en) 1982-11-16
AU532007B2 (en) 1983-09-15
DE2947952C2 (de) 1985-01-10
FR2452762B1 (de) 1985-05-10
FR2452762A1 (fr) 1980-10-24

Similar Documents

Publication Publication Date Title
US4508815A (en) Recessed metallization
KR20000011739A (ko) 배선패턴형성방법및그방법에따라형성된소자
KR20060009862A (ko) Mram 장치들의 전자기 소자들의 상부의 도전 층들을접촉하는 방법
US4007103A (en) Planarizing insulative layers by resputtering
US3602635A (en) Micro-circuit device
JPH0691033B2 (ja) 半導体構造上の接点スタッドの製造方法
US4251319A (en) Bubble memory chip and method for manufacture
KR19980028939A (ko) 게이트전극의 제조방법 및 그에 따라 제조된 게이트 구조
US4298436A (en) Method of forming insulated conductors in a conductive medium and article thus formed
US6329280B1 (en) Interim oxidation of silsesquioxane dielectric for dual damascene process
JPS59181032A (ja) 集積回路の電気接触口上に相互接続線を配置する方法
JPH051614B2 (de)
US4317700A (en) Method of fabrication of planar bubble domain device structures
US4174562A (en) Process for forming metallic ground grid for integrated circuits
US3675319A (en) Interconnection of electrical devices
JPS598908B2 (ja) バブル・メモリ・チツプの製造方法
JPH0575237A (ja) 導体パターン形成方法
US3974517A (en) Metallic ground grid for integrated circuits
JPS6146081A (ja) ジヨセフソン接合素子の製造方法
JPH0548247A (ja) 導体パターン形成方法
JPH07297590A (ja) 同軸構造の配線の形成方法
US4261096A (en) Process for forming metallic ground grid for integrated circuits
KR960008559B1 (ko) 반도체 소자의 미세 콘택홀 형성방법
TWI223409B (en) Method for forming DRAM cell bit line and bit line contact structure
KR950013385B1 (ko) 고집적 소자용 콘택형성방법