FR2452762A1 - Procede de formation d'un composant de memorisation du type memoire a bulles et composant realise par ce procede - Google Patents

Procede de formation d'un composant de memorisation du type memoire a bulles et composant realise par ce procede

Info

Publication number
FR2452762A1
FR2452762A1 FR8006647A FR8006647A FR2452762A1 FR 2452762 A1 FR2452762 A1 FR 2452762A1 FR 8006647 A FR8006647 A FR 8006647A FR 8006647 A FR8006647 A FR 8006647A FR 2452762 A1 FR2452762 A1 FR 2452762A1
Authority
FR
France
Prior art keywords
layer
protective coating
diagram
conductive
coarse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8006647A
Other languages
English (en)
Other versions
FR2452762B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Publication of FR2452762A1 publication Critical patent/FR2452762A1/fr
Application granted granted Critical
Publication of FR2452762B1 publication Critical patent/FR2452762B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
    • H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Magnetic Films (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'INVENTION CONCERNE LES PROCEDES DE FORMATION DE COMPOSANTS A MEMOIRE A BULLES. LE PROCEDE CONSISTE A DEPOSER UNE PREMIERE COUCHE DIELECTRIQUE 12 SUR UN SUBSTRAT DE GRENAT 10. ON FORME UNE SECONDE COUCHE DIELECTRIQUE 14 SUR LA PREMIERE. ON FORME SUR LA SECONDE COUCHE UN DIAGRAMME DE REVETEMENT PROTECTEUR, PUIS ON EFFECTUE UNE GRAVURE SUIVANT DES PAROIS RECTILIGNES PAR UN MOYEN QUI NE DECAPE PAS LA PREMIERE COUCHE. ON DEPOSE UNE COUCHE CONDUCTRICE 20 DANS LES ENTAILLES FORMEES LORS DE LA GRAVURE ET SUR LA SURFACE DU DIAGRAMME INITIAL DE REVETEMENT PROTECTEUR. ON APPLIQUE UN MATERIAU DE REVETEMENT PROTECTEUR GROSSIER SUR LA PARTIE RELATIVEMENT PETITE DESTINEE A ETRE COUVERTE PAR UN DIAGRAMME CONDUCTEUR, EN CONCORDANCE GROSSIERE AVEC LA COUCHE CONDUCTRICE A PRESERVER. ON DECAPE CHIMIQUEMENT CETTE COUCHE CONDUCTRICE DANS LES REGIONS NON COUVERTES PAR LE MATERIAU DE REVETEMENT PROTECTEUR GROSSIER. ENFIN, ON RETIRE LE MATERIAU DE REVETEMENT PROTECTEUR GROSSIER RESTANT EN MEME TEMPS QUE LA COUCHECONDUCTRICE AFIN DE LAISSER UNE SURFACE PLANE CONSTITUEE D'UN DIAGRAMME CONDUCTEUR AU NIVEAU D'UNE SURFACE DANS LE MEME PLAN QUE LA SURFACE DE LA DEUXIEME COUCHE.
FR8006647A 1979-03-27 1980-03-25 Procede de formation d'un composant de memorisation du type memoire a bulles et composant realise par ce procede Granted FR2452762A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2399579A 1979-03-27 1979-03-27

Publications (2)

Publication Number Publication Date
FR2452762A1 true FR2452762A1 (fr) 1980-10-24
FR2452762B1 FR2452762B1 (fr) 1985-05-10

Family

ID=21818297

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8006647A Granted FR2452762A1 (fr) 1979-03-27 1980-03-25 Procede de formation d'un composant de memorisation du type memoire a bulles et composant realise par ce procede

Country Status (6)

Country Link
JP (1) JPS598908B2 (fr)
AU (1) AU532007B2 (fr)
CA (1) CA1135852A (fr)
DE (1) DE2947952C2 (fr)
FR (1) FR2452762A1 (fr)
GB (1) GB2046040B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539556A1 (fr) * 1983-01-13 1984-07-20 Commissariat Energie Atomique Procede de fabrication de conducteurs pour circuits integres, en technologie planar

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
FR2376447A1 (fr) * 1976-12-30 1978-07-28 Ibm Procede de formation d'une configuration de films minces sur un substrat utilisant un masque de polyimide
FR2394892A1 (fr) * 1976-06-14 1979-01-12 Ibm Procede de depot multiple par masquage

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4178635A (en) * 1976-06-14 1979-12-11 Hewlett-Packard Company Planar and near planar magnetic bubble circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
FR2394892A1 (fr) * 1976-06-14 1979-01-12 Ibm Procede de depot multiple par masquage
FR2376447A1 (fr) * 1976-12-30 1978-07-28 Ibm Procede de formation d'une configuration de films minces sur un substrat utilisant un masque de polyimide

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539556A1 (fr) * 1983-01-13 1984-07-20 Commissariat Energie Atomique Procede de fabrication de conducteurs pour circuits integres, en technologie planar
EP0114133A1 (fr) * 1983-01-13 1984-07-25 Commissariat à l'Energie Atomique Procédé de fabrication de conducteurs pour circuits intégrés, en technologie planar
US4533431A (en) * 1983-01-13 1985-08-06 Commissariat A L'energie Atomique Process for producing conductors for integrated circuits using planar technology

Also Published As

Publication number Publication date
DE2947952A1 (de) 1980-10-09
GB2046040A (en) 1980-11-05
AU5501180A (en) 1980-10-02
JPS55132588A (en) 1980-10-15
GB2046040B (en) 1983-03-16
CA1135852A (fr) 1982-11-16
AU532007B2 (en) 1983-09-15
JPS598908B2 (ja) 1984-02-28
DE2947952C2 (de) 1985-01-10
FR2452762B1 (fr) 1985-05-10

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Legal Events

Date Code Title Description
ST Notification of lapse