FR2449971A1 - Procede d'attaque en une fois pour former une structure mesa ayant une paroi a plusieurs etages - Google Patents
Procede d'attaque en une fois pour former une structure mesa ayant une paroi a plusieurs etagesInfo
- Publication number
- FR2449971A1 FR2449971A1 FR8003835A FR8003835A FR2449971A1 FR 2449971 A1 FR2449971 A1 FR 2449971A1 FR 8003835 A FR8003835 A FR 8003835A FR 8003835 A FR8003835 A FR 8003835A FR 2449971 A1 FR2449971 A1 FR 2449971A1
- Authority
- FR
- France
- Prior art keywords
- mesa structure
- semiconductor
- forming
- stage
- attack method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Abstract
L'INVENTION CONCERNE UN PROCEDE DE FORMATION D'UNE STRUCTURE MESA A PLUSIEURS ETAGES DANS UN SEMI-CONDUCTEUR. SELON L'INVENTION, DES PAROIS DE STRUCTURE MESA A PLUSIEURS ETAGES SONT FORMEES EN PRETRAITANT DES PORTIONS CHOISIES DU SEMI-CONDUCTEUR 110 QUI DOIVENT ETRE RETIREES POUR FORMER LA STRUCTURE MESA AFIN DE CHANGER LA VITESSE MOYENNE D'ENLEVEMENT DU MATERIAU PRETRAITE DANS L'ETAPE SUBSEQUENTE D'ENLEVEMENT; ON PROTEGE DES PORTIONS DE LA SURFACE DU MATERIAU SEMI-CONDUCTEUR PAR UN MASQUE 130, TANDIS QUE L'ON LAISSE SANS PROTECTION LES PORTIONS 122, 132 QUI DOIVENT ETRE RETIREES POUR FORMER LES PLATEAUX; ON EXPOSE LA PASTILLE DU SEMI-CONDUCTEUR A UNE SEULE ETAPE D'ENLEVEMENT QUI RETIRE LE MATERIEU PRETRAITE 118 A DES VITESSES DIFFERENTES DU MATERIAU NON PRETRAITE 116. L'INVENTION S'APPLIQUE NOTAMMENT A LA FORMATION DE TRANSISTORS.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1414479A | 1979-02-22 | 1979-02-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2449971A1 true FR2449971A1 (fr) | 1980-09-19 |
Family
ID=21763796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8003835A Pending FR2449971A1 (fr) | 1979-02-22 | 1980-02-21 | Procede d'attaque en une fois pour former une structure mesa ayant une paroi a plusieurs etages |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS55115335A (fr) |
DE (1) | DE3005627A1 (fr) |
FR (1) | FR2449971A1 (fr) |
GB (1) | GB2042805A (fr) |
IT (1) | IT1212404B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3030876A1 (fr) * | 2014-12-22 | 2016-06-24 | Commissariat Energie Atomique | Procede de realisation de motifs |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8624637D0 (en) * | 1986-10-14 | 1986-11-19 | Emi Plc Thorn | Electrical device |
US4996627A (en) * | 1989-01-30 | 1991-02-26 | Dresser Industries, Inc. | High sensitivity miniature pressure transducer |
EP2717314A1 (fr) * | 2012-10-03 | 2014-04-09 | ABB Technology AG | Procédé de production d'une terminaison de jonction pour un dispositif semi-conducteur de puissance et dispositif semi-conducteur de puissance correspondant |
FR2998090A1 (fr) * | 2013-06-26 | 2014-05-16 | Commissariat Energie Atomique | Procede de structuration de surface par modification locale de selectivite a la gravure |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1562282A (fr) * | 1967-02-25 | 1969-04-04 | ||
FR2024961A1 (fr) * | 1968-11-29 | 1970-09-04 | Philips Nv | |
GB1211499A (en) * | 1969-03-07 | 1970-11-04 | Standard Telephones Cables Ltd | A method of manufacturing semiconductor devices |
FR2356276A1 (fr) * | 1976-06-21 | 1978-01-20 | Gen Electric | Dispositif semi-conducteur a tension de rupture elevee |
JPS5360580A (en) * | 1976-11-11 | 1978-05-31 | Nec Corp | Etching method of semiconductor material |
JPS53120280A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
-
1980
- 1980-01-29 IT IT8019547A patent/IT1212404B/it active
- 1980-02-15 DE DE19803005627 patent/DE3005627A1/de not_active Withdrawn
- 1980-02-18 JP JP1966180A patent/JPS55115335A/ja active Pending
- 1980-02-19 GB GB8005581A patent/GB2042805A/en not_active Withdrawn
- 1980-02-21 FR FR8003835A patent/FR2449971A1/fr active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1562282A (fr) * | 1967-02-25 | 1969-04-04 | ||
FR2024961A1 (fr) * | 1968-11-29 | 1970-09-04 | Philips Nv | |
GB1211499A (en) * | 1969-03-07 | 1970-11-04 | Standard Telephones Cables Ltd | A method of manufacturing semiconductor devices |
FR2356276A1 (fr) * | 1976-06-21 | 1978-01-20 | Gen Electric | Dispositif semi-conducteur a tension de rupture elevee |
JPS5360580A (en) * | 1976-11-11 | 1978-05-31 | Nec Corp | Etching method of semiconductor material |
JPS53120280A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
Non-Patent Citations (1)
Title |
---|
ABJP/78 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3030876A1 (fr) * | 2014-12-22 | 2016-06-24 | Commissariat Energie Atomique | Procede de realisation de motifs |
WO2016102628A1 (fr) * | 2014-12-22 | 2016-06-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de réalisation de motifs |
US10336023B2 (en) | 2014-12-22 | 2019-07-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for creating patterns |
Also Published As
Publication number | Publication date |
---|---|
JPS55115335A (en) | 1980-09-05 |
GB2042805A (en) | 1980-09-24 |
DE3005627A1 (de) | 1980-09-04 |
IT8019547A0 (it) | 1980-01-29 |
IT1212404B (it) | 1989-11-22 |
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